lib/Target/CellSPU/SPUISelLowering.h

   1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Cell SPU uses to lower LLVM code into
  11 // a selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SPU_ISELLOWERING_H
  16 #define SPU_ISELLOWERING_H
  17
  18 #include "llvm/Target/TargetLowering.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20 #include "SPU.h"
  21
  22 namespace llvm {
  23   namespace SPUISD {
  24     enum NodeType {
  25       // Start the numbering where the builting ops and target ops leave off.
  26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27
  28       // Pseudo instructions:
  29       RET_FLAG,                 ///< Return with flag, matched by bi instruction
  30
  31       Hi,                       ///< High address component (upper 16)
  32       Lo,                       ///< Low address component (lower 16)
  33       PCRelAddr,                ///< Program counter relative address
  34       AFormAddr,                ///< A-form address (local store)
  35       IndirectAddr,             ///< D-Form "imm($r)" and X-form "$r($r)"
  36
  37       LDRESULT,                 ///< Load result (value, chain)
  38       CALL,                     ///< CALL instruction
  39       SHUFB,                    ///< Vector shuffle (permute)
  40       SHUFFLE_MASK,             ///< Shuffle mask
  41       CNTB,                     ///< Count leading ones in bytes
  42       PREFSLOT2VEC,             ///< Promote scalar->vector
  43       VEC2PREFSLOT,             ///< Extract element 0
  44       SHLQUAD_L_BITS,           ///< Rotate quad left, by bits
  45       SHLQUAD_L_BYTES,          ///< Rotate quad left, by bytes
  46       VEC_ROTL,                 ///< Vector rotate left
  47       VEC_ROTR,                 ///< Vector rotate right
  48       ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
  49       ROTBYTES_LEFT_BITS,       ///< Rotate bytes left by bit shift count
  50       SELECT_MASK,              ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
  51       SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
  52       // Markers: These aren't used to generate target-dependent nodes, but
  53       // are used during instruction selection.
  54       ADD64_MARKER,             ///< i64 addition marker
  55       SUB64_MARKER,             ///< i64 subtraction marker
  56       MUL64_MARKER,             ///< i64 multiply marker
  57       LAST_SPUISD               ///< Last user-defined instruction
  58     };
  59   }
  60
  61   //! Utility functions specific to CellSPU:
  62   namespace SPU {
  63     SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
  64                              EVT ValueType);
  65     SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
  66                              EVT ValueType);
  67     SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
  68                              EVT ValueType);
  69     SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
  70                             EVT ValueType);
  71     SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
  72                               EVT ValueType);
  73     SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
  74     SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
  75
  76     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
  77                               const SPUTargetMachine &TM);
  78     //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form
  79     SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat,
  80                              DebugLoc dl);
  81   }
  82
  83   class SPUTargetMachine;            // forward dec'l.
  84
  85   class SPUTargetLowering :
  86     public TargetLowering
  87   {
  88     int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
  89     SPUTargetMachine &SPUTM;
  90
  91   public:
  92     //! The venerable constructor
  93     /*!
  94      This is where the CellSPU backend sets operation handling (i.e., legal,
  95      custom, expand or promote.)
  96      */
  97     SPUTargetLowering(SPUTargetMachine &TM);
  98
  99     //! Get the target machine
 100     SPUTargetMachine &getSPUTargetMachine() {
 101       return SPUTM;
 102     }
 103
 104     /// getTargetNodeName() - This method returns the name of a target specific
 105     /// DAG node.
 106     virtual const char *getTargetNodeName(unsigned Opcode) const;
 107
 108     /// getSetCCResultType - Return the ValueType for ISD::SETCC
 109     virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
 110
 111     //! Custom lowering hooks
 112     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
 113
 114     //! Custom lowering hook for nodes with illegal result types.
 115     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 116                                     SelectionDAG &DAG);
 117
 118     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 119
 120     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
 121                                                 const APInt &Mask,
 122                                                 APInt &KnownZero,
 123                                                 APInt &KnownOne,
 124                                                 const SelectionDAG &DAG,
 125                                                 unsigned Depth = 0) const;
 126
 127     virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
 128                                                    unsigned Depth = 0) const;
 129
 130     ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
 131
 132     std::pair<unsigned, const TargetRegisterClass*>
 133       getRegForInlineAsmConstraint(const std::string &Constraint,
 134                                    EVT VT) const;
 135
 136     void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
 137                                       bool hasMemory,
 138                                       std::vector<SDValue> &Ops,
 139                                       SelectionDAG &DAG) const;
 140
 141     /// isLegalAddressImmediate - Return true if the integer value can be used
 142     /// as the offset of the target addressing mode.
 143     virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
 144     virtual bool isLegalAddressImmediate(GlobalValue *) const;
 145
 146     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 147
 148     /// getFunctionAlignment - Return the Log2 alignment of this function.
 149     virtual unsigned getFunctionAlignment(const Function *F) const;
 150
 151     virtual SDValue
 152       LowerFormalArguments(SDValue Chain,
 153                            CallingConv::ID CallConv, bool isVarArg,
 154                            const SmallVectorImpl<ISD::InputArg> &Ins,
 155                            DebugLoc dl, SelectionDAG &DAG,
 156                            SmallVectorImpl<SDValue> &InVals);
 157
 158     virtual SDValue
 159       LowerCall(SDValue Chain, SDValue Callee,
 160                 CallingConv::ID CallConv, bool isVarArg,
 161                 bool isTailCall,
 162                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 163                 const SmallVectorImpl<ISD::InputArg> &Ins,
 164                 DebugLoc dl, SelectionDAG &DAG,
 165                 SmallVectorImpl<SDValue> &InVals);
 166
 167     virtual SDValue
 168       LowerReturn(SDValue Chain,
 169                   CallingConv::ID CallConv, bool isVarArg,
 170                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 171                   DebugLoc dl, SelectionDAG &DAG);
 172   };
 173 }
 174
 175 #endif