lib/Target/Mips/MipsRegisterInfo.cpp

   1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "mips-reg-info"
  15
  16 #include "Mips.h"
  17 #include "MipsSubtarget.h"
  18 #include "MipsRegisterInfo.h"
  19 #include "MipsMachineFunction.h"
  20 #include "llvm/Constants.h"
  21 #include "llvm/Type.h"
  22 #include "llvm/Function.h"
  23 #include "llvm/CodeGen/ValueTypes.h"
  24 #include "llvm/CodeGen/MachineInstrBuilder.h"
  25 #include "llvm/CodeGen/MachineFunction.h"
  26 #include "llvm/CodeGen/MachineFrameInfo.h"
  27 #include "llvm/CodeGen/MachineLocation.h"
  28 #include "llvm/Target/TargetFrameInfo.h"
  29 #include "llvm/Target/TargetMachine.h"
  30 #include "llvm/Target/TargetOptions.h"
  31 #include "llvm/Target/TargetInstrInfo.h"
  32 #include "llvm/Support/CommandLine.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/ErrorHandling.h"
  35 #include "llvm/Support/raw_ostream.h"
  36 #include "llvm/ADT/BitVector.h"
  37 #include "llvm/ADT/STLExtras.h"
  38
  39 using namespace llvm;
  40
  41 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
  42                                    const TargetInstrInfo &tii)
  43   : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
  44     Subtarget(ST), TII(tii) {}
  45
  46 /// getRegisterNumbering - Given the enum value for some register, e.g.
  47 /// Mips::RA, return the number that it corresponds to (e.g. 31).
  48 unsigned MipsRegisterInfo::
  49 getRegisterNumbering(unsigned RegEnum)
  50 {
  51   switch (RegEnum) {
  52     case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
  53     case Mips::AT   : case Mips::F1 : return 1;
  54     case Mips::V0   : case Mips::F2 : case Mips::D1 : return 2;
  55     case Mips::V1   : case Mips::F3 : return 3;
  56     case Mips::A0   : case Mips::F4 : case Mips::D2 : return 4;
  57     case Mips::A1   : case Mips::F5 : return 5;
  58     case Mips::A2   : case Mips::F6 : case Mips::D3 : return 6;
  59     case Mips::A3   : case Mips::F7 : return 7;
  60     case Mips::T0   : case Mips::F8 : case Mips::D4 : return 8;
  61     case Mips::T1   : case Mips::F9 : return 9;
  62     case Mips::T2   : case Mips::F10: case Mips::D5: return 10;
  63     case Mips::T3   : case Mips::F11: return 11;
  64     case Mips::T4   : case Mips::F12: case Mips::D6: return 12;
  65     case Mips::T5   : case Mips::F13: return 13;
  66     case Mips::T6   : case Mips::F14: case Mips::D7: return 14;
  67     case Mips::T7   : case Mips::F15: return 15;
  68     case Mips::T8   : case Mips::F16: case Mips::D8: return 16;
  69     case Mips::T9   : case Mips::F17: return 17;
  70     case Mips::S0   : case Mips::F18: case Mips::D9: return 18;
  71     case Mips::S1   : case Mips::F19: return 19;
  72     case Mips::S2   : case Mips::F20: case Mips::D10: return 20;
  73     case Mips::S3   : case Mips::F21: return 21;
  74     case Mips::S4   : case Mips::F22: case Mips::D11: return 22;
  75     case Mips::S5   : case Mips::F23: return 23;
  76     case Mips::S6   : case Mips::F24: case Mips::D12: return 24;
  77     case Mips::S7   : case Mips::F25: return 25;
  78     case Mips::K0   : case Mips::F26: case Mips::D13: return 26;
  79     case Mips::K1   : case Mips::F27: return 27;
  80     case Mips::GP   : case Mips::F28: case Mips::D14: return 28;
  81     case Mips::SP   : case Mips::F29: return 29;
  82     case Mips::FP   : case Mips::F30: case Mips::D15: return 30;
  83     case Mips::RA   : case Mips::F31: return 31;
  84     default: llvm_unreachable("Unknown register number!");
  85   }
  86   return 0; // Not reached
  87 }
  88
  89 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
  90
  91 //===----------------------------------------------------------------------===//
  92 // Callee Saved Registers methods
  93 //===----------------------------------------------------------------------===//
  94
  95 /// Mips Callee Saved Registers
  96 const unsigned* MipsRegisterInfo::
  97 getCalleeSavedRegs(const MachineFunction *MF) const
  98 {
  99   // Mips callee-save register range is $16-$23, $f20-$f30
 100   static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
 101     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
 102     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
 103     Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
 104     Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
 105   };
 106
 107   static const unsigned BitMode32CalleeSavedRegs[] = {
 108     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
 109     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
 110     Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
 111     Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,0
 112   };
 113
 114   if (Subtarget.isSingleFloat())
 115     return SingleFloatOnlyCalleeSavedRegs;
 116   else
 117     return BitMode32CalleeSavedRegs;
 118 }
 119
 120 /// Mips Callee Saved Register Classes
 121 const TargetRegisterClass* const*
 122 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
 123 {
 124   static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
 125     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 126     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 127     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 128     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 129     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 130     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 131     &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
 132   };
 133
 134   static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
 135     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 136     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 137     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 138     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 139     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 140     &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass,
 141     &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, 0
 142   };
 143
 144   if (Subtarget.isSingleFloat())
 145     return SingleFloatOnlyCalleeSavedRC;
 146   else
 147     return BitMode32CalleeSavedRC;
 148 }
 149
 150 BitVector MipsRegisterInfo::
 151 getReservedRegs(const MachineFunction &MF) const
 152 {
 153   BitVector Reserved(getNumRegs());
 154   Reserved.set(Mips::ZERO);
 155   Reserved.set(Mips::AT);
 156   Reserved.set(Mips::K0);
 157   Reserved.set(Mips::K1);
 158   Reserved.set(Mips::GP);
 159   Reserved.set(Mips::SP);
 160   Reserved.set(Mips::FP);
 161   Reserved.set(Mips::RA);
 162
 163   // SRV4 requires that odd register can't be used.
 164   if (!Subtarget.isSingleFloat())
 165     for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
 166       Reserved.set(FReg);
 167
 168   return Reserved;
 169 }
 170
 171 //===----------------------------------------------------------------------===//
 172 //
 173 // Stack Frame Processing methods
 174 // +----------------------------+
 175 //
 176 // The stack is allocated decrementing the stack pointer on
 177 // the first instruction of a function prologue. Once decremented,
 178 // all stack referencesare are done thought a positive offset
 179 // from the stack/frame pointer, so the stack is considering
 180 // to grow up! Otherwise terrible hacks would have to be made
 181 // to get this stack ABI compliant :)
 182 //
 183 //  The stack frame required by the ABI (after call):
 184 //  Offset
 185 //
 186 //  0                 ----------
 187 //  4                 Args to pass
 188 //  .                 saved $GP  (used in PIC)
 189 //  .                 Alloca allocations
 190 //  .                 Local Area
 191 //  .                 CPU "Callee Saved" Registers
 192 //  .                 saved FP
 193 //  .                 saved RA
 194 //  .                 FPU "Callee Saved" Registers
 195 //  StackSize         -----------
 196 //
 197 // Offset - offset from sp after stack allocation on function prologue
 198 //
 199 // The sp is the stack pointer subtracted/added from the stack size
 200 // at the Prologue/Epilogue
 201 //
 202 // References to the previous stack (to obtain arguments) are done
 203 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
 204 //
 205 // Examples:
 206 // - reference to the actual stack frame
 207 //   for any local area var there is smt like : FI >= 0, StackOffset: 4
 208 //     sw REGX, 4(SP)
 209 //
 210 // - reference to previous stack frame
 211 //   suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
 212 //   The emitted instruction will be something like:
 213 //     lw REGX, 16+StackSize(SP)
 214 //
 215 // Since the total stack size is unknown on LowerFormalArguments, all
 216 // stack references (ObjectOffset) created to reference the function
 217 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
 218 // possible to detect those references and the offsets are adjusted to
 219 // their real location.
 220 //
 221 //===----------------------------------------------------------------------===//
 222
 223 void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
 224 {
 225   MachineFrameInfo *MFI = MF.getFrameInfo();
 226   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 227   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 228   unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
 229
 230   // Min and Max CSI FrameIndex.
 231   int MinCSFI = -1, MaxCSFI = -1;
 232
 233   // See the description at MipsMachineFunction.h
 234   int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
 235
 236   // Replace the dummy '0' SPOffset by the negative offsets, as explained on
 237   // LowerFormalArguments. Leaving '0' for while is necessary to avoid
 238   // the approach done by calculateFrameObjectOffsets to the stack frame.
 239   MipsFI->adjustLoadArgsFI(MFI);
 240   MipsFI->adjustStoreVarArgsFI(MFI);
 241
 242   // It happens that the default stack frame allocation order does not directly
 243   // map to the convention used for mips. So we must fix it. We move the callee
 244   // save register slots after the local variables area, as described in the
 245   // stack frame above.
 246   unsigned CalleeSavedAreaSize = 0;
 247   if (!CSI.empty()) {
 248     MinCSFI = CSI[0].getFrameIdx();
 249     MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
 250   }
 251   for (unsigned i = 0, e = CSI.size(); i != e; ++i)
 252     CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
 253
 254   // Adjust local variables. They should come on the stack right
 255   // after the arguments.
 256   int LastOffsetFI = -1;
 257   for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
 258     if (i >= MinCSFI && i <= MaxCSFI)
 259       continue;
 260     if (MFI->isDeadObjectIndex(i))
 261       continue;
 262     unsigned Offset = MFI->getObjectOffset(i) - CalleeSavedAreaSize;
 263     if (LastOffsetFI == -1)
 264       LastOffsetFI = i;
 265     if (Offset > MFI->getObjectOffset(LastOffsetFI))
 266       LastOffsetFI = i;
 267     MFI->setObjectOffset(i, Offset);
 268   }
 269
 270   // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
 271   // be saved in this CPU Area there is the need. This whole Area must
 272   // be aligned to the default Stack Alignment requirements.
 273   unsigned StackOffset = 0;
 274   unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
 275
 276   if (LastOffsetFI >= 0)
 277     StackOffset = MFI->getObjectOffset(LastOffsetFI)+
 278                   MFI->getObjectSize(LastOffsetFI);
 279   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
 280
 281   for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
 282     if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
 283       break;
 284     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
 285     TopCPUSavedRegOff = StackOffset;
 286     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
 287   }
 288
 289   if (hasFP(MF)) {
 290     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
 291                          StackOffset);
 292     MipsFI->setFPStackOffset(StackOffset);
 293     TopCPUSavedRegOff = StackOffset;
 294     StackOffset += RegSize;
 295   }
 296
 297   if (MFI->hasCalls()) {
 298     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
 299                          StackOffset);
 300     MipsFI->setRAStackOffset(StackOffset);
 301     TopCPUSavedRegOff = StackOffset;
 302     StackOffset += RegSize;
 303   }
 304   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
 305
 306   // Adjust FPU Callee Saved Registers Area. This Area must be
 307   // aligned to the default Stack Alignment requirements.
 308   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
 309     if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
 310       continue;
 311     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
 312     TopFPUSavedRegOff = StackOffset;
 313     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
 314   }
 315   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
 316
 317   // Update frame info
 318   MFI->setStackSize(StackOffset);
 319
 320   // Recalculate the final tops offset. The final values must be '0'
 321   // if there isn't a callee saved register for CPU or FPU, otherwise
 322   // a negative offset is needed.
 323   if (TopCPUSavedRegOff >= 0)
 324     MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
 325
 326   if (TopFPUSavedRegOff >= 0)
 327     MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
 328 }
 329
 330 // hasFP - Return true if the specified function should have a dedicated frame
 331 // pointer register.  This is true if the function has variable sized allocas or
 332 // if frame pointer elimination is disabled.
 333 bool MipsRegisterInfo::
 334 hasFP(const MachineFunction &MF) const {
 335   const MachineFrameInfo *MFI = MF.getFrameInfo();
 336   return NoFramePointerElim || MFI->hasVarSizedObjects();
 337 }
 338
 339 // This function eliminate ADJCALLSTACKDOWN,
 340 // ADJCALLSTACKUP pseudo instructions
 341 void MipsRegisterInfo::
 342 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 343                               MachineBasicBlock::iterator I) const {
 344   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
 345   MBB.erase(I);
 346 }
 347
 348 // FrameIndex represent objects inside a abstract stack.
 349 // We must replace FrameIndex with an stack/frame pointer
 350 // direct reference.
 351 void MipsRegisterInfo::
 352 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
 353                     RegScavenger *RS) const
 354 {
 355   MachineInstr &MI = *II;
 356   MachineFunction &MF = *MI.getParent()->getParent();
 357
 358   unsigned i = 0;
 359   while (!MI.getOperand(i).isFI()) {
 360     ++i;
 361     assert(i < MI.getNumOperands() &&
 362            "Instr doesn't have FrameIndex operand!");
 363   }
 364
 365   DEBUG(errs() << "\nFunction : " << MF.getFunction()->getName() << "\n";
 366         errs() << "<--------->\n" << MI);
 367
 368   int FrameIndex = MI.getOperand(i).getIndex();
 369   int stackSize  = MF.getFrameInfo()->getStackSize();
 370   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 371
 372   DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"
 373                << "spOffset   : " << spOffset << "\n"
 374                << "stackSize  : " << stackSize << "\n");
 375
 376   // as explained on LowerFormalArguments, detect negative offsets
 377   // and adjust SPOffsets considering the final stack size.
 378   int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
 379   Offset    += MI.getOperand(i-1).getImm();
 380
 381   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
 382
 383   MI.getOperand(i-1).ChangeToImmediate(Offset);
 384   MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
 385 }
 386
 387 void MipsRegisterInfo::
 388 emitPrologue(MachineFunction &MF) const
 389 {
 390   MachineBasicBlock &MBB   = MF.front();
 391   MachineFrameInfo *MFI    = MF.getFrameInfo();
 392   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 393   MachineBasicBlock::iterator MBBI = MBB.begin();
 394   DebugLoc dl = (MBBI != MBB.end() ?
 395                  MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
 396   bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
 397
 398   // Get the right frame order for Mips.
 399   adjustMipsStackFrame(MF);
 400
 401   // Get the number of bytes to allocate from the FrameInfo.
 402   unsigned StackSize = MFI->getStackSize();
 403
 404   // No need to allocate space on the stack.
 405   if (StackSize == 0 && !MFI->hasCalls()) return;
 406
 407   int FPOffset = MipsFI->getFPStackOffset();
 408   int RAOffset = MipsFI->getRAStackOffset();
 409
 410   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
 411
 412   // TODO: check need from GP here.
 413   if (isPIC && Subtarget.isABI_O32())
 414     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
 415   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
 416
 417   // Adjust stack : addi sp, sp, (-imm)
 418   BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
 419       .addReg(Mips::SP).addImm(-StackSize);
 420
 421   // Save the return address only if the function isnt a leaf one.
 422   // sw  $ra, stack_loc($sp)
 423   if (MFI->hasCalls()) {
 424     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
 425         .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
 426   }
 427
 428   // if framepointer enabled, save it and set it
 429   // to point to the stack pointer
 430   if (hasFP(MF)) {
 431     // sw  $fp,stack_loc($sp)
 432     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
 433       .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
 434
 435     // move $fp, $sp
 436     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
 437       .addReg(Mips::SP).addReg(Mips::ZERO);
 438   }
 439
 440   // PIC speficic function prologue
 441   if ((isPIC) && (MFI->hasCalls())) {
 442     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
 443       .addImm(MipsFI->getGPStackOffset());
 444   }
 445 }
 446
 447 void MipsRegisterInfo::
 448 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
 449 {
 450   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 451   MachineFrameInfo *MFI            = MF.getFrameInfo();
 452   MipsFunctionInfo *MipsFI         = MF.getInfo<MipsFunctionInfo>();
 453   DebugLoc dl = MBBI->getDebugLoc();
 454
 455   // Get the number of bytes from FrameInfo
 456   int NumBytes = (int) MFI->getStackSize();
 457
 458   // Get the FI's where RA and FP are saved.
 459   int FPOffset = MipsFI->getFPStackOffset();
 460   int RAOffset = MipsFI->getRAStackOffset();
 461
 462   // if framepointer enabled, restore it and restore the
 463   // stack pointer
 464   if (hasFP(MF)) {
 465     // move $sp, $fp
 466     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
 467       .addReg(Mips::FP).addReg(Mips::ZERO);
 468
 469     // lw  $fp,stack_loc($sp)
 470     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP)
 471       .addImm(FPOffset).addReg(Mips::SP);
 472   }
 473
 474   // Restore the return address only if the function isnt a leaf one.
 475   // lw  $ra, stack_loc($sp)
 476   if (MFI->hasCalls()) {
 477     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA)
 478       .addImm(RAOffset).addReg(Mips::SP);
 479   }
 480
 481   // adjust stack  : insert addi sp, sp, (imm)
 482   if (NumBytes) {
 483     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
 484       .addReg(Mips::SP).addImm(NumBytes);
 485   }
 486 }
 487
 488
 489 void MipsRegisterInfo::
 490 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
 491   // Set the SPOffset on the FI where GP must be saved/loaded.
 492   MachineFrameInfo *MFI = MF.getFrameInfo();
 493   bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
 494   if (MFI->hasCalls() && isPIC) {
 495     MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 496     MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
 497   }
 498 }
 499
 500 unsigned MipsRegisterInfo::
 501 getRARegister() const {
 502   return Mips::RA;
 503 }
 504
 505 unsigned MipsRegisterInfo::
 506 getFrameRegister(MachineFunction &MF) const {
 507   return hasFP(MF) ? Mips::FP : Mips::SP;
 508 }
 509
 510 unsigned MipsRegisterInfo::
 511 getEHExceptionRegister() const {
 512   llvm_unreachable("What is the exception register");
 513   return 0;
 514 }
 515
 516 unsigned MipsRegisterInfo::
 517 getEHHandlerRegister() const {
 518   llvm_unreachable("What is the exception handler register");
 519   return 0;
 520 }
 521
 522 int MipsRegisterInfo::
 523 getDwarfRegNum(unsigned RegNum, bool isEH) const {
 524   llvm_unreachable("What is the dwarf register number");
 525   return -1;
 526 }
 527
 528 #include "MipsGenRegisterInfo.inc"
 529