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1 //===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
13 class PPCReg<string n> : Register<n> {
14 let Namespace = "PPC";
15 }
17 // We identify all our registers with a 5-bit ID, for consistency's sake.
19 // GPR - One of the 32 32-bit general-purpose registers
20 class GPR<bits<5> num, string n> : PPCReg<n> {
21 field bits<5> Num = num;
22 }
24 // GP8 - One of the 32 64-bit general-purpose registers
25 class GP8<GPR SubReg, string n> : PPCReg<n> {
26 field bits<5> Num = SubReg.Num;
27 let SubRegs = [SubReg];
28 }
30 // SPR - One of the 32-bit special-purpose registers
31 class SPR<bits<10> num, string n> : PPCReg<n> {
32 field bits<10> Num = num;
33 }
35 // FPR - One of the 32 64-bit floating-point registers
36 class FPR<bits<5> num, string n> : PPCReg<n> {
37 field bits<5> Num = num;
38 }
40 // VR - One of the 32 128-bit vector registers
41 class VR<bits<5> num, string n> : PPCReg<n> {
42 field bits<5> Num = num;
43 }
45 // CR - One of the 8 4-bit condition registers
46 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
47 field bits<3> Num = num;
48 let SubRegs = subregs;
49 }
51 // CRBIT - One of the 32 1-bit condition register fields
52 class CRBIT<bits<5> num, string n> : PPCReg<n> {
53 field bits<5> Num = num;
54 }
57 // General-purpose registers
58 def R0 : GPR< 0, "r0">, DwarfRegNum<[0]>;
59 def R1 : GPR< 1, "r1">, DwarfRegNum<[1]>;
60 def R2 : GPR< 2, "r2">, DwarfRegNum<[2]>;
61 def R3 : GPR< 3, "r3">, DwarfRegNum<[3]>;
62 def R4 : GPR< 4, "r4">, DwarfRegNum<[4]>;
63 def R5 : GPR< 5, "r5">, DwarfRegNum<[5]>;
64 def R6 : GPR< 6, "r6">, DwarfRegNum<[6]>;
65 def R7 : GPR< 7, "r7">, DwarfRegNum<[7]>;
66 def R8 : GPR< 8, "r8">, DwarfRegNum<[8]>;
67 def R9 : GPR< 9, "r9">, DwarfRegNum<[9]>;
68 def R10 : GPR<10, "r10">, DwarfRegNum<[10]>;
69 def R11 : GPR<11, "r11">, DwarfRegNum<[11]>;
70 def R12 : GPR<12, "r12">, DwarfRegNum<[12]>;
71 def R13 : GPR<13, "r13">, DwarfRegNum<[13]>;
72 def R14 : GPR<14, "r14">, DwarfRegNum<[14]>;
73 def R15 : GPR<15, "r15">, DwarfRegNum<[15]>;
74 def R16 : GPR<16, "r16">, DwarfRegNum<[16]>;
75 def R17 : GPR<17, "r17">, DwarfRegNum<[17]>;
76 def R18 : GPR<18, "r18">, DwarfRegNum<[18]>;
77 def R19 : GPR<19, "r19">, DwarfRegNum<[19]>;
78 def R20 : GPR<20, "r20">, DwarfRegNum<[20]>;
79 def R21 : GPR<21, "r21">, DwarfRegNum<[21]>;
80 def R22 : GPR<22, "r22">, DwarfRegNum<[22]>;
81 def R23 : GPR<23, "r23">, DwarfRegNum<[23]>;
82 def R24 : GPR<24, "r24">, DwarfRegNum<[24]>;
83 def R25 : GPR<25, "r25">, DwarfRegNum<[25]>;
84 def R26 : GPR<26, "r26">, DwarfRegNum<[26]>;
85 def R27 : GPR<27, "r27">, DwarfRegNum<[27]>;
86 def R28 : GPR<28, "r28">, DwarfRegNum<[28]>;
87 def R29 : GPR<29, "r29">, DwarfRegNum<[29]>;
88 def R30 : GPR<30, "r30">, DwarfRegNum<[30]>;
89 def R31 : GPR<31, "r31">, DwarfRegNum<[31]>;
91 // 64-bit General-purpose registers
92 def X0 : GP8< R0, "r0">, DwarfRegNum<[0]>;
93 def X1 : GP8< R1, "r1">, DwarfRegNum<[1]>;
94 def X2 : GP8< R2, "r2">, DwarfRegNum<[2]>;
95 def X3 : GP8< R3, "r3">, DwarfRegNum<[3]>;
96 def X4 : GP8< R4, "r4">, DwarfRegNum<[4]>;
97 def X5 : GP8< R5, "r5">, DwarfRegNum<[5]>;
98 def X6 : GP8< R6, "r6">, DwarfRegNum<[6]>;
99 def X7 : GP8< R7, "r7">, DwarfRegNum<[7]>;
100 def X8 : GP8< R8, "r8">, DwarfRegNum<[8]>;
101 def X9 : GP8< R9, "r9">, DwarfRegNum<[9]>;
102 def X10 : GP8<R10, "r10">, DwarfRegNum<[10]>;
103 def X11 : GP8<R11, "r11">, DwarfRegNum<[11]>;
104 def X12 : GP8<R12, "r12">, DwarfRegNum<[12]>;
105 def X13 : GP8<R13, "r13">, DwarfRegNum<[13]>;
106 def X14 : GP8<R14, "r14">, DwarfRegNum<[14]>;
107 def X15 : GP8<R15, "r15">, DwarfRegNum<[15]>;
108 def X16 : GP8<R16, "r16">, DwarfRegNum<[16]>;
109 def X17 : GP8<R17, "r17">, DwarfRegNum<[17]>;
110 def X18 : GP8<R18, "r18">, DwarfRegNum<[18]>;
111 def X19 : GP8<R19, "r19">, DwarfRegNum<[19]>;
112 def X20 : GP8<R20, "r20">, DwarfRegNum<[20]>;
113 def X21 : GP8<R21, "r21">, DwarfRegNum<[21]>;
114 def X22 : GP8<R22, "r22">, DwarfRegNum<[22]>;
115 def X23 : GP8<R23, "r23">, DwarfRegNum<[23]>;
116 def X24 : GP8<R24, "r24">, DwarfRegNum<[24]>;
117 def X25 : GP8<R25, "r25">, DwarfRegNum<[25]>;
118 def X26 : GP8<R26, "r26">, DwarfRegNum<[26]>;
119 def X27 : GP8<R27, "r27">, DwarfRegNum<[27]>;
120 def X28 : GP8<R28, "r28">, DwarfRegNum<[28]>;
121 def X29 : GP8<R29, "r29">, DwarfRegNum<[29]>;
122 def X30 : GP8<R30, "r30">, DwarfRegNum<[30]>;
123 def X31 : GP8<R31, "r31">, DwarfRegNum<[31]>;
125 // Floating-point registers
126 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
127 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>;
128 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>;
129 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>;
130 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>;
131 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>;
132 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>;
133 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>;
134 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>;
135 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>;
136 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>;
137 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>;
138 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>;
139 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>;
140 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>;
141 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>;
142 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>;
143 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>;
144 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>;
145 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>;
146 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>;
147 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>;
148 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>;
149 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>;
150 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>;
151 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>;
152 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>;
153 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>;
154 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>;
155 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>;
156 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>;
157 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>;
159 // Vector registers
160 def V0 : VR< 0, "v0">, DwarfRegNum<[77]>;
161 def V1 : VR< 1, "v1">, DwarfRegNum<[78]>;
162 def V2 : VR< 2, "v2">, DwarfRegNum<[79]>;
163 def V3 : VR< 3, "v3">, DwarfRegNum<[80]>;
164 def V4 : VR< 4, "v4">, DwarfRegNum<[81]>;
165 def V5 : VR< 5, "v5">, DwarfRegNum<[82]>;
166 def V6 : VR< 6, "v6">, DwarfRegNum<[83]>;
167 def V7 : VR< 7, "v7">, DwarfRegNum<[84]>;
168 def V8 : VR< 8, "v8">, DwarfRegNum<[85]>;
169 def V9 : VR< 9, "v9">, DwarfRegNum<[86]>;
170 def V10 : VR<10, "v10">, DwarfRegNum<[87]>;
171 def V11 : VR<11, "v11">, DwarfRegNum<[88]>;
172 def V12 : VR<12, "v12">, DwarfRegNum<[89]>;
173 def V13 : VR<13, "v13">, DwarfRegNum<[90]>;
174 def V14 : VR<14, "v14">, DwarfRegNum<[91]>;
175 def V15 : VR<15, "v15">, DwarfRegNum<[92]>;
176 def V16 : VR<16, "v16">, DwarfRegNum<[93]>;
177 def V17 : VR<17, "v17">, DwarfRegNum<[94]>;
178 def V18 : VR<18, "v18">, DwarfRegNum<[95]>;
179 def V19 : VR<19, "v19">, DwarfRegNum<[96]>;
180 def V20 : VR<20, "v20">, DwarfRegNum<[97]>;
181 def V21 : VR<21, "v21">, DwarfRegNum<[98]>;
182 def V22 : VR<22, "v22">, DwarfRegNum<[99]>;
183 def V23 : VR<23, "v23">, DwarfRegNum<[100]>;
184 def V24 : VR<24, "v24">, DwarfRegNum<[101]>;
185 def V25 : VR<25, "v25">, DwarfRegNum<[102]>;
186 def V26 : VR<26, "v26">, DwarfRegNum<[103]>;
187 def V27 : VR<27, "v27">, DwarfRegNum<[104]>;
188 def V28 : VR<28, "v28">, DwarfRegNum<[105]>;
189 def V29 : VR<29, "v29">, DwarfRegNum<[106]>;
190 def V30 : VR<30, "v30">, DwarfRegNum<[107]>;
191 def V31 : VR<31, "v31">, DwarfRegNum<[108]>;
193 // Condition register bits
194 def CR0LT : CRBIT< 0, "0">, DwarfRegNum<[0]>;
195 def CR0GT : CRBIT< 1, "1">, DwarfRegNum<[0]>;
196 def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<[0]>;
197 def CR0UN : CRBIT< 3, "3">, DwarfRegNum<[0]>;
198 def CR1LT : CRBIT< 4, "4">, DwarfRegNum<[0]>;
199 def CR1GT : CRBIT< 5, "5">, DwarfRegNum<[0]>;
200 def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<[0]>;
201 def CR1UN : CRBIT< 7, "7">, DwarfRegNum<[0]>;
202 def CR2LT : CRBIT< 8, "8">, DwarfRegNum<[0]>;
203 def CR2GT : CRBIT< 9, "9">, DwarfRegNum<[0]>;
204 def CR2EQ : CRBIT<10, "10">, DwarfRegNum<[0]>;
205 def CR2UN : CRBIT<11, "11">, DwarfRegNum<[0]>;
206 def CR3LT : CRBIT<12, "12">, DwarfRegNum<[0]>;
207 def CR3GT : CRBIT<13, "13">, DwarfRegNum<[0]>;
208 def CR3EQ : CRBIT<14, "14">, DwarfRegNum<[0]>;
209 def CR3UN : CRBIT<15, "15">, DwarfRegNum<[0]>;
210 def CR4LT : CRBIT<16, "16">, DwarfRegNum<[0]>;
211 def CR4GT : CRBIT<17, "17">, DwarfRegNum<[0]>;
212 def CR4EQ : CRBIT<18, "18">, DwarfRegNum<[0]>;
213 def CR4UN : CRBIT<19, "19">, DwarfRegNum<[0]>;
214 def CR5LT : CRBIT<20, "20">, DwarfRegNum<[0]>;
215 def CR5GT : CRBIT<21, "21">, DwarfRegNum<[0]>;
216 def CR5EQ : CRBIT<22, "22">, DwarfRegNum<[0]>;
217 def CR5UN : CRBIT<23, "23">, DwarfRegNum<[0]>;
218 def CR6LT : CRBIT<24, "24">, DwarfRegNum<[0]>;
219 def CR6GT : CRBIT<25, "25">, DwarfRegNum<[0]>;
220 def CR6EQ : CRBIT<26, "26">, DwarfRegNum<[0]>;
221 def CR6UN : CRBIT<27, "27">, DwarfRegNum<[0]>;
222 def CR7LT : CRBIT<28, "28">, DwarfRegNum<[0]>;
223 def CR7GT : CRBIT<29, "29">, DwarfRegNum<[0]>;
224 def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>;
225 def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>;
227 // Condition registers
228 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>;
229 def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>;
230 def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>;
231 def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71]>;
232 def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>;
233 def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>;
234 def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>;
235 def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>;
237 def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
238 [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
239 def : SubRegSet<2, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
240 [CR0GT, CR1GT, CR2GT, CR3GT, CR4GT, CR5GT, CR6GT, CR7GT]>;
241 def : SubRegSet<3, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
242 [CR0EQ, CR1EQ, CR2EQ, CR3EQ, CR4EQ, CR5EQ, CR6EQ, CR7EQ]>;
243 def : SubRegSet<4, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
244 [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>;
246 // Link register
247 def LR : SPR<8, "lr">, DwarfRegNum<[65]>;
248 //let Aliases = [LR] in
249 def LR8 : SPR<8, "lr">, DwarfRegNum<[65]>;
251 // Count register
252 def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>;
253 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>;
255 // VRsave register
256 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>;
258 // FP rounding mode: bits 30 and 31 of the FP status and control register
259 // This is not allocated as a normal register; it appears only in
260 // Uses and Defs. The ABI says it needs to be preserved by a function,
261 // but this is not achieved by saving and restoring it as with
262 // most registers, it has to be done in code; to make this work all the
263 // return and call instructions are described as Uses of RM, so instructions
264 // that do nothing but change RM will not get deleted.
265 // Also, in the architecture it is not really a SPR; 512 is arbitrary.
266 def RM: SPR<512, "**ROUNDING MODE**">, DwarfRegNum<[0]>;
268 /// Register classes
269 // Allocate volatiles first
270 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
271 def GPRC : RegisterClass<"PPC", [i32], 32,
272 [R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12,
273 R30, R29, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17,
274 R16, R15, R14, R13, R31, R0, R1, LR]>
275 {
276 let MethodProtos = [{
277 iterator allocation_order_begin(const MachineFunction &MF) const;
278 iterator allocation_order_end(const MachineFunction &MF) const;
279 }];
280 let MethodBodies = [{
281 GPRCClass::iterator
282 GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
283 // 32-bit SVR4 ABI: r2 is reserved for the OS.
284 // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
285 if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
286 return begin()+1;
288 return begin();
289 }
290 GPRCClass::iterator
291 GPRCClass::allocation_order_end(const MachineFunction &MF) const {
292 // On PPC64, r13 is the thread pointer. Never allocate this register.
293 // Note that this is overconservative, as it also prevents allocation of
294 // R31 when the FP is not needed.
295 // When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area
296 // pointer.
297 const PPCSubtarget &Subtarget
298 = MF.getTarget().getSubtarget<PPCSubtarget>();
300 if (Subtarget.isPPC64() || Subtarget.isSVR4ABI())
301 return end()-5; // don't allocate R13, R31, R0, R1, LR
303 if (needsFP(MF))
304 return end()-4; // don't allocate R31, R0, R1, LR
305 else
306 return end()-3; // don't allocate R0, R1, LR
307 }
308 }];
309 }
310 def G8RC : RegisterClass<"PPC", [i64], 64,
311 [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
312 X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
313 X16, X15, X14, X31, X13, X0, X1, LR8]>
314 {
315 let MethodProtos = [{
316 iterator allocation_order_begin(const MachineFunction &MF) const;
317 iterator allocation_order_end(const MachineFunction &MF) const;
318 }];
319 let MethodBodies = [{
320 G8RCClass::iterator
321 G8RCClass::allocation_order_begin(const MachineFunction &MF) const {
322 // 64-bit SVR4 ABI: r2 is reserved for the TOC pointer.
323 if (!MF.getTarget().getSubtarget<PPCSubtarget>().isDarwin())
324 return begin()+1;
326 return begin();
327 }
328 G8RCClass::iterator
329 G8RCClass::allocation_order_end(const MachineFunction &MF) const {
330 if (needsFP(MF))
331 return end()-5;
332 else
333 return end()-4;
334 }
335 }];
336 }
338 // Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
339 // ABI the size of the Floating-point register save area is determined by the
340 // allocated non-volatile register with the lowest register number, as FP
341 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
342 // previous stack frame. By allocating non-volatiles in reverse order we make
343 // sure that the Floating-point register save area is always as small as
344 // possible because there aren't any unused spill slots.
345 def F8RC : RegisterClass<"PPC", [f64], 64, [F0, F1, F2, F3, F4, F5, F6, F7,
346 F8, F9, F10, F11, F12, F13, F31, F30, F29, F28, F27, F26, F25, F24, F23,
347 F22, F21, F20, F19, F18, F17, F16, F15, F14]>;
348 def F4RC : RegisterClass<"PPC", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7,
349 F8, F9, F10, F11, F12, F13, F31, F30, F29, F28, F27, F26, F25, F24, F23,
350 F22, F21, F20, F19, F18, F17, F16, F15, F14]>;
352 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
353 [V2, V3, V4, V5, V0, V1,
354 V6, V7, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
355 V29, V28, V27, V26, V25, V24, V23, V22, V21, V20]>;
357 def CRBITRC : RegisterClass<"PPC", [i32], 32,
358 [CR0LT, CR0GT, CR0EQ, CR0UN,
359 CR1LT, CR1GT, CR1EQ, CR1UN,
360 CR2LT, CR2GT, CR2EQ, CR2UN,
361 CR3LT, CR3GT, CR3EQ, CR3UN,
362 CR4LT, CR4GT, CR4EQ, CR4UN,
363 CR5LT, CR5GT, CR5EQ, CR5UN,
364 CR6LT, CR6GT, CR6EQ, CR6UN,
365 CR7LT, CR7GT, CR7EQ, CR7UN
366 ]>
367 {
368 let CopyCost = -1;
369 }
371 def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2,
372 CR3, CR4]>
373 {
374 let SubRegClassList = [CRBITRC, CRBITRC, CRBITRC, CRBITRC];
375 }
377 def CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>;
378 def CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>;
379 def VRSAVERC : RegisterClass<"PPC", [i32], 32, [VRSAVE]>;