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remove a dead bool.
[llvm/avr.git] / lib / Target / X86 / X86InstrInfo.cpp
blob859ad57725db6ff3f4fe719ad89d5a56494995da
1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86InstrInfo.h"
15 #include "X86.h"
16 #include "X86GenInstrInfo.inc"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 using namespace llvm;
36
37 static cl::opt<bool>
38 NoFusing("disable-spill-fusing",
39 cl::desc("Disable fusing of spill code into instructions"));
40 static cl::opt<bool>
41 PrintFailedFusing("print-failed-fuse-candidates",
42 cl::desc("Print instructions that the allocator wants to"
43 " fuse, but the X86 backend currently can't"),
44 cl::Hidden);
45 static cl::opt<bool>
46 ReMatPICStubLoad("remat-pic-stub-load",
47 cl::desc("Re-materialize load from stub in PIC mode"),
48 cl::init(false), cl::Hidden);
49
50 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
51 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
52 TM(tm), RI(tm, *this) {
53 SmallVector<unsigned,16> AmbEntries;
54 static const unsigned OpTbl2Addr[][2] = {
55 { X86::ADC32ri, X86::ADC32mi },
56 { X86::ADC32ri8, X86::ADC32mi8 },
57 { X86::ADC32rr, X86::ADC32mr },
58 { X86::ADC64ri32, X86::ADC64mi32 },
59 { X86::ADC64ri8, X86::ADC64mi8 },
60 { X86::ADC64rr, X86::ADC64mr },
61 { X86::ADD16ri, X86::ADD16mi },
62 { X86::ADD16ri8, X86::ADD16mi8 },
63 { X86::ADD16rr, X86::ADD16mr },
64 { X86::ADD32ri, X86::ADD32mi },
65 { X86::ADD32ri8, X86::ADD32mi8 },
66 { X86::ADD32rr, X86::ADD32mr },
67 { X86::ADD64ri32, X86::ADD64mi32 },
68 { X86::ADD64ri8, X86::ADD64mi8 },
69 { X86::ADD64rr, X86::ADD64mr },
70 { X86::ADD8ri, X86::ADD8mi },
71 { X86::ADD8rr, X86::ADD8mr },
72 { X86::AND16ri, X86::AND16mi },
73 { X86::AND16ri8, X86::AND16mi8 },
74 { X86::AND16rr, X86::AND16mr },
75 { X86::AND32ri, X86::AND32mi },
76 { X86::AND32ri8, X86::AND32mi8 },
77 { X86::AND32rr, X86::AND32mr },
78 { X86::AND64ri32, X86::AND64mi32 },
79 { X86::AND64ri8, X86::AND64mi8 },
80 { X86::AND64rr, X86::AND64mr },
81 { X86::AND8ri, X86::AND8mi },
82 { X86::AND8rr, X86::AND8mr },
83 { X86::DEC16r, X86::DEC16m },
84 { X86::DEC32r, X86::DEC32m },
85 { X86::DEC64_16r, X86::DEC64_16m },
86 { X86::DEC64_32r, X86::DEC64_32m },
87 { X86::DEC64r, X86::DEC64m },
88 { X86::DEC8r, X86::DEC8m },
89 { X86::INC16r, X86::INC16m },
90 { X86::INC32r, X86::INC32m },
91 { X86::INC64_16r, X86::INC64_16m },
92 { X86::INC64_32r, X86::INC64_32m },
93 { X86::INC64r, X86::INC64m },
94 { X86::INC8r, X86::INC8m },
95 { X86::NEG16r, X86::NEG16m },
96 { X86::NEG32r, X86::NEG32m },
97 { X86::NEG64r, X86::NEG64m },
98 { X86::NEG8r, X86::NEG8m },
99 { X86::NOT16r, X86::NOT16m },
100 { X86::NOT32r, X86::NOT32m },
101 { X86::NOT64r, X86::NOT64m },
102 { X86::NOT8r, X86::NOT8m },
103 { X86::OR16ri, X86::OR16mi },
104 { X86::OR16ri8, X86::OR16mi8 },
105 { X86::OR16rr, X86::OR16mr },
106 { X86::OR32ri, X86::OR32mi },
107 { X86::OR32ri8, X86::OR32mi8 },
108 { X86::OR32rr, X86::OR32mr },
109 { X86::OR64ri32, X86::OR64mi32 },
110 { X86::OR64ri8, X86::OR64mi8 },
111 { X86::OR64rr, X86::OR64mr },
112 { X86::OR8ri, X86::OR8mi },
113 { X86::OR8rr, X86::OR8mr },
114 { X86::ROL16r1, X86::ROL16m1 },
115 { X86::ROL16rCL, X86::ROL16mCL },
116 { X86::ROL16ri, X86::ROL16mi },
117 { X86::ROL32r1, X86::ROL32m1 },
118 { X86::ROL32rCL, X86::ROL32mCL },
119 { X86::ROL32ri, X86::ROL32mi },
120 { X86::ROL64r1, X86::ROL64m1 },
121 { X86::ROL64rCL, X86::ROL64mCL },
122 { X86::ROL64ri, X86::ROL64mi },
123 { X86::ROL8r1, X86::ROL8m1 },
124 { X86::ROL8rCL, X86::ROL8mCL },
125 { X86::ROL8ri, X86::ROL8mi },
126 { X86::ROR16r1, X86::ROR16m1 },
127 { X86::ROR16rCL, X86::ROR16mCL },
128 { X86::ROR16ri, X86::ROR16mi },
129 { X86::ROR32r1, X86::ROR32m1 },
130 { X86::ROR32rCL, X86::ROR32mCL },
131 { X86::ROR32ri, X86::ROR32mi },
132 { X86::ROR64r1, X86::ROR64m1 },
133 { X86::ROR64rCL, X86::ROR64mCL },
134 { X86::ROR64ri, X86::ROR64mi },
135 { X86::ROR8r1, X86::ROR8m1 },
136 { X86::ROR8rCL, X86::ROR8mCL },
137 { X86::ROR8ri, X86::ROR8mi },
138 { X86::SAR16r1, X86::SAR16m1 },
139 { X86::SAR16rCL, X86::SAR16mCL },
140 { X86::SAR16ri, X86::SAR16mi },
141 { X86::SAR32r1, X86::SAR32m1 },
142 { X86::SAR32rCL, X86::SAR32mCL },
143 { X86::SAR32ri, X86::SAR32mi },
144 { X86::SAR64r1, X86::SAR64m1 },
145 { X86::SAR64rCL, X86::SAR64mCL },
146 { X86::SAR64ri, X86::SAR64mi },
147 { X86::SAR8r1, X86::SAR8m1 },
148 { X86::SAR8rCL, X86::SAR8mCL },
149 { X86::SAR8ri, X86::SAR8mi },
150 { X86::SBB32ri, X86::SBB32mi },
151 { X86::SBB32ri8, X86::SBB32mi8 },
152 { X86::SBB32rr, X86::SBB32mr },
153 { X86::SBB64ri32, X86::SBB64mi32 },
154 { X86::SBB64ri8, X86::SBB64mi8 },
155 { X86::SBB64rr, X86::SBB64mr },
156 { X86::SHL16rCL, X86::SHL16mCL },
157 { X86::SHL16ri, X86::SHL16mi },
158 { X86::SHL32rCL, X86::SHL32mCL },
159 { X86::SHL32ri, X86::SHL32mi },
160 { X86::SHL64rCL, X86::SHL64mCL },
161 { X86::SHL64ri, X86::SHL64mi },
162 { X86::SHL8rCL, X86::SHL8mCL },
163 { X86::SHL8ri, X86::SHL8mi },
164 { X86::SHLD16rrCL, X86::SHLD16mrCL },
165 { X86::SHLD16rri8, X86::SHLD16mri8 },
166 { X86::SHLD32rrCL, X86::SHLD32mrCL },
167 { X86::SHLD32rri8, X86::SHLD32mri8 },
168 { X86::SHLD64rrCL, X86::SHLD64mrCL },
169 { X86::SHLD64rri8, X86::SHLD64mri8 },
170 { X86::SHR16r1, X86::SHR16m1 },
171 { X86::SHR16rCL, X86::SHR16mCL },
172 { X86::SHR16ri, X86::SHR16mi },
173 { X86::SHR32r1, X86::SHR32m1 },
174 { X86::SHR32rCL, X86::SHR32mCL },
175 { X86::SHR32ri, X86::SHR32mi },
176 { X86::SHR64r1, X86::SHR64m1 },
177 { X86::SHR64rCL, X86::SHR64mCL },
178 { X86::SHR64ri, X86::SHR64mi },
179 { X86::SHR8r1, X86::SHR8m1 },
180 { X86::SHR8rCL, X86::SHR8mCL },
181 { X86::SHR8ri, X86::SHR8mi },
182 { X86::SHRD16rrCL, X86::SHRD16mrCL },
183 { X86::SHRD16rri8, X86::SHRD16mri8 },
184 { X86::SHRD32rrCL, X86::SHRD32mrCL },
185 { X86::SHRD32rri8, X86::SHRD32mri8 },
186 { X86::SHRD64rrCL, X86::SHRD64mrCL },
187 { X86::SHRD64rri8, X86::SHRD64mri8 },
188 { X86::SUB16ri, X86::SUB16mi },
189 { X86::SUB16ri8, X86::SUB16mi8 },
190 { X86::SUB16rr, X86::SUB16mr },
191 { X86::SUB32ri, X86::SUB32mi },
192 { X86::SUB32ri8, X86::SUB32mi8 },
193 { X86::SUB32rr, X86::SUB32mr },
194 { X86::SUB64ri32, X86::SUB64mi32 },
195 { X86::SUB64ri8, X86::SUB64mi8 },
196 { X86::SUB64rr, X86::SUB64mr },
197 { X86::SUB8ri, X86::SUB8mi },
198 { X86::SUB8rr, X86::SUB8mr },
199 { X86::XOR16ri, X86::XOR16mi },
200 { X86::XOR16ri8, X86::XOR16mi8 },
201 { X86::XOR16rr, X86::XOR16mr },
202 { X86::XOR32ri, X86::XOR32mi },
203 { X86::XOR32ri8, X86::XOR32mi8 },
204 { X86::XOR32rr, X86::XOR32mr },
205 { X86::XOR64ri32, X86::XOR64mi32 },
206 { X86::XOR64ri8, X86::XOR64mi8 },
207 { X86::XOR64rr, X86::XOR64mr },
208 { X86::XOR8ri, X86::XOR8mi },
209 { X86::XOR8rr, X86::XOR8mr }
210 };
211
212 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
213 unsigned RegOp = OpTbl2Addr[i][0];
214 unsigned MemOp = OpTbl2Addr[i][1];
215 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
216 std::make_pair(MemOp,0))).second)
217 assert(false && "Duplicated entries?");
218 // Index 0, folded load and store, no alignment requirement.
219 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
220 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
221 std::make_pair(RegOp,
222 AuxInfo))).second)
223 AmbEntries.push_back(MemOp);
224 }
225
226 // If the third value is 1, then it's folding either a load or a store.
227 static const unsigned OpTbl0[][4] = {
228 { X86::BT16ri8, X86::BT16mi8, 1, 0 },
229 { X86::BT32ri8, X86::BT32mi8, 1, 0 },
230 { X86::BT64ri8, X86::BT64mi8, 1, 0 },
231 { X86::CALL32r, X86::CALL32m, 1, 0 },
232 { X86::CALL64r, X86::CALL64m, 1, 0 },
233 { X86::CMP16ri, X86::CMP16mi, 1, 0 },
234 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 },
235 { X86::CMP16rr, X86::CMP16mr, 1, 0 },
236 { X86::CMP32ri, X86::CMP32mi, 1, 0 },
237 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 },
238 { X86::CMP32rr, X86::CMP32mr, 1, 0 },
239 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 },
240 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 },
241 { X86::CMP64rr, X86::CMP64mr, 1, 0 },
242 { X86::CMP8ri, X86::CMP8mi, 1, 0 },
243 { X86::CMP8rr, X86::CMP8mr, 1, 0 },
244 { X86::DIV16r, X86::DIV16m, 1, 0 },
245 { X86::DIV32r, X86::DIV32m, 1, 0 },
246 { X86::DIV64r, X86::DIV64m, 1, 0 },
247 { X86::DIV8r, X86::DIV8m, 1, 0 },
248 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
249 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 },
250 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 },
251 { X86::IDIV16r, X86::IDIV16m, 1, 0 },
252 { X86::IDIV32r, X86::IDIV32m, 1, 0 },
253 { X86::IDIV64r, X86::IDIV64m, 1, 0 },
254 { X86::IDIV8r, X86::IDIV8m, 1, 0 },
255 { X86::IMUL16r, X86::IMUL16m, 1, 0 },
256 { X86::IMUL32r, X86::IMUL32m, 1, 0 },
257 { X86::IMUL64r, X86::IMUL64m, 1, 0 },
258 { X86::IMUL8r, X86::IMUL8m, 1, 0 },
259 { X86::JMP32r, X86::JMP32m, 1, 0 },
260 { X86::JMP64r, X86::JMP64m, 1, 0 },
261 { X86::MOV16ri, X86::MOV16mi, 0, 0 },
262 { X86::MOV16rr, X86::MOV16mr, 0, 0 },
263 { X86::MOV32ri, X86::MOV32mi, 0, 0 },
264 { X86::MOV32rr, X86::MOV32mr, 0, 0 },
265 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 },
266 { X86::MOV64rr, X86::MOV64mr, 0, 0 },
267 { X86::MOV8ri, X86::MOV8mi, 0, 0 },
268 { X86::MOV8rr, X86::MOV8mr, 0, 0 },
269 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
270 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 },
271 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 },
272 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 },
273 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
274 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
275 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 },
276 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 },
277 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
278 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 },
279 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 },
280 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 },
281 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 },
282 { X86::MUL16r, X86::MUL16m, 1, 0 },
283 { X86::MUL32r, X86::MUL32m, 1, 0 },
284 { X86::MUL64r, X86::MUL64m, 1, 0 },
285 { X86::MUL8r, X86::MUL8m, 1, 0 },
286 { X86::SETAEr, X86::SETAEm, 0, 0 },
287 { X86::SETAr, X86::SETAm, 0, 0 },
288 { X86::SETBEr, X86::SETBEm, 0, 0 },
289 { X86::SETBr, X86::SETBm, 0, 0 },
290 { X86::SETEr, X86::SETEm, 0, 0 },
291 { X86::SETGEr, X86::SETGEm, 0, 0 },
292 { X86::SETGr, X86::SETGm, 0, 0 },
293 { X86::SETLEr, X86::SETLEm, 0, 0 },
294 { X86::SETLr, X86::SETLm, 0, 0 },
295 { X86::SETNEr, X86::SETNEm, 0, 0 },
296 { X86::SETNOr, X86::SETNOm, 0, 0 },
297 { X86::SETNPr, X86::SETNPm, 0, 0 },
298 { X86::SETNSr, X86::SETNSm, 0, 0 },
299 { X86::SETOr, X86::SETOm, 0, 0 },
300 { X86::SETPr, X86::SETPm, 0, 0 },
301 { X86::SETSr, X86::SETSm, 0, 0 },
302 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 },
303 { X86::TEST16ri, X86::TEST16mi, 1, 0 },
304 { X86::TEST32ri, X86::TEST32mi, 1, 0 },
305 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 },
306 { X86::TEST8ri, X86::TEST8mi, 1, 0 }
307 };
308
309 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
310 unsigned RegOp = OpTbl0[i][0];
311 unsigned MemOp = OpTbl0[i][1];
312 unsigned Align = OpTbl0[i][3];
313 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
314 std::make_pair(MemOp,Align))).second)
315 assert(false && "Duplicated entries?");
316 unsigned FoldedLoad = OpTbl0[i][2];
317 // Index 0, folded load or store.
318 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
319 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
320 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
321 std::make_pair(RegOp, AuxInfo))).second)
322 AmbEntries.push_back(MemOp);
323 }
324
325 static const unsigned OpTbl1[][3] = {
326 { X86::CMP16rr, X86::CMP16rm, 0 },
327 { X86::CMP32rr, X86::CMP32rm, 0 },
328 { X86::CMP64rr, X86::CMP64rm, 0 },
329 { X86::CMP8rr, X86::CMP8rm, 0 },
330 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
331 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
332 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
333 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
334 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
335 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
336 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
337 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
338 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
339 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
340 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 },
341 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 },
342 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
343 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
344 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
345 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
346 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
347 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
348 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
349 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
350 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
351 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
352 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 },
353 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 },
354 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 },
355 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 },
356 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 },
357 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 },
358 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
359 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 },
360 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
361 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
362 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
363 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
364 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
365 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
366 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
367 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 },
368 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
369 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
370 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
371 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
372 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
373 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
374 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
375 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
376 { X86::MOV16rr, X86::MOV16rm, 0 },
377 { X86::MOV32rr, X86::MOV32rm, 0 },
378 { X86::MOV64rr, X86::MOV64rm, 0 },
379 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
380 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
381 { X86::MOV8rr, X86::MOV8rm, 0 },
382 { X86::MOVAPDrr, X86::MOVAPDrm, 16 },
383 { X86::MOVAPSrr, X86::MOVAPSrm, 16 },
384 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
385 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
386 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
387 { X86::MOVDQArr, X86::MOVDQArm, 16 },
388 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 },
389 { X86::MOVSDrr, X86::MOVSDrm, 0 },
390 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 },
391 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 },
392 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 },
393 { X86::MOVSSrr, X86::MOVSSrm, 0 },
394 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
395 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
396 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
397 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
398 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
399 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
400 { X86::MOVUPDrr, X86::MOVUPDrm, 16 },
401 { X86::MOVUPSrr, X86::MOVUPSrm, 16 },
402 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 },
403 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
404 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
405 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
406 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
407 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
408 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
409 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 },
410 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 },
411 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 },
412 { X86::PSHUFDri, X86::PSHUFDmi, 16 },
413 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 },
414 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 },
415 { X86::RCPPSr, X86::RCPPSm, 16 },
416 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 },
417 { X86::RSQRTPSr, X86::RSQRTPSm, 16 },
418 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 },
419 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
420 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
421 { X86::SQRTPDr, X86::SQRTPDm, 16 },
422 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 },
423 { X86::SQRTPSr, X86::SQRTPSm, 16 },
424 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 },
425 { X86::SQRTSDr, X86::SQRTSDm, 0 },
426 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
427 { X86::SQRTSSr, X86::SQRTSSm, 0 },
428 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
429 { X86::TEST16rr, X86::TEST16rm, 0 },
430 { X86::TEST32rr, X86::TEST32rm, 0 },
431 { X86::TEST64rr, X86::TEST64rm, 0 },
432 { X86::TEST8rr, X86::TEST8rm, 0 },
433 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
434 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
435 { X86::UCOMISSrr, X86::UCOMISSrm, 0 }
436 };
437
438 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
439 unsigned RegOp = OpTbl1[i][0];
440 unsigned MemOp = OpTbl1[i][1];
441 unsigned Align = OpTbl1[i][2];
442 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
443 std::make_pair(MemOp,Align))).second)
444 assert(false && "Duplicated entries?");
445 // Index 1, folded load
446 unsigned AuxInfo = 1 | (1 << 4);
447 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
448 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
449 std::make_pair(RegOp, AuxInfo))).second)
450 AmbEntries.push_back(MemOp);
451 }
452
453 static const unsigned OpTbl2[][3] = {
454 { X86::ADC32rr, X86::ADC32rm, 0 },
455 { X86::ADC64rr, X86::ADC64rm, 0 },
456 { X86::ADD16rr, X86::ADD16rm, 0 },
457 { X86::ADD32rr, X86::ADD32rm, 0 },
458 { X86::ADD64rr, X86::ADD64rm, 0 },
459 { X86::ADD8rr, X86::ADD8rm, 0 },
460 { X86::ADDPDrr, X86::ADDPDrm, 16 },
461 { X86::ADDPSrr, X86::ADDPSrm, 16 },
462 { X86::ADDSDrr, X86::ADDSDrm, 0 },
463 { X86::ADDSSrr, X86::ADDSSrm, 0 },
464 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 },
465 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 },
466 { X86::AND16rr, X86::AND16rm, 0 },
467 { X86::AND32rr, X86::AND32rm, 0 },
468 { X86::AND64rr, X86::AND64rm, 0 },
469 { X86::AND8rr, X86::AND8rm, 0 },
470 { X86::ANDNPDrr, X86::ANDNPDrm, 16 },
471 { X86::ANDNPSrr, X86::ANDNPSrm, 16 },
472 { X86::ANDPDrr, X86::ANDPDrm, 16 },
473 { X86::ANDPSrr, X86::ANDPSrm, 16 },
474 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
475 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
476 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
477 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
478 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
479 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
480 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
481 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
482 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
483 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
484 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
485 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
486 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
487 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
488 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
489 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
490 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
491 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
492 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
493 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
494 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
495 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
496 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
497 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
498 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
499 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
500 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
501 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
502 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
503 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
504 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
505 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
506 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
507 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
508 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
509 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
510 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
511 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
512 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
513 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
514 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
515 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
516 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
517 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
518 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
519 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
520 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
521 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
522 { X86::CMPPDrri, X86::CMPPDrmi, 16 },
523 { X86::CMPPSrri, X86::CMPPSrmi, 16 },
524 { X86::CMPSDrr, X86::CMPSDrm, 0 },
525 { X86::CMPSSrr, X86::CMPSSrm, 0 },
526 { X86::DIVPDrr, X86::DIVPDrm, 16 },
527 { X86::DIVPSrr, X86::DIVPSrm, 16 },
528 { X86::DIVSDrr, X86::DIVSDrm, 0 },
529 { X86::DIVSSrr, X86::DIVSSrm, 0 },
530 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 },
531 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 },
532 { X86::FsANDPDrr, X86::FsANDPDrm, 16 },
533 { X86::FsANDPSrr, X86::FsANDPSrm, 16 },
534 { X86::FsORPDrr, X86::FsORPDrm, 16 },
535 { X86::FsORPSrr, X86::FsORPSrm, 16 },
536 { X86::FsXORPDrr, X86::FsXORPDrm, 16 },
537 { X86::FsXORPSrr, X86::FsXORPSrm, 16 },
538 { X86::HADDPDrr, X86::HADDPDrm, 16 },
539 { X86::HADDPSrr, X86::HADDPSrm, 16 },
540 { X86::HSUBPDrr, X86::HSUBPDrm, 16 },
541 { X86::HSUBPSrr, X86::HSUBPSrm, 16 },
542 { X86::IMUL16rr, X86::IMUL16rm, 0 },
543 { X86::IMUL32rr, X86::IMUL32rm, 0 },
544 { X86::IMUL64rr, X86::IMUL64rm, 0 },
545 { X86::MAXPDrr, X86::MAXPDrm, 16 },
546 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 },
547 { X86::MAXPSrr, X86::MAXPSrm, 16 },
548 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 },
549 { X86::MAXSDrr, X86::MAXSDrm, 0 },
550 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
551 { X86::MAXSSrr, X86::MAXSSrm, 0 },
552 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
553 { X86::MINPDrr, X86::MINPDrm, 16 },
554 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 },
555 { X86::MINPSrr, X86::MINPSrm, 16 },
556 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 },
557 { X86::MINSDrr, X86::MINSDrm, 0 },
558 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
559 { X86::MINSSrr, X86::MINSSrm, 0 },
560 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
561 { X86::MULPDrr, X86::MULPDrm, 16 },
562 { X86::MULPSrr, X86::MULPSrm, 16 },
563 { X86::MULSDrr, X86::MULSDrm, 0 },
564 { X86::MULSSrr, X86::MULSSrm, 0 },
565 { X86::OR16rr, X86::OR16rm, 0 },
566 { X86::OR32rr, X86::OR32rm, 0 },
567 { X86::OR64rr, X86::OR64rm, 0 },
568 { X86::OR8rr, X86::OR8rm, 0 },
569 { X86::ORPDrr, X86::ORPDrm, 16 },
570 { X86::ORPSrr, X86::ORPSrm, 16 },
571 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 },
572 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 },
573 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 },
574 { X86::PADDBrr, X86::PADDBrm, 16 },
575 { X86::PADDDrr, X86::PADDDrm, 16 },
576 { X86::PADDQrr, X86::PADDQrm, 16 },
577 { X86::PADDSBrr, X86::PADDSBrm, 16 },
578 { X86::PADDSWrr, X86::PADDSWrm, 16 },
579 { X86::PADDWrr, X86::PADDWrm, 16 },
580 { X86::PANDNrr, X86::PANDNrm, 16 },
581 { X86::PANDrr, X86::PANDrm, 16 },
582 { X86::PAVGBrr, X86::PAVGBrm, 16 },
583 { X86::PAVGWrr, X86::PAVGWrm, 16 },
584 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 },
585 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 },
586 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 },
587 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 },
588 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 },
589 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 },
590 { X86::PINSRWrri, X86::PINSRWrmi, 16 },
591 { X86::PMADDWDrr, X86::PMADDWDrm, 16 },
592 { X86::PMAXSWrr, X86::PMAXSWrm, 16 },
593 { X86::PMAXUBrr, X86::PMAXUBrm, 16 },
594 { X86::PMINSWrr, X86::PMINSWrm, 16 },
595 { X86::PMINUBrr, X86::PMINUBrm, 16 },
596 { X86::PMULDQrr, X86::PMULDQrm, 16 },
597 { X86::PMULHUWrr, X86::PMULHUWrm, 16 },
598 { X86::PMULHWrr, X86::PMULHWrm, 16 },
599 { X86::PMULLDrr, X86::PMULLDrm, 16 },
600 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 },
601 { X86::PMULLWrr, X86::PMULLWrm, 16 },
602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 },
603 { X86::PORrr, X86::PORrm, 16 },
604 { X86::PSADBWrr, X86::PSADBWrm, 16 },
605 { X86::PSLLDrr, X86::PSLLDrm, 16 },
606 { X86::PSLLQrr, X86::PSLLQrm, 16 },
607 { X86::PSLLWrr, X86::PSLLWrm, 16 },
608 { X86::PSRADrr, X86::PSRADrm, 16 },
609 { X86::PSRAWrr, X86::PSRAWrm, 16 },
610 { X86::PSRLDrr, X86::PSRLDrm, 16 },
611 { X86::PSRLQrr, X86::PSRLQrm, 16 },
612 { X86::PSRLWrr, X86::PSRLWrm, 16 },
613 { X86::PSUBBrr, X86::PSUBBrm, 16 },
614 { X86::PSUBDrr, X86::PSUBDrm, 16 },
615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 },
616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 },
617 { X86::PSUBWrr, X86::PSUBWrm, 16 },
618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 },
619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 },
620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 },
621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 },
622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 },
623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 },
624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 },
625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 },
626 { X86::PXORrr, X86::PXORrm, 16 },
627 { X86::SBB32rr, X86::SBB32rm, 0 },
628 { X86::SBB64rr, X86::SBB64rm, 0 },
629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 },
630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 },
631 { X86::SUB16rr, X86::SUB16rm, 0 },
632 { X86::SUB32rr, X86::SUB32rm, 0 },
633 { X86::SUB64rr, X86::SUB64rm, 0 },
634 { X86::SUB8rr, X86::SUB8rm, 0 },
635 { X86::SUBPDrr, X86::SUBPDrm, 16 },
636 { X86::SUBPSrr, X86::SUBPSrm, 16 },
637 { X86::SUBSDrr, X86::SUBSDrm, 0 },
638 { X86::SUBSSrr, X86::SUBSSrm, 0 },
639 // FIXME: TEST*rr -> swapped operand of TEST*mr.
640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 },
641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 },
642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 },
643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 },
644 { X86::XOR16rr, X86::XOR16rm, 0 },
645 { X86::XOR32rr, X86::XOR32rm, 0 },
646 { X86::XOR64rr, X86::XOR64rm, 0 },
647 { X86::XOR8rr, X86::XOR8rm, 0 },
648 { X86::XORPDrr, X86::XORPDrm, 16 },
649 { X86::XORPSrr, X86::XORPSrm, 16 }
650 };
651
652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
653 unsigned RegOp = OpTbl2[i][0];
654 unsigned MemOp = OpTbl2[i][1];
655 unsigned Align = OpTbl2[i][2];
656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
657 std::make_pair(MemOp,Align))).second)
658 assert(false && "Duplicated entries?");
659 // Index 2, folded load
660 unsigned AuxInfo = 2 | (1 << 4);
661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
662 std::make_pair(RegOp, AuxInfo))).second)
663 AmbEntries.push_back(MemOp);
664 }
665
666 // Remove ambiguous entries.
667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
668 }
669
670 bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
671 unsigned &SrcReg, unsigned &DstReg,
672 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
673 switch (MI.getOpcode()) {
674 default:
675 return false;
676 case X86::MOV8rr:
677 case X86::MOV8rr_NOREX:
678 case X86::MOV16rr:
679 case X86::MOV32rr:
680 case X86::MOV64rr:
681 case X86::MOVSSrr:
682 case X86::MOVSDrr:
683
684 // FP Stack register class copies
685 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
686 case X86::MOV_Fp3264: case X86::MOV_Fp3280:
687 case X86::MOV_Fp6432: case X86::MOV_Fp8032:
688
689 case X86::FsMOVAPSrr:
690 case X86::FsMOVAPDrr:
691 case X86::MOVAPSrr:
692 case X86::MOVAPDrr:
693 case X86::MOVDQArr:
694 case X86::MOVSS2PSrr:
695 case X86::MOVSD2PDrr:
696 case X86::MOVPS2SSrr:
697 case X86::MOVPD2SDrr:
698 case X86::MMX_MOVQ64rr:
699 assert(MI.getNumOperands() >= 2 &&
700 MI.getOperand(0).isReg() &&
701 MI.getOperand(1).isReg() &&
702 "invalid register-register move instruction");
703 SrcReg = MI.getOperand(1).getReg();
704 DstReg = MI.getOperand(0).getReg();
705 SrcSubIdx = MI.getOperand(1).getSubReg();
706 DstSubIdx = MI.getOperand(0).getSubReg();
707 return true;
708 }
709 }
710
711 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
712 int &FrameIndex) const {
713 switch (MI->getOpcode()) {
714 default: break;
715 case X86::MOV8rm:
716 case X86::MOV16rm:
717 case X86::MOV32rm:
718 case X86::MOV64rm:
719 case X86::LD_Fp64m:
720 case X86::MOVSSrm:
721 case X86::MOVSDrm:
722 case X86::MOVAPSrm:
723 case X86::MOVAPDrm:
724 case X86::MOVDQArm:
725 case X86::MMX_MOVD64rm:
726 case X86::MMX_MOVQ64rm:
727 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
728 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() &&
729 MI->getOperand(2).getImm() == 1 &&
730 MI->getOperand(3).getReg() == 0 &&
731 MI->getOperand(4).getImm() == 0) {
732 FrameIndex = MI->getOperand(1).getIndex();
733 return MI->getOperand(0).getReg();
734 }
735 break;
736 }
737 return 0;
738 }
739
740 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
741 int &FrameIndex) const {
742 switch (MI->getOpcode()) {
743 default: break;
744 case X86::MOV8mr:
745 case X86::MOV16mr:
746 case X86::MOV32mr:
747 case X86::MOV64mr:
748 case X86::ST_FpP64m:
749 case X86::MOVSSmr:
750 case X86::MOVSDmr:
751 case X86::MOVAPSmr:
752 case X86::MOVAPDmr:
753 case X86::MOVDQAmr:
754 case X86::MMX_MOVD64mr:
755 case X86::MMX_MOVQ64mr:
756 case X86::MMX_MOVNTQmr:
757 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
758 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() &&
759 MI->getOperand(1).getImm() == 1 &&
760 MI->getOperand(2).getReg() == 0 &&
761 MI->getOperand(3).getImm() == 0) {
762 FrameIndex = MI->getOperand(0).getIndex();
763 return MI->getOperand(X86AddrNumOperands).getReg();
764 }
765 break;
766 }
767 return 0;
768 }
769
770 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
771 /// X86::MOVPC32r.
772 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
773 bool isPICBase = false;
774 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
775 E = MRI.def_end(); I != E; ++I) {
776 MachineInstr *DefMI = I.getOperand().getParent();
777 if (DefMI->getOpcode() != X86::MOVPC32r)
778 return false;
779 assert(!isPICBase && "More than one PIC base?");
780 isPICBase = true;
781 }
782 return isPICBase;
783 }
784
785 /// CanRematLoadWithDispOperand - Return true if a load with the specified
786 /// operand is a candidate for remat: for this to be true we need to know that
787 /// the load will always return the same value, even if moved.
788 static bool CanRematLoadWithDispOperand(const MachineOperand &MO,
789 X86TargetMachine &TM) {
790 // Loads from constant pool entries can be remat'd.
791 if (MO.isCPI()) return true;
792
793 // We can remat globals in some cases.
794 if (MO.isGlobal()) {
795 // If this is a load of a stub, not of the global, we can remat it. This
796 // access will always return the address of the global.
797 if (isGlobalStubReference(MO.getTargetFlags()))
798 return true;
799
800 // If the global itself is constant, we can remat the load.
801 if (GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal()))
802 if (GV->isConstant())
803 return true;
804 }
805 return false;
806 }
807
808 bool
809 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const {
810 switch (MI->getOpcode()) {
811 default: break;
812 case X86::MOV8rm:
813 case X86::MOV16rm:
814 case X86::MOV32rm:
815 case X86::MOV64rm:
816 case X86::LD_Fp64m:
817 case X86::MOVSSrm:
818 case X86::MOVSDrm:
819 case X86::MOVAPSrm:
820 case X86::MOVAPDrm:
821 case X86::MOVDQArm:
822 case X86::MMX_MOVD64rm:
823 case X86::MMX_MOVQ64rm: {
824 // Loads from constant pools are trivially rematerializable.
825 if (MI->getOperand(1).isReg() &&
826 MI->getOperand(2).isImm() &&
827 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
828 CanRematLoadWithDispOperand(MI->getOperand(4), TM)) {
829 unsigned BaseReg = MI->getOperand(1).getReg();
830 if (BaseReg == 0 || BaseReg == X86::RIP)
831 return true;
832 // Allow re-materialization of PIC load.
833 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
834 return false;
835 const MachineFunction &MF = *MI->getParent()->getParent();
836 const MachineRegisterInfo &MRI = MF.getRegInfo();
837 bool isPICBase = false;
838 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
839 E = MRI.def_end(); I != E; ++I) {
840 MachineInstr *DefMI = I.getOperand().getParent();
841 if (DefMI->getOpcode() != X86::MOVPC32r)
842 return false;
843 assert(!isPICBase && "More than one PIC base?");
844 isPICBase = true;
845 }
846 return isPICBase;
847 }
848 return false;
849 }
850
851 case X86::LEA32r:
852 case X86::LEA64r: {
853 if (MI->getOperand(2).isImm() &&
854 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
855 !MI->getOperand(4).isReg()) {
856 // lea fi#, lea GV, etc. are all rematerializable.
857 if (!MI->getOperand(1).isReg())
858 return true;
859 unsigned BaseReg = MI->getOperand(1).getReg();
860 if (BaseReg == 0)
861 return true;
862 // Allow re-materialization of lea PICBase + x.
863 const MachineFunction &MF = *MI->getParent()->getParent();
864 const MachineRegisterInfo &MRI = MF.getRegInfo();
865 return regIsPICBase(BaseReg, MRI);
866 }
867 return false;
868 }
869 }
870
871 // All other instructions marked M_REMATERIALIZABLE are always trivially
872 // rematerializable.
873 return true;
874 }
875
876 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
877 /// would clobber the EFLAGS condition register. Note the result may be
878 /// conservative. If it cannot definitely determine the safety after visiting
879 /// two instructions it assumes it's not safe.
880 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
881 MachineBasicBlock::iterator I) {
882 // It's always safe to clobber EFLAGS at the end of a block.
883 if (I == MBB.end())
884 return true;
885
886 // For compile time consideration, if we are not able to determine the
887 // safety after visiting 2 instructions, we will assume it's not safe.
888 for (unsigned i = 0; i < 2; ++i) {
889 bool SeenDef = false;
890 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) {
891 MachineOperand &MO = I->getOperand(j);
892 if (!MO.isReg())
893 continue;
894 if (MO.getReg() == X86::EFLAGS) {
895 if (MO.isUse())
896 return false;
897 SeenDef = true;
898 }
899 }
900
901 if (SeenDef)
902 // This instruction defines EFLAGS, no need to look any further.
903 return true;
904 ++I;
905
906 // If we make it to the end of the block, it's safe to clobber EFLAGS.
907 if (I == MBB.end())
908 return true;
909 }
910
911 // Conservative answer.
912 return false;
913 }
914
915 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
916 MachineBasicBlock::iterator I,
917 unsigned DestReg, unsigned SubIdx,
918 const MachineInstr *Orig) const {
919 DebugLoc DL = DebugLoc::getUnknownLoc();
920 if (I != MBB.end()) DL = I->getDebugLoc();
921
922 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
923 DestReg = RI.getSubReg(DestReg, SubIdx);
924 SubIdx = 0;
925 }
926
927 // MOV32r0 etc. are implemented with xor which clobbers condition code.
928 // Re-materialize them as movri instructions to avoid side effects.
929 bool Clone = true;
930 unsigned Opc = Orig->getOpcode();
931 switch (Opc) {
932 default: break;
933 case X86::MOV8r0:
934 case X86::MOV16r0:
935 case X86::MOV32r0: {
936 if (!isSafeToClobberEFLAGS(MBB, I)) {
937 switch (Opc) {
938 default: break;
939 case X86::MOV8r0: Opc = X86::MOV8ri; break;
940 case X86::MOV16r0: Opc = X86::MOV16ri; break;
941 case X86::MOV32r0: Opc = X86::MOV32ri; break;
942 }
943 Clone = false;
944 }
945 break;
946 }
947 }
948
949 if (Clone) {
950 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
951 MI->getOperand(0).setReg(DestReg);
952 MBB.insert(I, MI);
953 } else {
954 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
955 }
956
957 MachineInstr *NewMI = prior(I);
958 NewMI->getOperand(0).setSubReg(SubIdx);
959 }
960
961 /// isInvariantLoad - Return true if the specified instruction (which is marked
962 /// mayLoad) is loading from a location whose value is invariant across the
963 /// function. For example, loading a value from the constant pool or from
964 /// from the argument area of a function if it does not change. This should
965 /// only return true of *all* loads the instruction does are invariant (if it
966 /// does multiple loads).
967 bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const {
968 // This code cares about loads from three cases: constant pool entries,
969 // invariant argument slots, and global stubs. In order to handle these cases
970 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV
971 // operand and base our analysis on it. This is safe because the address of
972 // none of these three cases is ever used as anything other than a load base
973 // and X86 doesn't have any instructions that load from multiple places.
974
975 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
976 const MachineOperand &MO = MI->getOperand(i);
977 // Loads from constant pools are trivially invariant.
978 if (MO.isCPI())
979 return true;
980
981 if (MO.isGlobal())
982 return isGlobalStubReference(MO.getTargetFlags());
983
984 // If this is a load from an invariant stack slot, the load is a constant.
985 if (MO.isFI()) {
986 const MachineFrameInfo &MFI =
987 *MI->getParent()->getParent()->getFrameInfo();
988 int Idx = MO.getIndex();
989 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx);
990 }
991 }
992
993 // All other instances of these instructions are presumed to have other
994 // issues.
995 return false;
996 }
997
998 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
999 /// is not marked dead.
1000 static bool hasLiveCondCodeDef(MachineInstr *MI) {
1001 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1002 MachineOperand &MO = MI->getOperand(i);
1003 if (MO.isReg() && MO.isDef() &&
1004 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1005 return true;
1006 }
1007 }
1008 return false;
1009 }
1010
1011 /// convertToThreeAddress - This method must be implemented by targets that
1012 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
1013 /// may be able to convert a two-address instruction into a true
1014 /// three-address instruction on demand. This allows the X86 target (for
1015 /// example) to convert ADD and SHL instructions into LEA instructions if they
1016 /// would require register copies due to two-addressness.
1017 ///
1018 /// This method returns a null pointer if the transformation cannot be
1019 /// performed, otherwise it returns the new instruction.
1020 ///
1021 MachineInstr *
1022 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1023 MachineBasicBlock::iterator &MBBI,
1024 LiveVariables *LV) const {
1025 MachineInstr *MI = MBBI;
1026 MachineFunction &MF = *MI->getParent()->getParent();
1027 // All instructions input are two-addr instructions. Get the known operands.
1028 unsigned Dest = MI->getOperand(0).getReg();
1029 unsigned Src = MI->getOperand(1).getReg();
1030 bool isDead = MI->getOperand(0).isDead();
1031 bool isKill = MI->getOperand(1).isKill();
1032
1033 MachineInstr *NewMI = NULL;
1034 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
1035 // we have better subtarget support, enable the 16-bit LEA generation here.
1036 bool DisableLEA16 = true;
1037
1038 unsigned MIOpc = MI->getOpcode();
1039 switch (MIOpc) {
1040 case X86::SHUFPSrri: {
1041 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1042 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1043
1044 unsigned B = MI->getOperand(1).getReg();
1045 unsigned C = MI->getOperand(2).getReg();
1046 if (B != C) return 0;
1047 unsigned A = MI->getOperand(0).getReg();
1048 unsigned M = MI->getOperand(3).getImm();
1049 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1050 .addReg(A, RegState::Define | getDeadRegState(isDead))
1051 .addReg(B, getKillRegState(isKill)).addImm(M);
1052 break;
1053 }
1054 case X86::SHL64ri: {
1055 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1056 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1057 // the flags produced by a shift yet, so this is safe.
1058 unsigned ShAmt = MI->getOperand(2).getImm();
1059 if (ShAmt == 0 || ShAmt >= 4) return 0;
1060
1061 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1062 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1063 .addReg(0).addImm(1 << ShAmt)
1064 .addReg(Src, getKillRegState(isKill))
1065 .addImm(0);
1066 break;
1067 }
1068 case X86::SHL32ri: {
1069 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1070 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1071 // the flags produced by a shift yet, so this is safe.
1072 unsigned ShAmt = MI->getOperand(2).getImm();
1073 if (ShAmt == 0 || ShAmt >= 4) return 0;
1074
1075 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ?
1076 X86::LEA64_32r : X86::LEA32r;
1077 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1078 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1079 .addReg(0).addImm(1 << ShAmt)
1080 .addReg(Src, getKillRegState(isKill)).addImm(0);
1081 break;
1082 }
1083 case X86::SHL16ri: {
1084 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1085 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1086 // the flags produced by a shift yet, so this is safe.
1087 unsigned ShAmt = MI->getOperand(2).getImm();
1088 if (ShAmt == 0 || ShAmt >= 4) return 0;
1089
1090 if (DisableLEA16) {
1091 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
1092 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1093 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1094 ? X86::LEA64_32r : X86::LEA32r;
1095 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1096 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1097
1098 // Build and insert into an implicit UNDEF value. This is OK because
1099 // well be shifting and then extracting the lower 16-bits.
1100 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1101 MachineInstr *InsMI =
1102 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1103 .addReg(leaInReg)
1104 .addReg(Src, getKillRegState(isKill))
1105 .addImm(X86::SUBREG_16BIT);
1106
1107 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg)
1108 .addReg(0).addImm(1 << ShAmt)
1109 .addReg(leaInReg, RegState::Kill)
1110 .addImm(0);
1111
1112 MachineInstr *ExtMI =
1113 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1114 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1115 .addReg(leaOutReg, RegState::Kill)
1116 .addImm(X86::SUBREG_16BIT);
1117
1118 if (LV) {
1119 // Update live variables
1120 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1121 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1122 if (isKill)
1123 LV->replaceKillInstruction(Src, MI, InsMI);
1124 if (isDead)
1125 LV->replaceKillInstruction(Dest, MI, ExtMI);
1126 }
1127 return ExtMI;
1128 } else {
1129 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1130 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1131 .addReg(0).addImm(1 << ShAmt)
1132 .addReg(Src, getKillRegState(isKill))
1133 .addImm(0);
1134 }
1135 break;
1136 }
1137 default: {
1138 // The following opcodes also sets the condition code register(s). Only
1139 // convert them to equivalent lea if the condition code register def's
1140 // are dead!
1141 if (hasLiveCondCodeDef(MI))
1142 return 0;
1143
1144 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1145 switch (MIOpc) {
1146 default: return 0;
1147 case X86::INC64r:
1148 case X86::INC32r:
1149 case X86::INC64_32r: {
1150 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1151 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1152 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1153 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1154 .addReg(Dest, RegState::Define |
1155 getDeadRegState(isDead)),
1156 Src, isKill, 1);
1157 break;
1158 }
1159 case X86::INC16r:
1160 case X86::INC64_16r:
1161 if (DisableLEA16) return 0;
1162 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1163 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1164 .addReg(Dest, RegState::Define |
1165 getDeadRegState(isDead)),
1166 Src, isKill, 1);
1167 break;
1168 case X86::DEC64r:
1169 case X86::DEC32r:
1170 case X86::DEC64_32r: {
1171 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1172 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1173 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1174 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1175 .addReg(Dest, RegState::Define |
1176 getDeadRegState(isDead)),
1177 Src, isKill, -1);
1178 break;
1179 }
1180 case X86::DEC16r:
1181 case X86::DEC64_16r:
1182 if (DisableLEA16) return 0;
1183 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1184 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1185 .addReg(Dest, RegState::Define |
1186 getDeadRegState(isDead)),
1187 Src, isKill, -1);
1188 break;
1189 case X86::ADD64rr:
1190 case X86::ADD32rr: {
1191 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1192 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1193 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1194 unsigned Src2 = MI->getOperand(2).getReg();
1195 bool isKill2 = MI->getOperand(2).isKill();
1196 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1197 .addReg(Dest, RegState::Define |
1198 getDeadRegState(isDead)),
1199 Src, isKill, Src2, isKill2);
1200 if (LV && isKill2)
1201 LV->replaceKillInstruction(Src2, MI, NewMI);
1202 break;
1203 }
1204 case X86::ADD16rr: {
1205 if (DisableLEA16) return 0;
1206 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1207 unsigned Src2 = MI->getOperand(2).getReg();
1208 bool isKill2 = MI->getOperand(2).isKill();
1209 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1210 .addReg(Dest, RegState::Define |
1211 getDeadRegState(isDead)),
1212 Src, isKill, Src2, isKill2);
1213 if (LV && isKill2)
1214 LV->replaceKillInstruction(Src2, MI, NewMI);
1215 break;
1216 }
1217 case X86::ADD64ri32:
1218 case X86::ADD64ri8:
1219 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1220 if (MI->getOperand(2).isImm())
1221 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1222 .addReg(Dest, RegState::Define |
1223 getDeadRegState(isDead)),
1224 Src, isKill, MI->getOperand(2).getImm());
1225 break;
1226 case X86::ADD32ri:
1227 case X86::ADD32ri8:
1228 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1229 if (MI->getOperand(2).isImm()) {
1230 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1231 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1232 .addReg(Dest, RegState::Define |
1233 getDeadRegState(isDead)),
1234 Src, isKill, MI->getOperand(2).getImm());
1235 }
1236 break;
1237 case X86::ADD16ri:
1238 case X86::ADD16ri8:
1239 if (DisableLEA16) return 0;
1240 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1241 if (MI->getOperand(2).isImm())
1242 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1243 .addReg(Dest, RegState::Define |
1244 getDeadRegState(isDead)),
1245 Src, isKill, MI->getOperand(2).getImm());
1246 break;
1247 case X86::SHL16ri:
1248 if (DisableLEA16) return 0;
1249 case X86::SHL32ri:
1250 case X86::SHL64ri: {
1251 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() &&
1252 "Unknown shl instruction!");
1253 unsigned ShAmt = MI->getOperand(2).getImm();
1254 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
1255 X86AddressMode AM;
1256 AM.Scale = 1 << ShAmt;
1257 AM.IndexReg = Src;
1258 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r
1259 : (MIOpc == X86::SHL32ri
1260 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r);
1261 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1262 .addReg(Dest, RegState::Define |
1263 getDeadRegState(isDead)), AM);
1264 if (isKill)
1265 NewMI->getOperand(3).setIsKill(true);
1266 }
1267 break;
1268 }
1269 }
1270 }
1271 }
1272
1273 if (!NewMI) return 0;
1274
1275 if (LV) { // Update live variables
1276 if (isKill)
1277 LV->replaceKillInstruction(Src, MI, NewMI);
1278 if (isDead)
1279 LV->replaceKillInstruction(Dest, MI, NewMI);
1280 }
1281
1282 MFI->insert(MBBI, NewMI); // Insert the new inst
1283 return NewMI;
1284 }
1285
1286 /// commuteInstruction - We have a few instructions that must be hacked on to
1287 /// commute them.
1288 ///
1289 MachineInstr *
1290 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1291 switch (MI->getOpcode()) {
1292 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1293 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1294 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1295 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1296 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1297 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1298 unsigned Opc;
1299 unsigned Size;
1300 switch (MI->getOpcode()) {
1301 default: llvm_unreachable("Unreachable!");
1302 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1303 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1304 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1305 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1306 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1307 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1308 }
1309 unsigned Amt = MI->getOperand(3).getImm();
1310 if (NewMI) {
1311 MachineFunction &MF = *MI->getParent()->getParent();
1312 MI = MF.CloneMachineInstr(MI);
1313 NewMI = false;
1314 }
1315 MI->setDesc(get(Opc));
1316 MI->getOperand(3).setImm(Size-Amt);
1317 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1318 }
1319 case X86::CMOVB16rr:
1320 case X86::CMOVB32rr:
1321 case X86::CMOVB64rr:
1322 case X86::CMOVAE16rr:
1323 case X86::CMOVAE32rr:
1324 case X86::CMOVAE64rr:
1325 case X86::CMOVE16rr:
1326 case X86::CMOVE32rr:
1327 case X86::CMOVE64rr:
1328 case X86::CMOVNE16rr:
1329 case X86::CMOVNE32rr:
1330 case X86::CMOVNE64rr:
1331 case X86::CMOVBE16rr:
1332 case X86::CMOVBE32rr:
1333 case X86::CMOVBE64rr:
1334 case X86::CMOVA16rr:
1335 case X86::CMOVA32rr:
1336 case X86::CMOVA64rr:
1337 case X86::CMOVL16rr:
1338 case X86::CMOVL32rr:
1339 case X86::CMOVL64rr:
1340 case X86::CMOVGE16rr:
1341 case X86::CMOVGE32rr:
1342 case X86::CMOVGE64rr:
1343 case X86::CMOVLE16rr:
1344 case X86::CMOVLE32rr:
1345 case X86::CMOVLE64rr:
1346 case X86::CMOVG16rr:
1347 case X86::CMOVG32rr:
1348 case X86::CMOVG64rr:
1349 case X86::CMOVS16rr:
1350 case X86::CMOVS32rr:
1351 case X86::CMOVS64rr:
1352 case X86::CMOVNS16rr:
1353 case X86::CMOVNS32rr:
1354 case X86::CMOVNS64rr:
1355 case X86::CMOVP16rr:
1356 case X86::CMOVP32rr:
1357 case X86::CMOVP64rr:
1358 case X86::CMOVNP16rr:
1359 case X86::CMOVNP32rr:
1360 case X86::CMOVNP64rr:
1361 case X86::CMOVO16rr:
1362 case X86::CMOVO32rr:
1363 case X86::CMOVO64rr:
1364 case X86::CMOVNO16rr:
1365 case X86::CMOVNO32rr:
1366 case X86::CMOVNO64rr: {
1367 unsigned Opc = 0;
1368 switch (MI->getOpcode()) {
1369 default: break;
1370 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
1371 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
1372 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
1373 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1374 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1375 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1376 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
1377 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
1378 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
1379 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1380 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1381 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1382 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1383 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1384 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1385 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
1386 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
1387 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
1388 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
1389 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
1390 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
1391 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1392 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1393 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1394 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1395 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1396 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1397 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
1398 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
1399 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
1400 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
1401 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
1402 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
1403 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1404 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1405 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1406 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
1407 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
1408 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
1409 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1410 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1411 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1412 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
1413 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
1414 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
1415 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1416 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1417 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1418 }
1419 if (NewMI) {
1420 MachineFunction &MF = *MI->getParent()->getParent();
1421 MI = MF.CloneMachineInstr(MI);
1422 NewMI = false;
1423 }
1424 MI->setDesc(get(Opc));
1425 // Fallthrough intended.
1426 }
1427 default:
1428 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1429 }
1430 }
1431
1432 static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1433 switch (BrOpc) {
1434 default: return X86::COND_INVALID;
1435 case X86::JE: return X86::COND_E;
1436 case X86::JNE: return X86::COND_NE;
1437 case X86::JL: return X86::COND_L;
1438 case X86::JLE: return X86::COND_LE;
1439 case X86::JG: return X86::COND_G;
1440 case X86::JGE: return X86::COND_GE;
1441 case X86::JB: return X86::COND_B;
1442 case X86::JBE: return X86::COND_BE;
1443 case X86::JA: return X86::COND_A;
1444 case X86::JAE: return X86::COND_AE;
1445 case X86::JS: return X86::COND_S;
1446 case X86::JNS: return X86::COND_NS;
1447 case X86::JP: return X86::COND_P;
1448 case X86::JNP: return X86::COND_NP;
1449 case X86::JO: return X86::COND_O;
1450 case X86::JNO: return X86::COND_NO;
1451 }
1452 }
1453
1454 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1455 switch (CC) {
1456 default: llvm_unreachable("Illegal condition code!");
1457 case X86::COND_E: return X86::JE;
1458 case X86::COND_NE: return X86::JNE;
1459 case X86::COND_L: return X86::JL;
1460 case X86::COND_LE: return X86::JLE;
1461 case X86::COND_G: return X86::JG;
1462 case X86::COND_GE: return X86::JGE;
1463 case X86::COND_B: return X86::JB;
1464 case X86::COND_BE: return X86::JBE;
1465 case X86::COND_A: return X86::JA;
1466 case X86::COND_AE: return X86::JAE;
1467 case X86::COND_S: return X86::JS;
1468 case X86::COND_NS: return X86::JNS;
1469 case X86::COND_P: return X86::JP;
1470 case X86::COND_NP: return X86::JNP;
1471 case X86::COND_O: return X86::JO;
1472 case X86::COND_NO: return X86::JNO;
1473 }
1474 }
1475
1476 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
1477 /// e.g. turning COND_E to COND_NE.
1478 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1479 switch (CC) {
1480 default: llvm_unreachable("Illegal condition code!");
1481 case X86::COND_E: return X86::COND_NE;
1482 case X86::COND_NE: return X86::COND_E;
1483 case X86::COND_L: return X86::COND_GE;
1484 case X86::COND_LE: return X86::COND_G;
1485 case X86::COND_G: return X86::COND_LE;
1486 case X86::COND_GE: return X86::COND_L;
1487 case X86::COND_B: return X86::COND_AE;
1488 case X86::COND_BE: return X86::COND_A;
1489 case X86::COND_A: return X86::COND_BE;
1490 case X86::COND_AE: return X86::COND_B;
1491 case X86::COND_S: return X86::COND_NS;
1492 case X86::COND_NS: return X86::COND_S;
1493 case X86::COND_P: return X86::COND_NP;
1494 case X86::COND_NP: return X86::COND_P;
1495 case X86::COND_O: return X86::COND_NO;
1496 case X86::COND_NO: return X86::COND_O;
1497 }
1498 }
1499
1500 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1501 const TargetInstrDesc &TID = MI->getDesc();
1502 if (!TID.isTerminator()) return false;
1503
1504 // Conditional branch is a special case.
1505 if (TID.isBranch() && !TID.isBarrier())
1506 return true;
1507 if (!TID.isPredicable())
1508 return true;
1509 return !isPredicated(MI);
1510 }
1511
1512 // For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1513 static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1514 const X86InstrInfo &TII) {
1515 if (MI->getOpcode() == X86::FP_REG_KILL)
1516 return false;
1517 return TII.isUnpredicatedTerminator(MI);
1518 }
1519
1520 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1521 MachineBasicBlock *&TBB,
1522 MachineBasicBlock *&FBB,
1523 SmallVectorImpl<MachineOperand> &Cond,
1524 bool AllowModify) const {
1525 // Start from the bottom of the block and work up, examining the
1526 // terminator instructions.
1527 MachineBasicBlock::iterator I = MBB.end();
1528 while (I != MBB.begin()) {
1529 --I;
1530 // Working from the bottom, when we see a non-terminator
1531 // instruction, we're done.
1532 if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1533 break;
1534 // A terminator that isn't a branch can't easily be handled
1535 // by this analysis.
1536 if (!I->getDesc().isBranch())
1537 return true;
1538 // Handle unconditional branches.
1539 if (I->getOpcode() == X86::JMP) {
1540 if (!AllowModify) {
1541 TBB = I->getOperand(0).getMBB();
1542 continue;
1543 }
1544
1545 // If the block has any instructions after a JMP, delete them.
1546 while (next(I) != MBB.end())
1547 next(I)->eraseFromParent();
1548 Cond.clear();
1549 FBB = 0;
1550 // Delete the JMP if it's equivalent to a fall-through.
1551 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1552 TBB = 0;
1553 I->eraseFromParent();
1554 I = MBB.end();
1555 continue;
1556 }
1557 // TBB is used to indicate the unconditinal destination.
1558 TBB = I->getOperand(0).getMBB();
1559 continue;
1560 }
1561 // Handle conditional branches.
1562 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1563 if (BranchCode == X86::COND_INVALID)
1564 return true; // Can't handle indirect branch.
1565 // Working from the bottom, handle the first conditional branch.
1566 if (Cond.empty()) {
1567 FBB = TBB;
1568 TBB = I->getOperand(0).getMBB();
1569 Cond.push_back(MachineOperand::CreateImm(BranchCode));
1570 continue;
1571 }
1572 // Handle subsequent conditional branches. Only handle the case
1573 // where all conditional branches branch to the same destination
1574 // and their condition opcodes fit one of the special
1575 // multi-branch idioms.
1576 assert(Cond.size() == 1);
1577 assert(TBB);
1578 // Only handle the case where all conditional branches branch to
1579 // the same destination.
1580 if (TBB != I->getOperand(0).getMBB())
1581 return true;
1582 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1583 // If the conditions are the same, we can leave them alone.
1584 if (OldBranchCode == BranchCode)
1585 continue;
1586 // If they differ, see if they fit one of the known patterns.
1587 // Theoretically we could handle more patterns here, but
1588 // we shouldn't expect to see them if instruction selection
1589 // has done a reasonable job.
1590 if ((OldBranchCode == X86::COND_NP &&
1591 BranchCode == X86::COND_E) ||
1592 (OldBranchCode == X86::COND_E &&
1593 BranchCode == X86::COND_NP))
1594 BranchCode = X86::COND_NP_OR_E;
1595 else if ((OldBranchCode == X86::COND_P &&
1596 BranchCode == X86::COND_NE) ||
1597 (OldBranchCode == X86::COND_NE &&
1598 BranchCode == X86::COND_P))
1599 BranchCode = X86::COND_NE_OR_P;
1600 else
1601 return true;
1602 // Update the MachineOperand.
1603 Cond[0].setImm(BranchCode);
1604 }
1605
1606 return false;
1607 }
1608
1609 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1610 MachineBasicBlock::iterator I = MBB.end();
1611 unsigned Count = 0;
1612
1613 while (I != MBB.begin()) {
1614 --I;
1615 if (I->getOpcode() != X86::JMP &&
1616 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1617 break;
1618 // Remove the branch.
1619 I->eraseFromParent();
1620 I = MBB.end();
1621 ++Count;
1622 }
1623
1624 return Count;
1625 }
1626
1627 unsigned
1628 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1629 MachineBasicBlock *FBB,
1630 const SmallVectorImpl<MachineOperand> &Cond) const {
1631 // FIXME this should probably have a DebugLoc operand
1632 DebugLoc dl = DebugLoc::getUnknownLoc();
1633 // Shouldn't be a fall through.
1634 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1635 assert((Cond.size() == 1 || Cond.size() == 0) &&
1636 "X86 branch conditions have one component!");
1637
1638 if (Cond.empty()) {
1639 // Unconditional branch?
1640 assert(!FBB && "Unconditional branch with multiple successors!");
1641 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB);
1642 return 1;
1643 }
1644
1645 // Conditional branch.
1646 unsigned Count = 0;
1647 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1648 switch (CC) {
1649 case X86::COND_NP_OR_E:
1650 // Synthesize NP_OR_E with two branches.
1651 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB);
1652 ++Count;
1653 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB);
1654 ++Count;
1655 break;
1656 case X86::COND_NE_OR_P:
1657 // Synthesize NE_OR_P with two branches.
1658 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB);
1659 ++Count;
1660 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB);
1661 ++Count;
1662 break;
1663 default: {
1664 unsigned Opc = GetCondBranchFromCond(CC);
1665 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1666 ++Count;
1667 }
1668 }
1669 if (FBB) {
1670 // Two-way Conditional branch. Insert the second branch.
1671 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB);
1672 ++Count;
1673 }
1674 return Count;
1675 }
1676
1677 /// isHReg - Test if the given register is a physical h register.
1678 static bool isHReg(unsigned Reg) {
1679 return X86::GR8_ABCD_HRegClass.contains(Reg);
1680 }
1681
1682 bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1683 MachineBasicBlock::iterator MI,
1684 unsigned DestReg, unsigned SrcReg,
1685 const TargetRegisterClass *DestRC,
1686 const TargetRegisterClass *SrcRC) const {
1687 DebugLoc DL = DebugLoc::getUnknownLoc();
1688 if (MI != MBB.end()) DL = MI->getDebugLoc();
1689
1690 // Determine if DstRC and SrcRC have a common superclass in common.
1691 const TargetRegisterClass *CommonRC = DestRC;
1692 if (DestRC == SrcRC)
1693 /* Source and destination have the same register class. */;
1694 else if (CommonRC->hasSuperClass(SrcRC))
1695 CommonRC = SrcRC;
1696 else if (!DestRC->hasSubClass(SrcRC)) {
1697 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1698 // but we want to copy then as GR64. Similarly, for GR32_NOREX and
1699 // GR32_NOSP, copy as GR32.
1700 if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1701 DestRC->hasSuperClass(&X86::GR64RegClass))
1702 CommonRC = &X86::GR64RegClass;
1703 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1704 DestRC->hasSuperClass(&X86::GR32RegClass))
1705 CommonRC = &X86::GR32RegClass;
1706 else
1707 CommonRC = 0;
1708 }
1709
1710 if (CommonRC) {
1711 unsigned Opc;
1712 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1713 Opc = X86::MOV64rr;
1714 } else if (CommonRC == &X86::GR32RegClass ||
1715 CommonRC == &X86::GR32_NOSPRegClass) {
1716 Opc = X86::MOV32rr;
1717 } else if (CommonRC == &X86::GR16RegClass) {
1718 Opc = X86::MOV16rr;
1719 } else if (CommonRC == &X86::GR8RegClass) {
1720 // Copying to or from a physical H register on x86-64 requires a NOREX
1721 // move. Otherwise use a normal move.
1722 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1723 TM.getSubtarget<X86Subtarget>().is64Bit())
1724 Opc = X86::MOV8rr_NOREX;
1725 else
1726 Opc = X86::MOV8rr;
1727 } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1728 Opc = X86::MOV64rr;
1729 } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1730 Opc = X86::MOV32rr;
1731 } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1732 Opc = X86::MOV16rr;
1733 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1734 Opc = X86::MOV8rr;
1735 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1736 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1737 Opc = X86::MOV8rr_NOREX;
1738 else
1739 Opc = X86::MOV8rr;
1740 } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1741 CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1742 Opc = X86::MOV64rr;
1743 } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1744 Opc = X86::MOV32rr;
1745 } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1746 Opc = X86::MOV16rr;
1747 } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1748 Opc = X86::MOV8rr;
1749 } else if (CommonRC == &X86::RFP32RegClass) {
1750 Opc = X86::MOV_Fp3232;
1751 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1752 Opc = X86::MOV_Fp6464;
1753 } else if (CommonRC == &X86::RFP80RegClass) {
1754 Opc = X86::MOV_Fp8080;
1755 } else if (CommonRC == &X86::FR32RegClass) {
1756 Opc = X86::FsMOVAPSrr;
1757 } else if (CommonRC == &X86::FR64RegClass) {
1758 Opc = X86::FsMOVAPDrr;
1759 } else if (CommonRC == &X86::VR128RegClass) {
1760 Opc = X86::MOVAPSrr;
1761 } else if (CommonRC == &X86::VR64RegClass) {
1762 Opc = X86::MMX_MOVQ64rr;
1763 } else {
1764 return false;
1765 }
1766 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1767 return true;
1768 }
1769
1770 // Moving EFLAGS to / from another register requires a push and a pop.
1771 if (SrcRC == &X86::CCRRegClass) {
1772 if (SrcReg != X86::EFLAGS)
1773 return false;
1774 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1775 BuildMI(MBB, MI, DL, get(X86::PUSHFQ));
1776 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1777 return true;
1778 } else if (DestRC == &X86::GR32RegClass ||
1779 DestRC == &X86::GR32_NOSPRegClass) {
1780 BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1781 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1782 return true;
1783 }
1784 } else if (DestRC == &X86::CCRRegClass) {
1785 if (DestReg != X86::EFLAGS)
1786 return false;
1787 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1788 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1789 BuildMI(MBB, MI, DL, get(X86::POPFQ));
1790 return true;
1791 } else if (SrcRC == &X86::GR32RegClass ||
1792 DestRC == &X86::GR32_NOSPRegClass) {
1793 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1794 BuildMI(MBB, MI, DL, get(X86::POPFD));
1795 return true;
1796 }
1797 }
1798
1799 // Moving from ST(0) turns into FpGET_ST0_32 etc.
1800 if (SrcRC == &X86::RSTRegClass) {
1801 // Copying from ST(0)/ST(1).
1802 if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1803 // Can only copy from ST(0)/ST(1) right now
1804 return false;
1805 bool isST0 = SrcReg == X86::ST0;
1806 unsigned Opc;
1807 if (DestRC == &X86::RFP32RegClass)
1808 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1809 else if (DestRC == &X86::RFP64RegClass)
1810 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1811 else {
1812 if (DestRC != &X86::RFP80RegClass)
1813 return false;
1814 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1815 }
1816 BuildMI(MBB, MI, DL, get(Opc), DestReg);
1817 return true;
1818 }
1819
1820 // Moving to ST(0) turns into FpSET_ST0_32 etc.
1821 if (DestRC == &X86::RSTRegClass) {
1822 // Copying to ST(0) / ST(1).
1823 if (DestReg != X86::ST0 && DestReg != X86::ST1)
1824 // Can only copy to TOS right now
1825 return false;
1826 bool isST0 = DestReg == X86::ST0;
1827 unsigned Opc;
1828 if (SrcRC == &X86::RFP32RegClass)
1829 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
1830 else if (SrcRC == &X86::RFP64RegClass)
1831 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
1832 else {
1833 if (SrcRC != &X86::RFP80RegClass)
1834 return false;
1835 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
1836 }
1837 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
1838 return true;
1839 }
1840
1841 // Not yet supported!
1842 return false;
1843 }
1844
1845 static unsigned getStoreRegOpcode(unsigned SrcReg,
1846 const TargetRegisterClass *RC,
1847 bool isStackAligned,
1848 TargetMachine &TM) {
1849 unsigned Opc = 0;
1850 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1851 Opc = X86::MOV64mr;
1852 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1853 Opc = X86::MOV32mr;
1854 } else if (RC == &X86::GR16RegClass) {
1855 Opc = X86::MOV16mr;
1856 } else if (RC == &X86::GR8RegClass) {
1857 // Copying to or from a physical H register on x86-64 requires a NOREX
1858 // move. Otherwise use a normal move.
1859 if (isHReg(SrcReg) &&
1860 TM.getSubtarget<X86Subtarget>().is64Bit())
1861 Opc = X86::MOV8mr_NOREX;
1862 else
1863 Opc = X86::MOV8mr;
1864 } else if (RC == &X86::GR64_ABCDRegClass) {
1865 Opc = X86::MOV64mr;
1866 } else if (RC == &X86::GR32_ABCDRegClass) {
1867 Opc = X86::MOV32mr;
1868 } else if (RC == &X86::GR16_ABCDRegClass) {
1869 Opc = X86::MOV16mr;
1870 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1871 Opc = X86::MOV8mr;
1872 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1873 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1874 Opc = X86::MOV8mr_NOREX;
1875 else
1876 Opc = X86::MOV8mr;
1877 } else if (RC == &X86::GR64_NOREXRegClass ||
1878 RC == &X86::GR64_NOREX_NOSPRegClass) {
1879 Opc = X86::MOV64mr;
1880 } else if (RC == &X86::GR32_NOREXRegClass) {
1881 Opc = X86::MOV32mr;
1882 } else if (RC == &X86::GR16_NOREXRegClass) {
1883 Opc = X86::MOV16mr;
1884 } else if (RC == &X86::GR8_NOREXRegClass) {
1885 Opc = X86::MOV8mr;
1886 } else if (RC == &X86::RFP80RegClass) {
1887 Opc = X86::ST_FpP80m; // pops
1888 } else if (RC == &X86::RFP64RegClass) {
1889 Opc = X86::ST_Fp64m;
1890 } else if (RC == &X86::RFP32RegClass) {
1891 Opc = X86::ST_Fp32m;
1892 } else if (RC == &X86::FR32RegClass) {
1893 Opc = X86::MOVSSmr;
1894 } else if (RC == &X86::FR64RegClass) {
1895 Opc = X86::MOVSDmr;
1896 } else if (RC == &X86::VR128RegClass) {
1897 // If stack is realigned we can use aligned stores.
1898 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
1899 } else if (RC == &X86::VR64RegClass) {
1900 Opc = X86::MMX_MOVQ64mr;
1901 } else {
1902 llvm_unreachable("Unknown regclass");
1903 }
1904
1905 return Opc;
1906 }
1907
1908 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1909 MachineBasicBlock::iterator MI,
1910 unsigned SrcReg, bool isKill, int FrameIdx,
1911 const TargetRegisterClass *RC) const {
1912 const MachineFunction &MF = *MBB.getParent();
1913 bool isAligned = (RI.getStackAlignment() >= 16) ||
1914 RI.needsStackRealignment(MF);
1915 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1916 DebugLoc DL = DebugLoc::getUnknownLoc();
1917 if (MI != MBB.end()) DL = MI->getDebugLoc();
1918 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
1919 .addReg(SrcReg, getKillRegState(isKill));
1920 }
1921
1922 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
1923 bool isKill,
1924 SmallVectorImpl<MachineOperand> &Addr,
1925 const TargetRegisterClass *RC,
1926 SmallVectorImpl<MachineInstr*> &NewMIs) const {
1927 bool isAligned = (RI.getStackAlignment() >= 16) ||
1928 RI.needsStackRealignment(MF);
1929 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
1930 DebugLoc DL = DebugLoc::getUnknownLoc();
1931 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
1932 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
1933 MIB.addOperand(Addr[i]);
1934 MIB.addReg(SrcReg, getKillRegState(isKill));
1935 NewMIs.push_back(MIB);
1936 }
1937
1938 static unsigned getLoadRegOpcode(unsigned DestReg,
1939 const TargetRegisterClass *RC,
1940 bool isStackAligned,
1941 const TargetMachine &TM) {
1942 unsigned Opc = 0;
1943 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
1944 Opc = X86::MOV64rm;
1945 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
1946 Opc = X86::MOV32rm;
1947 } else if (RC == &X86::GR16RegClass) {
1948 Opc = X86::MOV16rm;
1949 } else if (RC == &X86::GR8RegClass) {
1950 // Copying to or from a physical H register on x86-64 requires a NOREX
1951 // move. Otherwise use a normal move.
1952 if (isHReg(DestReg) &&
1953 TM.getSubtarget<X86Subtarget>().is64Bit())
1954 Opc = X86::MOV8rm_NOREX;
1955 else
1956 Opc = X86::MOV8rm;
1957 } else if (RC == &X86::GR64_ABCDRegClass) {
1958 Opc = X86::MOV64rm;
1959 } else if (RC == &X86::GR32_ABCDRegClass) {
1960 Opc = X86::MOV32rm;
1961 } else if (RC == &X86::GR16_ABCDRegClass) {
1962 Opc = X86::MOV16rm;
1963 } else if (RC == &X86::GR8_ABCD_LRegClass) {
1964 Opc = X86::MOV8rm;
1965 } else if (RC == &X86::GR8_ABCD_HRegClass) {
1966 if (TM.getSubtarget<X86Subtarget>().is64Bit())
1967 Opc = X86::MOV8rm_NOREX;
1968 else
1969 Opc = X86::MOV8rm;
1970 } else if (RC == &X86::GR64_NOREXRegClass ||
1971 RC == &X86::GR64_NOREX_NOSPRegClass) {
1972 Opc = X86::MOV64rm;
1973 } else if (RC == &X86::GR32_NOREXRegClass) {
1974 Opc = X86::MOV32rm;
1975 } else if (RC == &X86::GR16_NOREXRegClass) {
1976 Opc = X86::MOV16rm;
1977 } else if (RC == &X86::GR8_NOREXRegClass) {
1978 Opc = X86::MOV8rm;
1979 } else if (RC == &X86::RFP80RegClass) {
1980 Opc = X86::LD_Fp80m;
1981 } else if (RC == &X86::RFP64RegClass) {
1982 Opc = X86::LD_Fp64m;
1983 } else if (RC == &X86::RFP32RegClass) {
1984 Opc = X86::LD_Fp32m;
1985 } else if (RC == &X86::FR32RegClass) {
1986 Opc = X86::MOVSSrm;
1987 } else if (RC == &X86::FR64RegClass) {
1988 Opc = X86::MOVSDrm;
1989 } else if (RC == &X86::VR128RegClass) {
1990 // If stack is realigned we can use aligned loads.
1991 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
1992 } else if (RC == &X86::VR64RegClass) {
1993 Opc = X86::MMX_MOVQ64rm;
1994 } else {
1995 llvm_unreachable("Unknown regclass");
1996 }
1997
1998 return Opc;
1999 }
2000
2001 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2002 MachineBasicBlock::iterator MI,
2003 unsigned DestReg, int FrameIdx,
2004 const TargetRegisterClass *RC) const{
2005 const MachineFunction &MF = *MBB.getParent();
2006 bool isAligned = (RI.getStackAlignment() >= 16) ||
2007 RI.needsStackRealignment(MF);
2008 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2009 DebugLoc DL = DebugLoc::getUnknownLoc();
2010 if (MI != MBB.end()) DL = MI->getDebugLoc();
2011 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2012 }
2013
2014 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2015 SmallVectorImpl<MachineOperand> &Addr,
2016 const TargetRegisterClass *RC,
2017 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2018 bool isAligned = (RI.getStackAlignment() >= 16) ||
2019 RI.needsStackRealignment(MF);
2020 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2021 DebugLoc DL = DebugLoc::getUnknownLoc();
2022 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2023 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2024 MIB.addOperand(Addr[i]);
2025 NewMIs.push_back(MIB);
2026 }
2027
2028 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2029 MachineBasicBlock::iterator MI,
2030 const std::vector<CalleeSavedInfo> &CSI) const {
2031 if (CSI.empty())
2032 return false;
2033
2034 DebugLoc DL = DebugLoc::getUnknownLoc();
2035 if (MI != MBB.end()) DL = MI->getDebugLoc();
2036
2037 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2038 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2039 unsigned SlotSize = is64Bit ? 8 : 4;
2040
2041 MachineFunction &MF = *MBB.getParent();
2042 unsigned FPReg = RI.getFrameRegister(MF);
2043 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2044 unsigned CalleeFrameSize = 0;
2045
2046 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2047 for (unsigned i = CSI.size(); i != 0; --i) {
2048 unsigned Reg = CSI[i-1].getReg();
2049 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2050 // Add the callee-saved register as live-in. It's killed at the spill.
2051 MBB.addLiveIn(Reg);
2052 if (Reg == FPReg)
2053 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2054 continue;
2055 if (RegClass != &X86::VR128RegClass && !isWin64) {
2056 CalleeFrameSize += SlotSize;
2057 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2058 } else {
2059 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2060 }
2061 }
2062
2063 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2064 return true;
2065 }
2066
2067 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2068 MachineBasicBlock::iterator MI,
2069 const std::vector<CalleeSavedInfo> &CSI) const {
2070 if (CSI.empty())
2071 return false;
2072
2073 DebugLoc DL = DebugLoc::getUnknownLoc();
2074 if (MI != MBB.end()) DL = MI->getDebugLoc();
2075
2076 MachineFunction &MF = *MBB.getParent();
2077 unsigned FPReg = RI.getFrameRegister(MF);
2078 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2079 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2080 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2081 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2082 unsigned Reg = CSI[i].getReg();
2083 if (Reg == FPReg)
2084 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2085 continue;
2086 const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2087 if (RegClass != &X86::VR128RegClass && !isWin64) {
2088 BuildMI(MBB, MI, DL, get(Opc), Reg);
2089 } else {
2090 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2091 }
2092 }
2093 return true;
2094 }
2095
2096 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2097 const SmallVectorImpl<MachineOperand> &MOs,
2098 MachineInstr *MI,
2099 const TargetInstrInfo &TII) {
2100 // Create the base instruction with the memory operand as the first part.
2101 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2102 MI->getDebugLoc(), true);
2103 MachineInstrBuilder MIB(NewMI);
2104 unsigned NumAddrOps = MOs.size();
2105 for (unsigned i = 0; i != NumAddrOps; ++i)
2106 MIB.addOperand(MOs[i]);
2107 if (NumAddrOps < 4) // FrameIndex only
2108 addOffset(MIB, 0);
2109
2110 // Loop over the rest of the ri operands, converting them over.
2111 unsigned NumOps = MI->getDesc().getNumOperands()-2;
2112 for (unsigned i = 0; i != NumOps; ++i) {
2113 MachineOperand &MO = MI->getOperand(i+2);
2114 MIB.addOperand(MO);
2115 }
2116 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2117 MachineOperand &MO = MI->getOperand(i);
2118 MIB.addOperand(MO);
2119 }
2120 return MIB;
2121 }
2122
2123 static MachineInstr *FuseInst(MachineFunction &MF,
2124 unsigned Opcode, unsigned OpNo,
2125 const SmallVectorImpl<MachineOperand> &MOs,
2126 MachineInstr *MI, const TargetInstrInfo &TII) {
2127 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2128 MI->getDebugLoc(), true);
2129 MachineInstrBuilder MIB(NewMI);
2130
2131 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2132 MachineOperand &MO = MI->getOperand(i);
2133 if (i == OpNo) {
2134 assert(MO.isReg() && "Expected to fold into reg operand!");
2135 unsigned NumAddrOps = MOs.size();
2136 for (unsigned i = 0; i != NumAddrOps; ++i)
2137 MIB.addOperand(MOs[i]);
2138 if (NumAddrOps < 4) // FrameIndex only
2139 addOffset(MIB, 0);
2140 } else {
2141 MIB.addOperand(MO);
2142 }
2143 }
2144 return MIB;
2145 }
2146
2147 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2148 const SmallVectorImpl<MachineOperand> &MOs,
2149 MachineInstr *MI) {
2150 MachineFunction &MF = *MI->getParent()->getParent();
2151 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2152
2153 unsigned NumAddrOps = MOs.size();
2154 for (unsigned i = 0; i != NumAddrOps; ++i)
2155 MIB.addOperand(MOs[i]);
2156 if (NumAddrOps < 4) // FrameIndex only
2157 addOffset(MIB, 0);
2158 return MIB.addImm(0);
2159 }
2160
2161 MachineInstr*
2162 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2163 MachineInstr *MI, unsigned i,
2164 const SmallVectorImpl<MachineOperand> &MOs,
2165 unsigned Size, unsigned Align) const {
2166 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2167 bool isTwoAddrFold = false;
2168 unsigned NumOps = MI->getDesc().getNumOperands();
2169 bool isTwoAddr = NumOps > 1 &&
2170 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2171
2172 MachineInstr *NewMI = NULL;
2173 // Folding a memory location into the two-address part of a two-address
2174 // instruction is different than folding it other places. It requires
2175 // replacing the *two* registers with the memory location.
2176 if (isTwoAddr && NumOps >= 2 && i < 2 &&
2177 MI->getOperand(0).isReg() &&
2178 MI->getOperand(1).isReg() &&
2179 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2180 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2181 isTwoAddrFold = true;
2182 } else if (i == 0) { // If operand 0
2183 if (MI->getOpcode() == X86::MOV16r0)
2184 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2185 else if (MI->getOpcode() == X86::MOV32r0)
2186 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2187 else if (MI->getOpcode() == X86::MOV8r0)
2188 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2189 if (NewMI)
2190 return NewMI;
2191
2192 OpcodeTablePtr = &RegOp2MemOpTable0;
2193 } else if (i == 1) {
2194 OpcodeTablePtr = &RegOp2MemOpTable1;
2195 } else if (i == 2) {
2196 OpcodeTablePtr = &RegOp2MemOpTable2;
2197 }
2198
2199 // If table selected...
2200 if (OpcodeTablePtr) {
2201 // Find the Opcode to fuse
2202 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2203 OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2204 if (I != OpcodeTablePtr->end()) {
2205 unsigned Opcode = I->second.first;
2206 unsigned MinAlign = I->second.second;
2207 if (Align < MinAlign)
2208 return NULL;
2209 bool NarrowToMOV32rm = false;
2210 if (Size) {
2211 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2212 if (Size < RCSize) {
2213 // Check if it's safe to fold the load. If the size of the object is
2214 // narrower than the load width, then it's not.
2215 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2216 return NULL;
2217 // If this is a 64-bit load, but the spill slot is 32, then we can do
2218 // a 32-bit load which is implicitly zero-extended. This likely is due
2219 // to liveintervalanalysis remat'ing a load from stack slot.
2220 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2221 return NULL;
2222 Opcode = X86::MOV32rm;
2223 NarrowToMOV32rm = true;
2224 }
2225 }
2226
2227 if (isTwoAddrFold)
2228 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2229 else
2230 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2231
2232 if (NarrowToMOV32rm) {
2233 // If this is the special case where we use a MOV32rm to load a 32-bit
2234 // value and zero-extend the top bits. Change the destination register
2235 // to a 32-bit one.
2236 unsigned DstReg = NewMI->getOperand(0).getReg();
2237 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2238 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2239 4/*x86_subreg_32bit*/));
2240 else
2241 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2242 }
2243 return NewMI;
2244 }
2245 }
2246
2247 // No fusion
2248 if (PrintFailedFusing)
2249 errs() << "We failed to fuse operand " << i << " in " << *MI;
2250 return NULL;
2251 }
2252
2253
2254 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2255 MachineInstr *MI,
2256 const SmallVectorImpl<unsigned> &Ops,
2257 int FrameIndex) const {
2258 // Check switch flag
2259 if (NoFusing) return NULL;
2260
2261 const MachineFrameInfo *MFI = MF.getFrameInfo();
2262 unsigned Size = MFI->getObjectSize(FrameIndex);
2263 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2264 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2265 unsigned NewOpc = 0;
2266 unsigned RCSize = 0;
2267 switch (MI->getOpcode()) {
2268 default: return NULL;
2269 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
2270 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2271 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2272 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2273 }
2274 // Check if it's safe to fold the load. If the size of the object is
2275 // narrower than the load width, then it's not.
2276 if (Size < RCSize)
2277 return NULL;
2278 // Change to CMPXXri r, 0 first.
2279 MI->setDesc(get(NewOpc));
2280 MI->getOperand(1).ChangeToImmediate(0);
2281 } else if (Ops.size() != 1)
2282 return NULL;
2283
2284 SmallVector<MachineOperand,4> MOs;
2285 MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2286 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2287 }
2288
2289 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2290 MachineInstr *MI,
2291 const SmallVectorImpl<unsigned> &Ops,
2292 MachineInstr *LoadMI) const {
2293 // Check switch flag
2294 if (NoFusing) return NULL;
2295
2296 // Determine the alignment of the load.
2297 unsigned Alignment = 0;
2298 if (LoadMI->hasOneMemOperand())
2299 Alignment = LoadMI->memoperands_begin()->getAlignment();
2300 else if (LoadMI->getOpcode() == X86::V_SET0 ||
2301 LoadMI->getOpcode() == X86::V_SETALLONES)
2302 Alignment = 16;
2303 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2304 unsigned NewOpc = 0;
2305 switch (MI->getOpcode()) {
2306 default: return NULL;
2307 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
2308 case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2309 case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2310 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2311 }
2312 // Change to CMPXXri r, 0 first.
2313 MI->setDesc(get(NewOpc));
2314 MI->getOperand(1).ChangeToImmediate(0);
2315 } else if (Ops.size() != 1)
2316 return NULL;
2317
2318 SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2319 if (LoadMI->getOpcode() == X86::V_SET0 ||
2320 LoadMI->getOpcode() == X86::V_SETALLONES) {
2321 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
2322 // Create a constant-pool entry and operands to load from it.
2323
2324 // x86-32 PIC requires a PIC base register for constant pools.
2325 unsigned PICBase = 0;
2326 if (TM.getRelocationModel() == Reloc::PIC_) {
2327 if (TM.getSubtarget<X86Subtarget>().is64Bit())
2328 PICBase = X86::RIP;
2329 else
2330 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2331 // This doesn't work for several reasons.
2332 // 1. GlobalBaseReg may have been spilled.
2333 // 2. It may not be live at MI.
2334 return false;
2335 }
2336
2337 // Create a v4i32 constant-pool entry.
2338 MachineConstantPool &MCP = *MF.getConstantPool();
2339 const VectorType *Ty =
2340 VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2341 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ?
2342 Constant::getNullValue(Ty) :
2343 Constant::getAllOnesValue(Ty);
2344 unsigned CPI = MCP.getConstantPoolIndex(C, 16);
2345
2346 // Create operands to load from the constant pool entry.
2347 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2348 MOs.push_back(MachineOperand::CreateImm(1));
2349 MOs.push_back(MachineOperand::CreateReg(0, false));
2350 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2351 MOs.push_back(MachineOperand::CreateReg(0, false));
2352 } else {
2353 // Folding a normal load. Just copy the load's address operands.
2354 unsigned NumOps = LoadMI->getDesc().getNumOperands();
2355 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2356 MOs.push_back(LoadMI->getOperand(i));
2357 }
2358 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2359 }
2360
2361
2362 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2363 const SmallVectorImpl<unsigned> &Ops) const {
2364 // Check switch flag
2365 if (NoFusing) return 0;
2366
2367 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2368 switch (MI->getOpcode()) {
2369 default: return false;
2370 case X86::TEST8rr:
2371 case X86::TEST16rr:
2372 case X86::TEST32rr:
2373 case X86::TEST64rr:
2374 return true;
2375 }
2376 }
2377
2378 if (Ops.size() != 1)
2379 return false;
2380
2381 unsigned OpNum = Ops[0];
2382 unsigned Opc = MI->getOpcode();
2383 unsigned NumOps = MI->getDesc().getNumOperands();
2384 bool isTwoAddr = NumOps > 1 &&
2385 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2386
2387 // Folding a memory location into the two-address part of a two-address
2388 // instruction is different than folding it other places. It requires
2389 // replacing the *two* registers with the memory location.
2390 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2391 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2392 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2393 } else if (OpNum == 0) { // If operand 0
2394 switch (Opc) {
2395 case X86::MOV8r0:
2396 case X86::MOV16r0:
2397 case X86::MOV32r0:
2398 return true;
2399 default: break;
2400 }
2401 OpcodeTablePtr = &RegOp2MemOpTable0;
2402 } else if (OpNum == 1) {
2403 OpcodeTablePtr = &RegOp2MemOpTable1;
2404 } else if (OpNum == 2) {
2405 OpcodeTablePtr = &RegOp2MemOpTable2;
2406 }
2407
2408 if (OpcodeTablePtr) {
2409 // Find the Opcode to fuse
2410 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2411 OpcodeTablePtr->find((unsigned*)Opc);
2412 if (I != OpcodeTablePtr->end())
2413 return true;
2414 }
2415 return false;
2416 }
2417
2418 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2419 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2420 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2421 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2422 MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2423 if (I == MemOp2RegOpTable.end())
2424 return false;
2425 DebugLoc dl = MI->getDebugLoc();
2426 unsigned Opc = I->second.first;
2427 unsigned Index = I->second.second & 0xf;
2428 bool FoldedLoad = I->second.second & (1 << 4);
2429 bool FoldedStore = I->second.second & (1 << 5);
2430 if (UnfoldLoad && !FoldedLoad)
2431 return false;
2432 UnfoldLoad &= FoldedLoad;
2433 if (UnfoldStore && !FoldedStore)
2434 return false;
2435 UnfoldStore &= FoldedStore;
2436
2437 const TargetInstrDesc &TID = get(Opc);
2438 const TargetOperandInfo &TOI = TID.OpInfo[Index];
2439 const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2440 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2441 SmallVector<MachineOperand,2> BeforeOps;
2442 SmallVector<MachineOperand,2> AfterOps;
2443 SmallVector<MachineOperand,4> ImpOps;
2444 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2445 MachineOperand &Op = MI->getOperand(i);
2446 if (i >= Index && i < Index + X86AddrNumOperands)
2447 AddrOps.push_back(Op);
2448 else if (Op.isReg() && Op.isImplicit())
2449 ImpOps.push_back(Op);
2450 else if (i < Index)
2451 BeforeOps.push_back(Op);
2452 else if (i > Index)
2453 AfterOps.push_back(Op);
2454 }
2455
2456 // Emit the load instruction.
2457 if (UnfoldLoad) {
2458 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
2459 if (UnfoldStore) {
2460 // Address operands cannot be marked isKill.
2461 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2462 MachineOperand &MO = NewMIs[0]->getOperand(i);
2463 if (MO.isReg())
2464 MO.setIsKill(false);
2465 }
2466 }
2467 }
2468
2469 // Emit the data processing instruction.
2470 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2471 MachineInstrBuilder MIB(DataMI);
2472
2473 if (FoldedStore)
2474 MIB.addReg(Reg, RegState::Define);
2475 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2476 MIB.addOperand(BeforeOps[i]);
2477 if (FoldedLoad)
2478 MIB.addReg(Reg);
2479 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2480 MIB.addOperand(AfterOps[i]);
2481 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2482 MachineOperand &MO = ImpOps[i];
2483 MIB.addReg(MO.getReg(),
2484 getDefRegState(MO.isDef()) |
2485 RegState::Implicit |
2486 getKillRegState(MO.isKill()) |
2487 getDeadRegState(MO.isDead()) |
2488 getUndefRegState(MO.isUndef()));
2489 }
2490 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2491 unsigned NewOpc = 0;
2492 switch (DataMI->getOpcode()) {
2493 default: break;
2494 case X86::CMP64ri32:
2495 case X86::CMP32ri:
2496 case X86::CMP16ri:
2497 case X86::CMP8ri: {
2498 MachineOperand &MO0 = DataMI->getOperand(0);
2499 MachineOperand &MO1 = DataMI->getOperand(1);
2500 if (MO1.getImm() == 0) {
2501 switch (DataMI->getOpcode()) {
2502 default: break;
2503 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2504 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
2505 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
2506 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
2507 }
2508 DataMI->setDesc(get(NewOpc));
2509 MO1.ChangeToRegister(MO0.getReg(), false);
2510 }
2511 }
2512 }
2513 NewMIs.push_back(DataMI);
2514
2515 // Emit the store instruction.
2516 if (UnfoldStore) {
2517 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2518 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
2519 }
2520
2521 return true;
2522 }
2523
2524 bool
2525 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2526 SmallVectorImpl<SDNode*> &NewNodes) const {
2527 if (!N->isMachineOpcode())
2528 return false;
2529
2530 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2531 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2532 if (I == MemOp2RegOpTable.end())
2533 return false;
2534 unsigned Opc = I->second.first;
2535 unsigned Index = I->second.second & 0xf;
2536 bool FoldedLoad = I->second.second & (1 << 4);
2537 bool FoldedStore = I->second.second & (1 << 5);
2538 const TargetInstrDesc &TID = get(Opc);
2539 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2540 unsigned NumDefs = TID.NumDefs;
2541 std::vector<SDValue> AddrOps;
2542 std::vector<SDValue> BeforeOps;
2543 std::vector<SDValue> AfterOps;
2544 DebugLoc dl = N->getDebugLoc();
2545 unsigned NumOps = N->getNumOperands();
2546 for (unsigned i = 0; i != NumOps-1; ++i) {
2547 SDValue Op = N->getOperand(i);
2548 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2549 AddrOps.push_back(Op);
2550 else if (i < Index-NumDefs)
2551 BeforeOps.push_back(Op);
2552 else if (i > Index-NumDefs)
2553 AfterOps.push_back(Op);
2554 }
2555 SDValue Chain = N->getOperand(NumOps-1);
2556 AddrOps.push_back(Chain);
2557
2558 // Emit the load instruction.
2559 SDNode *Load = 0;
2560 const MachineFunction &MF = DAG.getMachineFunction();
2561 if (FoldedLoad) {
2562 EVT VT = *RC->vt_begin();
2563 bool isAligned = (RI.getStackAlignment() >= 16) ||
2564 RI.needsStackRealignment(MF);
2565 Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2566 VT, MVT::Other, &AddrOps[0], AddrOps.size());
2567 NewNodes.push_back(Load);
2568 }
2569
2570 // Emit the data processing instruction.
2571 std::vector<EVT> VTs;
2572 const TargetRegisterClass *DstRC = 0;
2573 if (TID.getNumDefs() > 0) {
2574 DstRC = TID.OpInfo[0].getRegClass(&RI);
2575 VTs.push_back(*DstRC->vt_begin());
2576 }
2577 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2578 EVT VT = N->getValueType(i);
2579 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2580 VTs.push_back(VT);
2581 }
2582 if (Load)
2583 BeforeOps.push_back(SDValue(Load, 0));
2584 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2585 SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0],
2586 BeforeOps.size());
2587 NewNodes.push_back(NewNode);
2588
2589 // Emit the store instruction.
2590 if (FoldedStore) {
2591 AddrOps.pop_back();
2592 AddrOps.push_back(SDValue(NewNode, 0));
2593 AddrOps.push_back(Chain);
2594 bool isAligned = (RI.getStackAlignment() >= 16) ||
2595 RI.needsStackRealignment(MF);
2596 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
2597 isAligned, TM),
2598 dl, MVT::Other,
2599 &AddrOps[0], AddrOps.size());
2600 NewNodes.push_back(Store);
2601 }
2602
2603 return true;
2604 }
2605
2606 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2607 bool UnfoldLoad, bool UnfoldStore) const {
2608 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
2609 MemOp2RegOpTable.find((unsigned*)Opc);
2610 if (I == MemOp2RegOpTable.end())
2611 return 0;
2612 bool FoldedLoad = I->second.second & (1 << 4);
2613 bool FoldedStore = I->second.second & (1 << 5);
2614 if (UnfoldLoad && !FoldedLoad)
2615 return 0;
2616 if (UnfoldStore && !FoldedStore)
2617 return 0;
2618 return I->second.first;
2619 }
2620
2621 bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
2622 if (MBB.empty()) return false;
2623
2624 switch (MBB.back().getOpcode()) {
2625 case X86::TCRETURNri:
2626 case X86::TCRETURNdi:
2627 case X86::RET: // Return.
2628 case X86::RETI:
2629 case X86::TAILJMPd:
2630 case X86::TAILJMPr:
2631 case X86::TAILJMPm:
2632 case X86::JMP: // Uncond branch.
2633 case X86::JMP32r: // Indirect branch.
2634 case X86::JMP64r: // Indirect branch (64-bit).
2635 case X86::JMP32m: // Indirect branch through mem.
2636 case X86::JMP64m: // Indirect branch through mem (64-bit).
2637 return true;
2638 default: return false;
2639 }
2640 }
2641
2642 bool X86InstrInfo::
2643 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
2644 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
2645 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
2646 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
2647 return true;
2648 Cond[0].setImm(GetOppositeBranchCondition(CC));
2649 return false;
2650 }
2651
2652 bool X86InstrInfo::
2653 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
2654 // FIXME: Return false for x87 stack register classes for now. We can't
2655 // allow any loads of these registers before FpGet_ST0_80.
2656 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
2657 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
2658 }
2659
2660 unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) {
2661 switch (Desc->TSFlags & X86II::ImmMask) {
2662 case X86II::Imm8: return 1;
2663 case X86II::Imm16: return 2;
2664 case X86II::Imm32: return 4;
2665 case X86II::Imm64: return 8;
2666 default: llvm_unreachable("Immediate size not set!");
2667 return 0;
2668 }
2669 }
2670
2671 /// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register?
2672 /// e.g. r8, xmm8, etc.
2673 bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) {
2674 if (!MO.isReg()) return false;
2675 switch (MO.getReg()) {
2676 default: break;
2677 case X86::R8: case X86::R9: case X86::R10: case X86::R11:
2678 case X86::R12: case X86::R13: case X86::R14: case X86::R15:
2679 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D:
2680 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D:
2681 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W:
2682 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W:
2683 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B:
2684 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B:
2685 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
2686 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
2687 return true;
2688 }
2689 return false;
2690 }
2691
2692
2693 /// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
2694 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
2695 /// size, and 3) use of X86-64 extended registers.
2696 unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
2697 unsigned REX = 0;
2698 const TargetInstrDesc &Desc = MI.getDesc();
2699
2700 // Pseudo instructions do not need REX prefix byte.
2701 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
2702 return 0;
2703 if (Desc.TSFlags & X86II::REX_W)
2704 REX |= 1 << 3;
2705
2706 unsigned NumOps = Desc.getNumOperands();
2707 if (NumOps) {
2708 bool isTwoAddr = NumOps > 1 &&
2709 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
2710
2711 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
2712 unsigned i = isTwoAddr ? 1 : 0;
2713 for (unsigned e = NumOps; i != e; ++i) {
2714 const MachineOperand& MO = MI.getOperand(i);
2715 if (MO.isReg()) {
2716 unsigned Reg = MO.getReg();
2717 if (isX86_64NonExtLowByteReg(Reg))
2718 REX |= 0x40;
2719 }
2720 }
2721
2722 switch (Desc.TSFlags & X86II::FormMask) {
2723 case X86II::MRMInitReg:
2724 if (isX86_64ExtendedReg(MI.getOperand(0)))
2725 REX |= (1 << 0) | (1 << 2);
2726 break;
2727 case X86II::MRMSrcReg: {
2728 if (isX86_64ExtendedReg(MI.getOperand(0)))
2729 REX |= 1 << 2;
2730 i = isTwoAddr ? 2 : 1;
2731 for (unsigned e = NumOps; i != e; ++i) {
2732 const MachineOperand& MO = MI.getOperand(i);
2733 if (isX86_64ExtendedReg(MO))
2734 REX |= 1 << 0;
2735 }
2736 break;
2737 }
2738 case X86II::MRMSrcMem: {
2739 if (isX86_64ExtendedReg(MI.getOperand(0)))
2740 REX |= 1 << 2;
2741 unsigned Bit = 0;
2742 i = isTwoAddr ? 2 : 1;
2743 for (; i != NumOps; ++i) {
2744 const MachineOperand& MO = MI.getOperand(i);
2745 if (MO.isReg()) {
2746 if (isX86_64ExtendedReg(MO))
2747 REX |= 1 << Bit;
2748 Bit++;
2749 }
2750 }
2751 break;
2752 }
2753 case X86II::MRM0m: case X86II::MRM1m:
2754 case X86II::MRM2m: case X86II::MRM3m:
2755 case X86II::MRM4m: case X86II::MRM5m:
2756 case X86II::MRM6m: case X86II::MRM7m:
2757 case X86II::MRMDestMem: {
2758 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
2759 i = isTwoAddr ? 1 : 0;
2760 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
2761 REX |= 1 << 2;
2762 unsigned Bit = 0;
2763 for (; i != e; ++i) {
2764 const MachineOperand& MO = MI.getOperand(i);
2765 if (MO.isReg()) {
2766 if (isX86_64ExtendedReg(MO))
2767 REX |= 1 << Bit;
2768 Bit++;
2769 }
2770 }
2771 break;
2772 }
2773 default: {
2774 if (isX86_64ExtendedReg(MI.getOperand(0)))
2775 REX |= 1 << 0;
2776 i = isTwoAddr ? 2 : 1;
2777 for (unsigned e = NumOps; i != e; ++i) {
2778 const MachineOperand& MO = MI.getOperand(i);
2779 if (isX86_64ExtendedReg(MO))
2780 REX |= 1 << 2;
2781 }
2782 break;
2783 }
2784 }
2785 }
2786 return REX;
2787 }
2788
2789 /// sizePCRelativeBlockAddress - This method returns the size of a PC
2790 /// relative block address instruction
2791 ///
2792 static unsigned sizePCRelativeBlockAddress() {
2793 return 4;
2794 }
2795
2796 /// sizeGlobalAddress - Give the size of the emission of this global address
2797 ///
2798 static unsigned sizeGlobalAddress(bool dword) {
2799 return dword ? 8 : 4;
2800 }
2801
2802 /// sizeConstPoolAddress - Give the size of the emission of this constant
2803 /// pool address
2804 ///
2805 static unsigned sizeConstPoolAddress(bool dword) {
2806 return dword ? 8 : 4;
2807 }
2808
2809 /// sizeExternalSymbolAddress - Give the size of the emission of this external
2810 /// symbol
2811 ///
2812 static unsigned sizeExternalSymbolAddress(bool dword) {
2813 return dword ? 8 : 4;
2814 }
2815
2816 /// sizeJumpTableAddress - Give the size of the emission of this jump
2817 /// table address
2818 ///
2819 static unsigned sizeJumpTableAddress(bool dword) {
2820 return dword ? 8 : 4;
2821 }
2822
2823 static unsigned sizeConstant(unsigned Size) {
2824 return Size;
2825 }
2826
2827 static unsigned sizeRegModRMByte(){
2828 return 1;
2829 }
2830
2831 static unsigned sizeSIBByte(){
2832 return 1;
2833 }
2834
2835 static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
2836 unsigned FinalSize = 0;
2837 // If this is a simple integer displacement that doesn't require a relocation.
2838 if (!RelocOp) {
2839 FinalSize += sizeConstant(4);
2840 return FinalSize;
2841 }
2842
2843 // Otherwise, this is something that requires a relocation.
2844 if (RelocOp->isGlobal()) {
2845 FinalSize += sizeGlobalAddress(false);
2846 } else if (RelocOp->isCPI()) {
2847 FinalSize += sizeConstPoolAddress(false);
2848 } else if (RelocOp->isJTI()) {
2849 FinalSize += sizeJumpTableAddress(false);
2850 } else {
2851 llvm_unreachable("Unknown value to relocate!");
2852 }
2853 return FinalSize;
2854 }
2855
2856 static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
2857 bool IsPIC, bool Is64BitMode) {
2858 const MachineOperand &Op3 = MI.getOperand(Op+3);
2859 int DispVal = 0;
2860 const MachineOperand *DispForReloc = 0;
2861 unsigned FinalSize = 0;
2862
2863 // Figure out what sort of displacement we have to handle here.
2864 if (Op3.isGlobal()) {
2865 DispForReloc = &Op3;
2866 } else if (Op3.isCPI()) {
2867 if (Is64BitMode || IsPIC) {
2868 DispForReloc = &Op3;
2869 } else {
2870 DispVal = 1;
2871 }
2872 } else if (Op3.isJTI()) {
2873 if (Is64BitMode || IsPIC) {
2874 DispForReloc = &Op3;
2875 } else {
2876 DispVal = 1;
2877 }
2878 } else {
2879 DispVal = 1;
2880 }
2881
2882 const MachineOperand &Base = MI.getOperand(Op);
2883 const MachineOperand &IndexReg = MI.getOperand(Op+2);
2884
2885 unsigned BaseReg = Base.getReg();
2886
2887 // Is a SIB byte needed?
2888 if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
2889 IndexReg.getReg() == 0 &&
2890 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
2891 if (BaseReg == 0) { // Just a displacement?
2892 // Emit special case [disp32] encoding
2893 ++FinalSize;
2894 FinalSize += getDisplacementFieldSize(DispForReloc);
2895 } else {
2896 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
2897 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
2898 // Emit simple indirect register encoding... [EAX] f.e.
2899 ++FinalSize;
2900 // Be pessimistic and assume it's a disp32, not a disp8
2901 } else {
2902 // Emit the most general non-SIB encoding: [REG+disp32]
2903 ++FinalSize;
2904 FinalSize += getDisplacementFieldSize(DispForReloc);
2905 }
2906 }
2907
2908 } else { // We need a SIB byte, so start by outputting the ModR/M byte first
2909 assert(IndexReg.getReg() != X86::ESP &&
2910 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
2911
2912 bool ForceDisp32 = false;
2913 if (BaseReg == 0 || DispForReloc) {
2914 // Emit the normal disp32 encoding.
2915 ++FinalSize;
2916 ForceDisp32 = true;
2917 } else {
2918 ++FinalSize;
2919 }
2920
2921 FinalSize += sizeSIBByte();
2922
2923 // Do we need to output a displacement?
2924 if (DispVal != 0 || ForceDisp32) {
2925 FinalSize += getDisplacementFieldSize(DispForReloc);
2926 }
2927 }
2928 return FinalSize;
2929 }
2930
2931
2932 static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
2933 const TargetInstrDesc *Desc,
2934 bool IsPIC, bool Is64BitMode) {
2935
2936 unsigned Opcode = Desc->Opcode;
2937 unsigned FinalSize = 0;
2938
2939 // Emit the lock opcode prefix as needed.
2940 if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
2941
2942 // Emit segment override opcode prefix as needed.
2943 switch (Desc->TSFlags & X86II::SegOvrMask) {
2944 case X86II::FS:
2945 case X86II::GS:
2946 ++FinalSize;
2947 break;
2948 default: llvm_unreachable("Invalid segment!");
2949 case 0: break; // No segment override!
2950 }
2951
2952 // Emit the repeat opcode prefix as needed.
2953 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
2954
2955 // Emit the operand size opcode prefix as needed.
2956 if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
2957
2958 // Emit the address size opcode prefix as needed.
2959 if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
2960
2961 bool Need0FPrefix = false;
2962 switch (Desc->TSFlags & X86II::Op0Mask) {
2963 case X86II::TB: // Two-byte opcode prefix
2964 case X86II::T8: // 0F 38
2965 case X86II::TA: // 0F 3A
2966 Need0FPrefix = true;
2967 break;
2968 case X86II::TF: // F2 0F 38
2969 ++FinalSize;
2970 Need0FPrefix = true;
2971 break;
2972 case X86II::REP: break; // already handled.
2973 case X86II::XS: // F3 0F
2974 ++FinalSize;
2975 Need0FPrefix = true;
2976 break;
2977 case X86II::XD: // F2 0F
2978 ++FinalSize;
2979 Need0FPrefix = true;
2980 break;
2981 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
2982 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
2983 ++FinalSize;
2984 break; // Two-byte opcode prefix
2985 default: llvm_unreachable("Invalid prefix!");
2986 case 0: break; // No prefix!
2987 }
2988
2989 if (Is64BitMode) {
2990 // REX prefix
2991 unsigned REX = X86InstrInfo::determineREX(MI);
2992 if (REX)
2993 ++FinalSize;
2994 }
2995
2996 // 0x0F escape code must be emitted just before the opcode.
2997 if (Need0FPrefix)
2998 ++FinalSize;
2999
3000 switch (Desc->TSFlags & X86II::Op0Mask) {
3001 case X86II::T8: // 0F 38
3002 ++FinalSize;
3003 break;
3004 case X86II::TA: // 0F 3A
3005 ++FinalSize;
3006 break;
3007 case X86II::TF: // F2 0F 38
3008 ++FinalSize;
3009 break;
3010 }
3011
3012 // If this is a two-address instruction, skip one of the register operands.
3013 unsigned NumOps = Desc->getNumOperands();
3014 unsigned CurOp = 0;
3015 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3016 CurOp++;
3017 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3018 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3019 --NumOps;
3020
3021 switch (Desc->TSFlags & X86II::FormMask) {
3022 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3023 case X86II::Pseudo:
3024 // Remember the current PC offset, this is the PIC relocation
3025 // base address.
3026 switch (Opcode) {
3027 default:
3028 break;
3029 case TargetInstrInfo::INLINEASM: {
3030 const MachineFunction *MF = MI.getParent()->getParent();
3031 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3032 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3033 *MF->getTarget().getMCAsmInfo());
3034 break;
3035 }
3036 case TargetInstrInfo::DBG_LABEL:
3037 case TargetInstrInfo::EH_LABEL:
3038 break;
3039 case TargetInstrInfo::IMPLICIT_DEF:
3040 case X86::DWARF_LOC:
3041 case X86::FP_REG_KILL:
3042 break;
3043 case X86::MOVPC32r: {
3044 // This emits the "call" portion of this pseudo instruction.
3045 ++FinalSize;
3046 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3047 break;
3048 }
3049 }
3050 CurOp = NumOps;
3051 break;
3052 case X86II::RawFrm:
3053 ++FinalSize;
3054
3055 if (CurOp != NumOps) {
3056 const MachineOperand &MO = MI.getOperand(CurOp++);
3057 if (MO.isMBB()) {
3058 FinalSize += sizePCRelativeBlockAddress();
3059 } else if (MO.isGlobal()) {
3060 FinalSize += sizeGlobalAddress(false);
3061 } else if (MO.isSymbol()) {
3062 FinalSize += sizeExternalSymbolAddress(false);
3063 } else if (MO.isImm()) {
3064 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3065 } else {
3066 llvm_unreachable("Unknown RawFrm operand!");
3067 }
3068 }
3069 break;
3070
3071 case X86II::AddRegFrm:
3072 ++FinalSize;
3073 ++CurOp;
3074
3075 if (CurOp != NumOps) {
3076 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3077 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3078 if (MO1.isImm())
3079 FinalSize += sizeConstant(Size);
3080 else {
3081 bool dword = false;
3082 if (Opcode == X86::MOV64ri)
3083 dword = true;
3084 if (MO1.isGlobal()) {
3085 FinalSize += sizeGlobalAddress(dword);
3086 } else if (MO1.isSymbol())
3087 FinalSize += sizeExternalSymbolAddress(dword);
3088 else if (MO1.isCPI())
3089 FinalSize += sizeConstPoolAddress(dword);
3090 else if (MO1.isJTI())
3091 FinalSize += sizeJumpTableAddress(dword);
3092 }
3093 }
3094 break;
3095
3096 case X86II::MRMDestReg: {
3097 ++FinalSize;
3098 FinalSize += sizeRegModRMByte();
3099 CurOp += 2;
3100 if (CurOp != NumOps) {
3101 ++CurOp;
3102 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3103 }
3104 break;
3105 }
3106 case X86II::MRMDestMem: {
3107 ++FinalSize;
3108 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3109 CurOp += X86AddrNumOperands + 1;
3110 if (CurOp != NumOps) {
3111 ++CurOp;
3112 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3113 }
3114 break;
3115 }
3116
3117 case X86II::MRMSrcReg:
3118 ++FinalSize;
3119 FinalSize += sizeRegModRMByte();
3120 CurOp += 2;
3121 if (CurOp != NumOps) {
3122 ++CurOp;
3123 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3124 }
3125 break;
3126
3127 case X86II::MRMSrcMem: {
3128 int AddrOperands;
3129 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3130 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3131 AddrOperands = X86AddrNumOperands - 1; // No segment register
3132 else
3133 AddrOperands = X86AddrNumOperands;
3134
3135 ++FinalSize;
3136 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3137 CurOp += AddrOperands + 1;
3138 if (CurOp != NumOps) {
3139 ++CurOp;
3140 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
3141 }
3142 break;
3143 }
3144
3145 case X86II::MRM0r: case X86II::MRM1r:
3146 case X86II::MRM2r: case X86II::MRM3r:
3147 case X86II::MRM4r: case X86II::MRM5r:
3148 case X86II::MRM6r: case X86II::MRM7r:
3149 ++FinalSize;
3150 if (Desc->getOpcode() == X86::LFENCE ||
3151 Desc->getOpcode() == X86::MFENCE) {
3152 // Special handling of lfence and mfence;
3153 FinalSize += sizeRegModRMByte();
3154 } else if (Desc->getOpcode() == X86::MONITOR ||
3155 Desc->getOpcode() == X86::MWAIT) {
3156 // Special handling of monitor and mwait.
3157 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3158 } else {
3159 ++CurOp;
3160 FinalSize += sizeRegModRMByte();
3161 }
3162
3163 if (CurOp != NumOps) {
3164 const MachineOperand &MO1 = MI.getOperand(CurOp++);
3165 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3166 if (MO1.isImm())
3167 FinalSize += sizeConstant(Size);
3168 else {
3169 bool dword = false;
3170 if (Opcode == X86::MOV64ri32)
3171 dword = true;
3172 if (MO1.isGlobal()) {
3173 FinalSize += sizeGlobalAddress(dword);
3174 } else if (MO1.isSymbol())
3175 FinalSize += sizeExternalSymbolAddress(dword);
3176 else if (MO1.isCPI())
3177 FinalSize += sizeConstPoolAddress(dword);
3178 else if (MO1.isJTI())
3179 FinalSize += sizeJumpTableAddress(dword);
3180 }
3181 }
3182 break;
3183
3184 case X86II::MRM0m: case X86II::MRM1m:
3185 case X86II::MRM2m: case X86II::MRM3m:
3186 case X86II::MRM4m: case X86II::MRM5m:
3187 case X86II::MRM6m: case X86II::MRM7m: {
3188
3189 ++FinalSize;
3190 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3191 CurOp += X86AddrNumOperands;
3192
3193 if (CurOp != NumOps) {
3194 const MachineOperand &MO = MI.getOperand(CurOp++);
3195 unsigned Size = X86InstrInfo::sizeOfImm(Desc);
3196 if (MO.isImm())
3197 FinalSize += sizeConstant(Size);
3198 else {
3199 bool dword = false;
3200 if (Opcode == X86::MOV64mi32)
3201 dword = true;
3202 if (MO.isGlobal()) {
3203 FinalSize += sizeGlobalAddress(dword);
3204 } else if (MO.isSymbol())
3205 FinalSize += sizeExternalSymbolAddress(dword);
3206 else if (MO.isCPI())
3207 FinalSize += sizeConstPoolAddress(dword);
3208 else if (MO.isJTI())
3209 FinalSize += sizeJumpTableAddress(dword);
3210 }
3211 }
3212 break;
3213 }
3214
3215 case X86II::MRMInitReg:
3216 ++FinalSize;
3217 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3218 FinalSize += sizeRegModRMByte();
3219 ++CurOp;
3220 break;
3221 }
3222
3223 if (!Desc->isVariadic() && CurOp != NumOps) {
3224 std::string msg;
3225 raw_string_ostream Msg(msg);
3226 Msg << "Cannot determine size: " << MI;
3227 llvm_report_error(Msg.str());
3228 }
3229
3230
3231 return FinalSize;
3232 }
3233
3234
3235 unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3236 const TargetInstrDesc &Desc = MI->getDesc();
3237 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3238 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3239 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3240 if (Desc.getOpcode() == X86::MOVPC32r)
3241 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3242 return Size;
3243 }
3244
3245 /// getGlobalBaseReg - Return a virtual register initialized with the
3246 /// the global base register value. Output instructions required to
3247 /// initialize the register in the function entry block, if necessary.
3248 ///
3249 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3250 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3251 "X86-64 PIC uses RIP relative addressing");
3252
3253 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3254 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3255 if (GlobalBaseReg != 0)
3256 return GlobalBaseReg;
3257
3258 // Insert the set of GlobalBaseReg into the first MBB of the function
3259 MachineBasicBlock &FirstMBB = MF->front();
3260 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3261 DebugLoc DL = DebugLoc::getUnknownLoc();
3262 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc();
3263 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3264 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3265
3266 const TargetInstrInfo *TII = TM.getInstrInfo();
3267 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3268 // only used in JIT code emission as displacement to pc.
3269 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3270
3271 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3272 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3273 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3274 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3275 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3276 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3277 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3278 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3279 } else {
3280 GlobalBaseReg = PC;
3281 }
3282
3283 X86FI->setGlobalBaseReg(GlobalBaseReg);
3284 return GlobalBaseReg;
3285 }
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