lib/Target/X86/X86Subtarget.cpp

   1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the X86 specific subclass of TargetSubtarget.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "subtarget"
  15 #include "X86Subtarget.h"
  16 #include "X86InstrInfo.h"
  17 #include "X86GenSubtarget.inc"
  18 #include "llvm/GlobalValue.h"
  19 #include "llvm/Support/Debug.h"
  20 #include "llvm/Support/raw_ostream.h"
  21 #include "llvm/Target/TargetMachine.h"
  22 #include "llvm/Target/TargetOptions.h"
  23 using namespace llvm;
  24
  25 #if defined(_MSC_VER)
  26 #include <intrin.h>
  27 #endif
  28
  29 /// ClassifyGlobalReference - Classify a global variable reference for the
  30 /// current subtarget according to how we should reference it in a non-pcrel
  31 /// context.
  32 unsigned char X86Subtarget::
  33 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
  34   // DLLImport only exists on windows, it is implemented as a load from a
  35   // DLLIMPORT stub.
  36   if (GV->hasDLLImportLinkage())
  37     return X86II::MO_DLLIMPORT;
  38
  39   // GV with ghost linkage (in JIT lazy compilation mode) do not require an
  40   // extra load from stub.
  41   bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
  42
  43   // X86-64 in PIC mode.
  44   if (isPICStyleRIPRel()) {
  45     // Large model never uses stubs.
  46     if (TM.getCodeModel() == CodeModel::Large)
  47       return X86II::MO_NO_FLAG;
  48
  49     if (isTargetDarwin()) {
  50       // If symbol visibility is hidden, the extra load is not needed if
  51       // target is x86-64 or the symbol is definitely defined in the current
  52       // translation unit.
  53       if (GV->hasDefaultVisibility() &&
  54           (isDecl || GV->isWeakForLinker()))
  55         return X86II::MO_GOTPCREL;
  56     } else {
  57       assert(isTargetELF() && "Unknown rip-relative target");
  58
  59       // Extra load is needed for all externally visible.
  60       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
  61         return X86II::MO_GOTPCREL;
  62     }
  63
  64     return X86II::MO_NO_FLAG;
  65   }
  66
  67   if (isPICStyleGOT()) {   // 32-bit ELF targets.
  68     // Extra load is needed for all externally visible.
  69     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
  70       return X86II::MO_GOTOFF;
  71     return X86II::MO_GOT;
  72   }
  73
  74   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
  75     // Determine whether we have a stub reference and/or whether the reference
  76     // is relative to the PIC base or not.
  77
  78     // If this is a strong reference to a definition, it is definitely not
  79     // through a stub.
  80     if (!isDecl && !GV->isWeakForLinker())
  81       return X86II::MO_PIC_BASE_OFFSET;
  82
  83     // Unless we have a symbol with hidden visibility, we have to go through a
  84     // normal $non_lazy_ptr stub because this symbol might be resolved late.
  85     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
  86       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
  87
  88     // If symbol visibility is hidden, we have a stub for common symbol
  89     // references and external declarations.
  90     if (isDecl || GV->hasCommonLinkage()) {
  91       // Hidden $non_lazy_ptr reference.
  92       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
  93     }
  94
  95     // Otherwise, no stub.
  96     return X86II::MO_PIC_BASE_OFFSET;
  97   }
  98
  99   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
 100     // Determine whether we have a stub reference.
 101
 102     // If this is a strong reference to a definition, it is definitely not
 103     // through a stub.
 104     if (!isDecl && !GV->isWeakForLinker())
 105       return X86II::MO_NO_FLAG;
 106
 107     // Unless we have a symbol with hidden visibility, we have to go through a
 108     // normal $non_lazy_ptr stub because this symbol might be resolved late.
 109     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
 110       return X86II::MO_DARWIN_NONLAZY;
 111
 112     // Otherwise, no stub.
 113     return X86II::MO_NO_FLAG;
 114   }
 115
 116   // Direct static reference to global.
 117   return X86II::MO_NO_FLAG;
 118 }
 119
 120
 121 /// getBZeroEntry - This function returns the name of a function which has an
 122 /// interface like the non-standard bzero function, if such a function exists on
 123 /// the current subtarget and it is considered prefereable over memset with zero
 124 /// passed as the second argument. Otherwise it returns null.
 125 const char *X86Subtarget::getBZeroEntry() const {
 126   // Darwin 10 has a __bzero entry point for this purpose.
 127   if (getDarwinVers() >= 10)
 128     return "__bzero";
 129
 130   return 0;
 131 }
 132
 133 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
 134 /// to immediate address.
 135 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
 136   if (Is64Bit)
 137     return false;
 138   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
 139 }
 140
 141 /// getSpecialAddressLatency - For targets where it is beneficial to
 142 /// backschedule instructions that compute addresses, return a value
 143 /// indicating the number of scheduling cycles of backscheduling that
 144 /// should be attempted.
 145 unsigned X86Subtarget::getSpecialAddressLatency() const {
 146   // For x86 out-of-order targets, back-schedule address computations so
 147   // that loads and stores aren't blocked.
 148   // This value was chosen arbitrarily.
 149   return 200;
 150 }
 151
 152 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
 153 /// specified arguments.  If we can't run cpuid on the host, return true.
 154 static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
 155                             unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
 156 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
 157   #if defined(__GNUC__)
 158     // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
 159     asm ("movq\t%%rbx, %%rsi\n\t"
 160          "cpuid\n\t"
 161          "xchgq\t%%rbx, %%rsi\n\t"
 162          : "=a" (*rEAX),
 163            "=S" (*rEBX),
 164            "=c" (*rECX),
 165            "=d" (*rEDX)
 166          :  "a" (value));
 167     return false;
 168   #elif defined(_MSC_VER)
 169     int registers[4];
 170     __cpuid(registers, value);
 171     *rEAX = registers[0];
 172     *rEBX = registers[1];
 173     *rECX = registers[2];
 174     *rEDX = registers[3];
 175     return false;
 176   #endif
 177 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
 178   #if defined(__GNUC__)
 179     asm ("movl\t%%ebx, %%esi\n\t"
 180          "cpuid\n\t"
 181          "xchgl\t%%ebx, %%esi\n\t"
 182          : "=a" (*rEAX),
 183            "=S" (*rEBX),
 184            "=c" (*rECX),
 185            "=d" (*rEDX)
 186          :  "a" (value));
 187     return false;
 188   #elif defined(_MSC_VER)
 189     __asm {
 190       mov   eax,value
 191       cpuid
 192       mov   esi,rEAX
 193       mov   dword ptr [esi],eax
 194       mov   esi,rEBX
 195       mov   dword ptr [esi],ebx
 196       mov   esi,rECX
 197       mov   dword ptr [esi],ecx
 198       mov   esi,rEDX
 199       mov   dword ptr [esi],edx
 200     }
 201     return false;
 202   #endif
 203 #endif
 204   return true;
 205 }
 206
 207 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
 208   Family = (EAX >> 8) & 0xf; // Bits 8 - 11
 209   Model  = (EAX >> 4) & 0xf; // Bits 4 - 7
 210   if (Family == 6 || Family == 0xf) {
 211     if (Family == 0xf)
 212       // Examine extended family ID if family ID is F.
 213       Family += (EAX >> 20) & 0xff;    // Bits 20 - 27
 214     // Examine extended model ID if family ID is 6 or F.
 215     Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
 216   }
 217 }
 218
 219 void X86Subtarget::AutoDetectSubtargetFeatures() {
 220   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 221   union {
 222     unsigned u[3];
 223     char     c[12];
 224   } text;
 225
 226   if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
 227     return;
 228
 229   GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
 230
 231   if ((EDX >> 15) & 1) HasCMov = true;
 232   if ((EDX >> 23) & 1) X86SSELevel = MMX;
 233   if ((EDX >> 25) & 1) X86SSELevel = SSE1;
 234   if ((EDX >> 26) & 1) X86SSELevel = SSE2;
 235   if (ECX & 0x1)       X86SSELevel = SSE3;
 236   if ((ECX >> 9)  & 1) X86SSELevel = SSSE3;
 237   if ((ECX >> 19) & 1) X86SSELevel = SSE41;
 238   if ((ECX >> 20) & 1) X86SSELevel = SSE42;
 239
 240   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
 241   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
 242
 243   HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
 244   HasAVX = ((ECX >> 28) & 0x1);
 245
 246   if (IsIntel || IsAMD) {
 247     // Determine if bit test memory instructions are slow.
 248     unsigned Family = 0;
 249     unsigned Model  = 0;
 250     DetectFamilyModel(EAX, Family, Model);
 251     IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
 252
 253     GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 254     HasX86_64 = (EDX >> 29) & 0x1;
 255     HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
 256     HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
 257   }
 258 }
 259
 260 static const char *GetCurrentX86CPU() {
 261   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
 262   if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
 263     return "generic";
 264   unsigned Family = 0;
 265   unsigned Model  = 0;
 266   DetectFamilyModel(EAX, Family, Model);
 267
 268   GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
 269   bool Em64T = (EDX >> 29) & 0x1;
 270   bool HasSSE3 = (ECX & 0x1);
 271
 272   union {
 273     unsigned u[3];
 274     char     c[12];
 275   } text;
 276
 277   GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
 278   if (memcmp(text.c, "GenuineIntel", 12) == 0) {
 279     switch (Family) {
 280       case 3:
 281         return "i386";
 282       case 4:
 283         return "i486";
 284       case 5:
 285         switch (Model) {
 286         case 4:  return "pentium-mmx";
 287         default: return "pentium";
 288         }
 289       case 6:
 290         switch (Model) {
 291         case 1:  return "pentiumpro";
 292         case 3:
 293         case 5:
 294         case 6:  return "pentium2";
 295         case 7:
 296         case 8:
 297         case 10:
 298         case 11: return "pentium3";
 299         case 9:
 300         case 13: return "pentium-m";
 301         case 14: return "yonah";
 302         case 15:
 303         case 22: // Celeron M 540
 304           return "core2";
 305         case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
 306           return "penryn";
 307         default: return "i686";
 308         }
 309       case 15: {
 310         switch (Model) {
 311         case 3:
 312         case 4:
 313         case 6: // same as 4, but 65nm
 314           return (Em64T) ? "nocona" : "prescott";
 315         case 26:
 316           return "corei7";
 317         case 28:
 318           return "atom";
 319         default:
 320           return (Em64T) ? "x86-64" : "pentium4";
 321         }
 322       }
 323
 324     default:
 325       return "generic";
 326     }
 327   } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
 328     // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
 329     // appears to be no way to generate the wide variety of AMD-specific targets
 330     // from the information returned from CPUID.
 331     switch (Family) {
 332       case 4:
 333         return "i486";
 334       case 5:
 335         switch (Model) {
 336         case 6:
 337         case 7:  return "k6";
 338         case 8:  return "k6-2";
 339         case 9:
 340         case 13: return "k6-3";
 341         default: return "pentium";
 342         }
 343       case 6:
 344         switch (Model) {
 345         case 4:  return "athlon-tbird";
 346         case 6:
 347         case 7:
 348         case 8:  return "athlon-mp";
 349         case 10: return "athlon-xp";
 350         default: return "athlon";
 351         }
 352       case 15:
 353         if (HasSSE3) {
 354           return "k8-sse3";
 355         } else {
 356           switch (Model) {
 357           case 1:  return "opteron";
 358           case 5:  return "athlon-fx"; // also opteron
 359           default: return "athlon64";
 360           }
 361         }
 362       case 16:
 363         return "amdfam10";
 364     default:
 365       return "generic";
 366     }
 367   } else {
 368     return "generic";
 369   }
 370 }
 371
 372 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
 373                            bool is64Bit)
 374   : PICStyle(PICStyles::None)
 375   , X86SSELevel(NoMMXSSE)
 376   , X863DNowLevel(NoThreeDNow)
 377   , HasCMov(false)
 378   , HasX86_64(false)
 379   , HasSSE4A(false)
 380   , HasAVX(false)
 381   , HasFMA3(false)
 382   , HasFMA4(false)
 383   , IsBTMemSlow(false)
 384   , DarwinVers(0)
 385   , IsLinux(false)
 386   , stackAlignment(8)
 387   // FIXME: this is a known good value for Yonah. How about others?
 388   , MaxInlineSizeThreshold(128)
 389   , Is64Bit(is64Bit)
 390   , TargetType(isELF) { // Default to ELF unless otherwise specified.
 391
 392   // default to hard float ABI
 393   if (FloatABIType == FloatABI::Default)
 394     FloatABIType = FloatABI::Hard;
 395
 396   // Determine default and user specified characteristics
 397   if (!FS.empty()) {
 398     // If feature string is not empty, parse features string.
 399     std::string CPU = GetCurrentX86CPU();
 400     ParseSubtargetFeatures(FS, CPU);
 401     // All X86-64 CPUs also have SSE2, however user might request no SSE via
 402     // -mattr, so don't force SSELevel here.
 403   } else {
 404     // Otherwise, use CPUID to auto-detect feature set.
 405     AutoDetectSubtargetFeatures();
 406     // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
 407     if (Is64Bit && X86SSELevel < SSE2)
 408       X86SSELevel = SSE2;
 409   }
 410
 411   // If requesting codegen for X86-64, make sure that 64-bit features
 412   // are enabled.
 413   if (Is64Bit)
 414     HasX86_64 = true;
 415
 416   DEBUG(errs() << "Subtarget features: SSELevel " << X86SSELevel
 417                << ", 3DNowLevel " << X863DNowLevel
 418                << ", 64bit " << HasX86_64 << "\n");
 419   assert((!Is64Bit || HasX86_64) &&
 420          "64-bit code requested on a subtarget that doesn't support it!");
 421
 422   // Set the boolean corresponding to the current target triple, or the default
 423   // if one cannot be determined, to true.
 424   if (TT.length() > 5) {
 425     size_t Pos;
 426     if ((Pos = TT.find("-darwin")) != std::string::npos) {
 427       TargetType = isDarwin;
 428
 429       // Compute the darwin version number.
 430       if (isdigit(TT[Pos+7]))
 431         DarwinVers = atoi(&TT[Pos+7]);
 432       else
 433         DarwinVers = 8;  // Minimum supported darwin is Tiger.
 434     } else if (TT.find("linux") != std::string::npos) {
 435       // Linux doesn't imply ELF, but we don't currently support anything else.
 436       TargetType = isELF;
 437       IsLinux = true;
 438     } else if (TT.find("cygwin") != std::string::npos) {
 439       TargetType = isCygwin;
 440     } else if (TT.find("mingw") != std::string::npos) {
 441       TargetType = isMingw;
 442     } else if (TT.find("win32") != std::string::npos) {
 443       TargetType = isWindows;
 444     } else if (TT.find("windows") != std::string::npos) {
 445       TargetType = isWindows;
 446     } else if (TT.find("-cl") != std::string::npos) {
 447       TargetType = isDarwin;
 448       DarwinVers = 9;
 449     }
 450   }
 451
 452   // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
 453   // bit targets.
 454   if (TargetType == isDarwin || Is64Bit)
 455     stackAlignment = 16;
 456
 457   if (StackAlignment)
 458     stackAlignment = StackAlignment;
 459 }