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1 //====- X86Instr64bit.td - Describe X86-64 Instructions ----*- tablegen -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
13 //
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions.
18 //
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
23 // 64-bits but only 32 bits are significant, and those bits are treated as being
24 // pc relative.
25 def i64i32imm_pcrel : Operand<i64> {
26 let PrintMethod = "print_pcrel_imm";
27 }
30 // 64-bits but only 8 bits are significant.
31 def i64i8imm : Operand<i64> {
32 let ParserMatchClass = ImmSExt8AsmOperand;
33 }
35 def lea64mem : Operand<i64> {
36 let PrintMethod = "printlea64mem";
37 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
38 let ParserMatchClass = X86MemAsmOperand;
39 }
41 def lea64_32mem : Operand<i32> {
42 let PrintMethod = "printlea64_32mem";
43 let AsmOperandLowerMethod = "lower_lea64_32mem";
44 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
45 let ParserMatchClass = X86MemAsmOperand;
46 }
48 //===----------------------------------------------------------------------===//
49 // Complex Pattern Definitions.
50 //
51 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
52 [add, sub, mul, X86mul_imm, shl, or, frameindex,
53 X86WrapperRIP], []>;
55 def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
56 [tglobaltlsaddr], []>;
58 //===----------------------------------------------------------------------===//
59 // Pattern fragments.
60 //
62 def i64immSExt8 : PatLeaf<(i64 imm), [{
63 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
64 // sign extended field.
65 return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
66 }]>;
68 def i64immSExt32 : PatLeaf<(i64 imm), [{
69 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
70 // sign extended field.
71 return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
72 }]>;
74 def i64immZExt32 : PatLeaf<(i64 imm), [{
75 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
76 // unsignedsign extended field.
77 return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
78 }]>;
80 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
81 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
82 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
84 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
85 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
86 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
87 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
89 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
90 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
91 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
92 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
94 //===----------------------------------------------------------------------===//
95 // Instruction list...
96 //
98 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
99 // a stack adjustment and the codegen must know that they may modify the stack
100 // pointer before prolog-epilog rewriting occurs.
101 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
102 // sub / add which can clobber EFLAGS.
103 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
104 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
105 "#ADJCALLSTACKDOWN",
106 [(X86callseq_start timm:$amt)]>,
107 Requires<[In64BitMode]>;
108 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
109 "#ADJCALLSTACKUP",
110 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
111 Requires<[In64BitMode]>;
112 }
114 //===----------------------------------------------------------------------===//
115 // Call Instructions...
116 //
117 let isCall = 1 in
118 // All calls clobber the non-callee saved registers. RSP is marked as
119 // a use to prevent stack-pointer assignments that appear immediately
120 // before calls from potentially appearing dead. Uses for argument
121 // registers are added manually.
122 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
123 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
124 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
125 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
126 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
127 Uses = [RSP] in {
129 // NOTE: this pattern doesn't match "X86call imm", because we do not know
130 // that the offset between an arbitrary immediate and the call will fit in
131 // the 32-bit pcrel field that we have.
132 def CALL64pcrel32 : Ii32<0xE8, RawFrm,
133 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
134 "call\t$dst", []>,
135 Requires<[In64BitMode, NotWin64]>;
136 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
137 "call\t{*}$dst", [(X86call GR64:$dst)]>,
138 Requires<[NotWin64]>;
139 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
140 "call\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
141 Requires<[NotWin64]>;
143 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst),
144 "lcall{q}\t{*}$dst", []>;
145 }
147 // FIXME: We need to teach codegen about single list of call-clobbered registers.
148 let isCall = 1 in
149 // All calls clobber the non-callee saved registers. RSP is marked as
150 // a use to prevent stack-pointer assignments that appear immediately
151 // before calls from potentially appearing dead. Uses for argument
152 // registers are added manually.
153 let Defs = [RAX, RCX, RDX, R8, R9, R10, R11,
154 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
155 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
156 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
157 Uses = [RSP] in {
158 def WINCALL64pcrel32 : I<0xE8, RawFrm,
159 (outs), (ins i64i32imm_pcrel:$dst, variable_ops),
160 "call\t$dst", []>,
161 Requires<[IsWin64]>;
162 def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
163 "call\t{*}$dst",
164 [(X86call GR64:$dst)]>, Requires<[IsWin64]>;
165 def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
166 "call\t{*}$dst",
167 [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>;
168 }
171 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
172 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset,
173 variable_ops),
174 "#TC_RETURN $dst $offset",
175 []>;
177 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
178 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset,
179 variable_ops),
180 "#TC_RETURN $dst $offset",
181 []>;
184 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
185 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
186 "jmp{q}\t{*}$dst # TAILCALL",
187 []>;
189 // Branches
190 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
191 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
192 [(brind GR64:$dst)]>;
193 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
194 [(brind (loadi64 addr:$dst))]>;
195 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
196 "ljmp{q}\t{*}$dst", []>;
197 }
199 //===----------------------------------------------------------------------===//
200 // EH Pseudo Instructions
201 //
202 let isTerminator = 1, isReturn = 1, isBarrier = 1,
203 hasCtrlDep = 1 in {
204 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
205 "ret\t#eh_return, addr: $addr",
206 [(X86ehret GR64:$addr)]>;
208 }
210 //===----------------------------------------------------------------------===//
211 // Miscellaneous Instructions...
212 //
213 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
214 def LEAVE64 : I<0xC9, RawFrm,
215 (outs), (ins), "leave", []>;
216 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
217 let mayLoad = 1 in {
218 def POP64r : I<0x58, AddRegFrm,
219 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
220 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
221 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>;
222 }
223 let mayStore = 1 in {
224 def PUSH64r : I<0x50, AddRegFrm,
225 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
226 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
227 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>;
228 }
229 }
231 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in {
232 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
233 "push{q}\t$imm", []>;
234 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
235 "push{q}\t$imm", []>;
236 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
237 "push{q}\t$imm", []>;
238 }
240 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1 in
241 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
242 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1 in
243 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
245 def LEA64_32r : I<0x8D, MRMSrcMem,
246 (outs GR32:$dst), (ins lea64_32mem:$src),
247 "lea{l}\t{$src|$dst}, {$dst|$src}",
248 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
250 let isReMaterializable = 1 in
251 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
252 "lea{q}\t{$src|$dst}, {$dst|$src}",
253 [(set GR64:$dst, lea64addr:$src)]>;
255 let isTwoAddress = 1 in
256 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
257 "bswap{q}\t$dst",
258 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
260 // Bit scan instructions.
261 let Defs = [EFLAGS] in {
262 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
263 "bsf{q}\t{$src, $dst|$dst, $src}",
264 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
265 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
266 "bsf{q}\t{$src, $dst|$dst, $src}",
267 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
268 (implicit EFLAGS)]>, TB;
270 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
271 "bsr{q}\t{$src, $dst|$dst, $src}",
272 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
273 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
274 "bsr{q}\t{$src, $dst|$dst, $src}",
275 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
276 (implicit EFLAGS)]>, TB;
277 } // Defs = [EFLAGS]
279 // Repeat string ops
280 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
281 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
282 [(X86rep_movs i64)]>, REP;
283 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
284 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
285 [(X86rep_stos i64)]>, REP;
287 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scas{q}", []>;
289 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmps{q}", []>;
291 // Fast system-call instructions
292 def SYSEXIT64 : RI<0x35, RawFrm,
293 (outs), (ins), "sysexit", []>, TB;
295 //===----------------------------------------------------------------------===//
296 // Move Instructions...
297 //
299 let neverHasSideEffects = 1 in
300 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
301 "mov{q}\t{$src, $dst|$dst, $src}", []>;
303 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
304 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
305 "movabs{q}\t{$src, $dst|$dst, $src}",
306 [(set GR64:$dst, imm:$src)]>;
307 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
308 "mov{q}\t{$src, $dst|$dst, $src}",
309 [(set GR64:$dst, i64immSExt32:$src)]>;
310 }
312 let canFoldAsLoad = 1 in
313 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
314 "mov{q}\t{$src, $dst|$dst, $src}",
315 [(set GR64:$dst, (load addr:$src))]>;
317 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
318 "mov{q}\t{$src, $dst|$dst, $src}",
319 [(store GR64:$src, addr:$dst)]>;
320 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
321 "mov{q}\t{$src, $dst|$dst, $src}",
322 [(store i64immSExt32:$src, addr:$dst)]>;
324 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins i8imm:$src),
325 "mov{q}\t{$src, %rax|%rax, $src}", []>;
326 def MOV64o32a : RIi32<0xA1, RawFrm, (outs), (ins i32imm:$src),
327 "mov{q}\t{$src, %rax|%rax, $src}", []>;
328 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs i8imm:$dst), (ins),
329 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
330 def MOV64ao32 : RIi32<0xA3, RawFrm, (outs i32imm:$dst), (ins),
331 "mov{q}\t{%rax, $dst|$dst, %rax}", []>;
333 // Sign/Zero extenders
335 // MOVSX64rr8 always has a REX prefix and it has an 8-bit register
336 // operand, which makes it a rare instruction with an 8-bit register
337 // operand that can never access an h register. If support for h registers
338 // were generalized, this would require a special register class.
339 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
340 "movs{bq|x}\t{$src, $dst|$dst, $src}",
341 [(set GR64:$dst, (sext GR8:$src))]>, TB;
342 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
343 "movs{bq|x}\t{$src, $dst|$dst, $src}",
344 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
345 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
346 "movs{wq|x}\t{$src, $dst|$dst, $src}",
347 [(set GR64:$dst, (sext GR16:$src))]>, TB;
348 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
349 "movs{wq|x}\t{$src, $dst|$dst, $src}",
350 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
351 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
352 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
353 [(set GR64:$dst, (sext GR32:$src))]>;
354 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
355 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
356 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
358 // Use movzbl instead of movzbq when the destination is a register; it's
359 // equivalent due to implicit zero-extending, and it has a smaller encoding.
360 def MOVZX64rr8 : I<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
361 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
362 [(set GR64:$dst, (zext GR8:$src))]>, TB;
363 def MOVZX64rm8 : I<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
364 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
365 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
366 // Use movzwl instead of movzwq when the destination is a register; it's
367 // equivalent due to implicit zero-extending, and it has a smaller encoding.
368 def MOVZX64rr16: I<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
369 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
370 [(set GR64:$dst, (zext GR16:$src))]>, TB;
371 def MOVZX64rm16: I<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
372 "movz{wl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
373 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
375 // There's no movzlq instruction, but movl can be used for this purpose, using
376 // implicit zero-extension. The preferred way to do 32-bit-to-64-bit zero
377 // extension on x86-64 is to use a SUBREG_TO_REG to utilize implicit
378 // zero-extension, however this isn't possible when the 32-bit value is
379 // defined by a truncate or is copied from something where the high bits aren't
380 // necessarily all zero. In such cases, we fall back to these explicit zext
381 // instructions.
382 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
383 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
384 [(set GR64:$dst, (zext GR32:$src))]>;
385 def MOVZX64rm32 : I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
386 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
387 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
389 // Any instruction that defines a 32-bit result leaves the high half of the
390 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
391 // be copying from a truncate, but any other 32-bit operation will zero-extend
392 // up to 64 bits.
393 def def32 : PatLeaf<(i32 GR32:$src), [{
394 return N->getOpcode() != ISD::TRUNCATE &&
395 N->getOpcode() != TargetInstrInfo::EXTRACT_SUBREG &&
396 N->getOpcode() != ISD::CopyFromReg;
397 }]>;
399 // In the case of a 32-bit def that is known to implicitly zero-extend,
400 // we can use a SUBREG_TO_REG.
401 def : Pat<(i64 (zext def32:$src)),
402 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
404 let neverHasSideEffects = 1 in {
405 let Defs = [RAX], Uses = [EAX] in
406 def CDQE : RI<0x98, RawFrm, (outs), (ins),
407 "{cltq|cdqe}", []>; // RAX = signext(EAX)
409 let Defs = [RAX,RDX], Uses = [RAX] in
410 def CQO : RI<0x99, RawFrm, (outs), (ins),
411 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
412 }
414 //===----------------------------------------------------------------------===//
415 // Arithmetic Instructions...
416 //
418 let Defs = [EFLAGS] in {
420 def ADD64i32 : RI<0x05, RawFrm, (outs), (ins i32imm:$src),
421 "add{q}\t{$src, %rax|%rax, $src}", []>;
423 let isTwoAddress = 1 in {
424 let isConvertibleToThreeAddress = 1 in {
425 let isCommutable = 1 in
426 // Register-Register Addition
427 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
428 "add{q}\t{$src2, $dst|$dst, $src2}",
429 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
430 (implicit EFLAGS)]>;
432 // Register-Integer Addition
433 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
434 "add{q}\t{$src2, $dst|$dst, $src2}",
435 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2)),
436 (implicit EFLAGS)]>;
437 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
438 "add{q}\t{$src2, $dst|$dst, $src2}",
439 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2)),
440 (implicit EFLAGS)]>;
441 } // isConvertibleToThreeAddress
443 // Register-Memory Addition
444 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
445 "add{q}\t{$src2, $dst|$dst, $src2}",
446 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
447 (implicit EFLAGS)]>;
448 } // isTwoAddress
450 // Memory-Register Addition
451 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
452 "add{q}\t{$src2, $dst|$dst, $src2}",
453 [(store (add (load addr:$dst), GR64:$src2), addr:$dst),
454 (implicit EFLAGS)]>;
455 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
456 "add{q}\t{$src2, $dst|$dst, $src2}",
457 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst),
458 (implicit EFLAGS)]>;
459 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
460 "add{q}\t{$src2, $dst|$dst, $src2}",
461 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst),
462 (implicit EFLAGS)]>;
464 let Uses = [EFLAGS] in {
466 def ADC64i32 : RI<0x15, RawFrm, (outs), (ins i32imm:$src),
467 "adc{q}\t{$src, %rax|%rax, $src}", []>;
469 let isTwoAddress = 1 in {
470 let isCommutable = 1 in
471 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
472 "adc{q}\t{$src2, $dst|$dst, $src2}",
473 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
475 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
476 "adc{q}\t{$src2, $dst|$dst, $src2}",
477 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
479 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
480 "adc{q}\t{$src2, $dst|$dst, $src2}",
481 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
482 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
483 "adc{q}\t{$src2, $dst|$dst, $src2}",
484 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
485 } // isTwoAddress
487 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
488 "adc{q}\t{$src2, $dst|$dst, $src2}",
489 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
490 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
491 "adc{q}\t{$src2, $dst|$dst, $src2}",
492 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
493 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
494 "adc{q}\t{$src2, $dst|$dst, $src2}",
495 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
496 } // Uses = [EFLAGS]
498 let isTwoAddress = 1 in {
499 // Register-Register Subtraction
500 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
501 "sub{q}\t{$src2, $dst|$dst, $src2}",
502 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2)),
503 (implicit EFLAGS)]>;
505 // Register-Memory Subtraction
506 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
507 "sub{q}\t{$src2, $dst|$dst, $src2}",
508 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2))),
509 (implicit EFLAGS)]>;
511 // Register-Integer Subtraction
512 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst),
513 (ins GR64:$src1, i64i8imm:$src2),
514 "sub{q}\t{$src2, $dst|$dst, $src2}",
515 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2)),
516 (implicit EFLAGS)]>;
517 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst),
518 (ins GR64:$src1, i64i32imm:$src2),
519 "sub{q}\t{$src2, $dst|$dst, $src2}",
520 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2)),
521 (implicit EFLAGS)]>;
522 } // isTwoAddress
524 def SUB64i32 : RI<0x2D, RawFrm, (outs), (ins i32imm:$src),
525 "sub{q}\t{$src, %rax|%rax, $src}", []>;
527 // Memory-Register Subtraction
528 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
529 "sub{q}\t{$src2, $dst|$dst, $src2}",
530 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst),
531 (implicit EFLAGS)]>;
533 // Memory-Integer Subtraction
534 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
535 "sub{q}\t{$src2, $dst|$dst, $src2}",
536 [(store (sub (load addr:$dst), i64immSExt8:$src2),
537 addr:$dst),
538 (implicit EFLAGS)]>;
539 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
540 "sub{q}\t{$src2, $dst|$dst, $src2}",
541 [(store (sub (load addr:$dst), i64immSExt32:$src2),
542 addr:$dst),
543 (implicit EFLAGS)]>;
545 let Uses = [EFLAGS] in {
546 let isTwoAddress = 1 in {
547 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
548 "sbb{q}\t{$src2, $dst|$dst, $src2}",
549 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
551 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
552 "sbb{q}\t{$src2, $dst|$dst, $src2}",
553 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
555 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
556 "sbb{q}\t{$src2, $dst|$dst, $src2}",
557 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
558 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
559 "sbb{q}\t{$src2, $dst|$dst, $src2}",
560 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
561 } // isTwoAddress
563 def SBB64i32 : RI<0x1D, RawFrm, (outs), (ins i32imm:$src),
564 "sbb{q}\t{$src, %rax|%rax, $src}", []>;
566 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
567 "sbb{q}\t{$src2, $dst|$dst, $src2}",
568 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
569 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
570 "sbb{q}\t{$src2, $dst|$dst, $src2}",
571 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
572 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
573 "sbb{q}\t{$src2, $dst|$dst, $src2}",
574 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
575 } // Uses = [EFLAGS]
576 } // Defs = [EFLAGS]
578 // Unsigned multiplication
579 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in {
580 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
581 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
582 let mayLoad = 1 in
583 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
584 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
586 // Signed multiplication
587 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
588 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
589 let mayLoad = 1 in
590 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
591 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
592 }
594 let Defs = [EFLAGS] in {
595 let isTwoAddress = 1 in {
596 let isCommutable = 1 in
597 // Register-Register Signed Integer Multiplication
598 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
599 (ins GR64:$src1, GR64:$src2),
600 "imul{q}\t{$src2, $dst|$dst, $src2}",
601 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2)),
602 (implicit EFLAGS)]>, TB;
604 // Register-Memory Signed Integer Multiplication
605 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
606 (ins GR64:$src1, i64mem:$src2),
607 "imul{q}\t{$src2, $dst|$dst, $src2}",
608 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2))),
609 (implicit EFLAGS)]>, TB;
610 } // isTwoAddress
612 // Suprisingly enough, these are not two address instructions!
614 // Register-Integer Signed Integer Multiplication
615 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
616 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
617 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
618 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2)),
619 (implicit EFLAGS)]>;
620 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
621 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
622 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
623 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2)),
624 (implicit EFLAGS)]>;
626 // Memory-Integer Signed Integer Multiplication
627 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
628 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
629 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
630 [(set GR64:$dst, (mul (load addr:$src1),
631 i64immSExt8:$src2)),
632 (implicit EFLAGS)]>;
633 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
634 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
635 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
636 [(set GR64:$dst, (mul (load addr:$src1),
637 i64immSExt32:$src2)),
638 (implicit EFLAGS)]>;
639 } // Defs = [EFLAGS]
641 // Unsigned division / remainder
642 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
643 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
644 "div{q}\t$src", []>;
645 // Signed division / remainder
646 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
647 "idiv{q}\t$src", []>;
648 let mayLoad = 1 in {
649 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
650 "div{q}\t$src", []>;
651 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
652 "idiv{q}\t$src", []>;
653 }
654 }
656 // Unary instructions
657 let Defs = [EFLAGS], CodeSize = 2 in {
658 let isTwoAddress = 1 in
659 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
660 [(set GR64:$dst, (ineg GR64:$src)),
661 (implicit EFLAGS)]>;
662 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
663 [(store (ineg (loadi64 addr:$dst)), addr:$dst),
664 (implicit EFLAGS)]>;
666 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
667 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
668 [(set GR64:$dst, (add GR64:$src, 1)),
669 (implicit EFLAGS)]>;
670 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
671 [(store (add (loadi64 addr:$dst), 1), addr:$dst),
672 (implicit EFLAGS)]>;
674 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
675 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
676 [(set GR64:$dst, (add GR64:$src, -1)),
677 (implicit EFLAGS)]>;
678 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
679 [(store (add (loadi64 addr:$dst), -1), addr:$dst),
680 (implicit EFLAGS)]>;
682 // In 64-bit mode, single byte INC and DEC cannot be encoded.
683 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
684 // Can transform into LEA.
685 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
686 [(set GR16:$dst, (add GR16:$src, 1)),
687 (implicit EFLAGS)]>,
688 OpSize, Requires<[In64BitMode]>;
689 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
690 [(set GR32:$dst, (add GR32:$src, 1)),
691 (implicit EFLAGS)]>,
692 Requires<[In64BitMode]>;
693 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
694 [(set GR16:$dst, (add GR16:$src, -1)),
695 (implicit EFLAGS)]>,
696 OpSize, Requires<[In64BitMode]>;
697 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
698 [(set GR32:$dst, (add GR32:$src, -1)),
699 (implicit EFLAGS)]>,
700 Requires<[In64BitMode]>;
701 } // isConvertibleToThreeAddress
703 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
704 // how to unfold them.
705 let isTwoAddress = 0, CodeSize = 2 in {
706 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
707 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
708 (implicit EFLAGS)]>,
709 OpSize, Requires<[In64BitMode]>;
710 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
711 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
712 (implicit EFLAGS)]>,
713 Requires<[In64BitMode]>;
714 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
715 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
716 (implicit EFLAGS)]>,
717 OpSize, Requires<[In64BitMode]>;
718 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
719 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
720 (implicit EFLAGS)]>,
721 Requires<[In64BitMode]>;
722 }
723 } // Defs = [EFLAGS], CodeSize
726 let Defs = [EFLAGS] in {
727 // Shift instructions
728 let isTwoAddress = 1 in {
729 let Uses = [CL] in
730 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
731 "shl{q}\t{%cl, $dst|$dst, %CL}",
732 [(set GR64:$dst, (shl GR64:$src, CL))]>;
733 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
734 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
735 "shl{q}\t{$src2, $dst|$dst, $src2}",
736 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
737 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
738 // cheaper.
739 } // isTwoAddress
741 let Uses = [CL] in
742 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
743 "shl{q}\t{%cl, $dst|$dst, %CL}",
744 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
745 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
746 "shl{q}\t{$src, $dst|$dst, $src}",
747 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
748 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
749 "shl{q}\t$dst",
750 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
752 let isTwoAddress = 1 in {
753 let Uses = [CL] in
754 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
755 "shr{q}\t{%cl, $dst|$dst, %CL}",
756 [(set GR64:$dst, (srl GR64:$src, CL))]>;
757 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
758 "shr{q}\t{$src2, $dst|$dst, $src2}",
759 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
760 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
761 "shr{q}\t$dst",
762 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
763 } // isTwoAddress
765 let Uses = [CL] in
766 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
767 "shr{q}\t{%cl, $dst|$dst, %CL}",
768 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
769 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
770 "shr{q}\t{$src, $dst|$dst, $src}",
771 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
772 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
773 "shr{q}\t$dst",
774 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
776 let isTwoAddress = 1 in {
777 let Uses = [CL] in
778 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
779 "sar{q}\t{%cl, $dst|$dst, %CL}",
780 [(set GR64:$dst, (sra GR64:$src, CL))]>;
781 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
782 "sar{q}\t{$src2, $dst|$dst, $src2}",
783 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
784 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
785 "sar{q}\t$dst",
786 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
787 } // isTwoAddress
789 let Uses = [CL] in
790 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
791 "sar{q}\t{%cl, $dst|$dst, %CL}",
792 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
793 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
794 "sar{q}\t{$src, $dst|$dst, $src}",
795 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
796 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
797 "sar{q}\t$dst",
798 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
800 // Rotate instructions
801 let isTwoAddress = 1 in {
802 let Uses = [CL] in
803 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
804 "rol{q}\t{%cl, $dst|$dst, %CL}",
805 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
806 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
807 "rol{q}\t{$src2, $dst|$dst, $src2}",
808 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
809 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
810 "rol{q}\t$dst",
811 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
812 } // isTwoAddress
814 let Uses = [CL] in
815 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
816 "rol{q}\t{%cl, $dst|$dst, %CL}",
817 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
818 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
819 "rol{q}\t{$src, $dst|$dst, $src}",
820 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
821 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
822 "rol{q}\t$dst",
823 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
825 let isTwoAddress = 1 in {
826 let Uses = [CL] in
827 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
828 "ror{q}\t{%cl, $dst|$dst, %CL}",
829 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
830 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
831 "ror{q}\t{$src2, $dst|$dst, $src2}",
832 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
833 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
834 "ror{q}\t$dst",
835 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
836 } // isTwoAddress
838 let Uses = [CL] in
839 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
840 "ror{q}\t{%cl, $dst|$dst, %CL}",
841 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
842 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
843 "ror{q}\t{$src, $dst|$dst, $src}",
844 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
845 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
846 "ror{q}\t$dst",
847 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
849 // Double shift instructions (generalizations of rotate)
850 let isTwoAddress = 1 in {
851 let Uses = [CL] in {
852 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
853 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
854 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
855 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
856 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
857 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
858 }
860 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
861 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
862 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
863 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
864 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
865 (i8 imm:$src3)))]>,
866 TB;
867 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
868 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
869 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
870 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
871 (i8 imm:$src3)))]>,
872 TB;
873 } // isCommutable
874 } // isTwoAddress
876 let Uses = [CL] in {
877 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
878 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
879 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
880 addr:$dst)]>, TB;
881 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
882 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
883 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
884 addr:$dst)]>, TB;
885 }
886 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
887 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
888 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
889 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
890 (i8 imm:$src3)), addr:$dst)]>,
891 TB;
892 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
893 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
894 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
895 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
896 (i8 imm:$src3)), addr:$dst)]>,
897 TB;
898 } // Defs = [EFLAGS]
900 //===----------------------------------------------------------------------===//
901 // Logical Instructions...
902 //
904 let isTwoAddress = 1 , AddedComplexity = 15 in
905 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
906 [(set GR64:$dst, (not GR64:$src))]>;
907 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
908 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
910 let Defs = [EFLAGS] in {
911 def AND64i32 : RI<0x25, RawFrm, (outs), (ins i32imm:$src),
912 "and{q}\t{$src, %rax|%rax, $src}", []>;
914 let isTwoAddress = 1 in {
915 let isCommutable = 1 in
916 def AND64rr : RI<0x21, MRMDestReg,
917 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
918 "and{q}\t{$src2, $dst|$dst, $src2}",
919 [(set GR64:$dst, (and GR64:$src1, GR64:$src2)),
920 (implicit EFLAGS)]>;
921 def AND64rm : RI<0x23, MRMSrcMem,
922 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
923 "and{q}\t{$src2, $dst|$dst, $src2}",
924 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2))),
925 (implicit EFLAGS)]>;
926 def AND64ri8 : RIi8<0x83, MRM4r,
927 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
928 "and{q}\t{$src2, $dst|$dst, $src2}",
929 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2)),
930 (implicit EFLAGS)]>;
931 def AND64ri32 : RIi32<0x81, MRM4r,
932 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
933 "and{q}\t{$src2, $dst|$dst, $src2}",
934 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2)),
935 (implicit EFLAGS)]>;
936 } // isTwoAddress
938 def AND64mr : RI<0x21, MRMDestMem,
939 (outs), (ins i64mem:$dst, GR64:$src),
940 "and{q}\t{$src, $dst|$dst, $src}",
941 [(store (and (load addr:$dst), GR64:$src), addr:$dst),
942 (implicit EFLAGS)]>;
943 def AND64mi8 : RIi8<0x83, MRM4m,
944 (outs), (ins i64mem:$dst, i64i8imm :$src),
945 "and{q}\t{$src, $dst|$dst, $src}",
946 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst),
947 (implicit EFLAGS)]>;
948 def AND64mi32 : RIi32<0x81, MRM4m,
949 (outs), (ins i64mem:$dst, i64i32imm:$src),
950 "and{q}\t{$src, $dst|$dst, $src}",
951 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
952 (implicit EFLAGS)]>;
954 let isTwoAddress = 1 in {
955 let isCommutable = 1 in
956 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
957 "or{q}\t{$src2, $dst|$dst, $src2}",
958 [(set GR64:$dst, (or GR64:$src1, GR64:$src2)),
959 (implicit EFLAGS)]>;
960 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
961 "or{q}\t{$src2, $dst|$dst, $src2}",
962 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2))),
963 (implicit EFLAGS)]>;
964 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
965 "or{q}\t{$src2, $dst|$dst, $src2}",
966 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2)),
967 (implicit EFLAGS)]>;
968 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
969 "or{q}\t{$src2, $dst|$dst, $src2}",
970 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2)),
971 (implicit EFLAGS)]>;
972 } // isTwoAddress
974 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
975 "or{q}\t{$src, $dst|$dst, $src}",
976 [(store (or (load addr:$dst), GR64:$src), addr:$dst),
977 (implicit EFLAGS)]>;
978 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
979 "or{q}\t{$src, $dst|$dst, $src}",
980 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst),
981 (implicit EFLAGS)]>;
982 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
983 "or{q}\t{$src, $dst|$dst, $src}",
984 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
985 (implicit EFLAGS)]>;
987 def OR64i32 : RIi32<0x0D, RawFrm, (outs), (ins i32imm:$src),
988 "or{q}\t{$src, %rax|%rax, $src}", []>;
990 let isTwoAddress = 1 in {
991 let isCommutable = 1 in
992 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
993 "xor{q}\t{$src2, $dst|$dst, $src2}",
994 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2)),
995 (implicit EFLAGS)]>;
996 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
997 "xor{q}\t{$src2, $dst|$dst, $src2}",
998 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2))),
999 (implicit EFLAGS)]>;
1000 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1001 "xor{q}\t{$src2, $dst|$dst, $src2}",
1002 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2)),
1003 (implicit EFLAGS)]>;
1004 def XOR64ri32 : RIi32<0x81, MRM6r,
1005 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1006 "xor{q}\t{$src2, $dst|$dst, $src2}",
1007 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2)),
1008 (implicit EFLAGS)]>;
1009 } // isTwoAddress
1011 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1012 "xor{q}\t{$src, $dst|$dst, $src}",
1013 [(store (xor (load addr:$dst), GR64:$src), addr:$dst),
1014 (implicit EFLAGS)]>;
1015 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
1016 "xor{q}\t{$src, $dst|$dst, $src}",
1017 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst),
1018 (implicit EFLAGS)]>;
1019 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1020 "xor{q}\t{$src, $dst|$dst, $src}",
1021 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst),
1022 (implicit EFLAGS)]>;
1024 def XOR64i32 : RIi32<0x35, RawFrm, (outs), (ins i32imm:$src),
1025 "xor{q}\t{$src, %rax|%rax, $src}", []>;
1027 } // Defs = [EFLAGS]
1029 //===----------------------------------------------------------------------===//
1030 // Comparison Instructions...
1031 //
1033 // Integer comparison
1034 let Defs = [EFLAGS] in {
1035 def TEST64i32 : RI<0xa9, RawFrm, (outs), (ins i32imm:$src),
1036 "test{q}\t{$src, %rax|%rax, $src}", []>;
1037 let isCommutable = 1 in
1038 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1039 "test{q}\t{$src2, $src1|$src1, $src2}",
1040 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
1041 (implicit EFLAGS)]>;
1042 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1043 "test{q}\t{$src2, $src1|$src1, $src2}",
1044 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
1045 (implicit EFLAGS)]>;
1046 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
1047 (ins GR64:$src1, i64i32imm:$src2),
1048 "test{q}\t{$src2, $src1|$src1, $src2}",
1049 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
1050 (implicit EFLAGS)]>;
1051 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
1052 (ins i64mem:$src1, i64i32imm:$src2),
1053 "test{q}\t{$src2, $src1|$src1, $src2}",
1054 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
1055 (implicit EFLAGS)]>;
1058 def CMP64i32 : RI<0x3D, RawFrm, (outs), (ins i32imm:$src),
1059 "cmp{q}\t{$src, %rax|%rax, $src}", []>;
1060 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1061 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1062 [(X86cmp GR64:$src1, GR64:$src2),
1063 (implicit EFLAGS)]>;
1064 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1065 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1066 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
1067 (implicit EFLAGS)]>;
1068 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
1069 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1070 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
1071 (implicit EFLAGS)]>;
1072 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1073 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1074 [(X86cmp GR64:$src1, i64immSExt8:$src2),
1075 (implicit EFLAGS)]>;
1076 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
1077 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1078 [(X86cmp GR64:$src1, i64immSExt32:$src2),
1079 (implicit EFLAGS)]>;
1080 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1081 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1082 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
1083 (implicit EFLAGS)]>;
1084 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
1085 (ins i64mem:$src1, i64i32imm:$src2),
1086 "cmp{q}\t{$src2, $src1|$src1, $src2}",
1087 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
1088 (implicit EFLAGS)]>;
1089 } // Defs = [EFLAGS]
1091 // Bit tests.
1092 // TODO: BTC, BTR, and BTS
1093 let Defs = [EFLAGS] in {
1094 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1095 "bt{q}\t{$src2, $src1|$src1, $src2}",
1096 [(X86bt GR64:$src1, GR64:$src2),
1097 (implicit EFLAGS)]>, TB;
1099 // Unlike with the register+register form, the memory+register form of the
1100 // bt instruction does not ignore the high bits of the index. From ISel's
1101 // perspective, this is pretty bizarre. Disable these instructions for now.
1102 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1103 // "bt{q}\t{$src2, $src1|$src1, $src2}",
1104 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1105 // (implicit EFLAGS)]>, TB;
1107 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1108 "bt{q}\t{$src2, $src1|$src1, $src2}",
1109 [(X86bt GR64:$src1, i64immSExt8:$src2),
1110 (implicit EFLAGS)]>, TB;
1111 // Note that these instructions don't need FastBTMem because that
1112 // only applies when the other operand is in a register. When it's
1113 // an immediate, bt is still fast.
1114 def BT64mi8 : Ii8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1115 "bt{q}\t{$src2, $src1|$src1, $src2}",
1116 [(X86bt (loadi64 addr:$src1), i64immSExt8:$src2),
1117 (implicit EFLAGS)]>, TB;
1118 } // Defs = [EFLAGS]
1120 // Conditional moves
1121 let Uses = [EFLAGS], isTwoAddress = 1 in {
1122 let isCommutable = 1 in {
1123 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
1124 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1125 "cmovb\t{$src2, $dst|$dst, $src2}",
1126 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1127 X86_COND_B, EFLAGS))]>, TB;
1128 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
1129 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1130 "cmovae\t{$src2, $dst|$dst, $src2}",
1131 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1132 X86_COND_AE, EFLAGS))]>, TB;
1133 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
1134 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1135 "cmove\t{$src2, $dst|$dst, $src2}",
1136 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1137 X86_COND_E, EFLAGS))]>, TB;
1138 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
1139 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1140 "cmovne\t{$src2, $dst|$dst, $src2}",
1141 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1142 X86_COND_NE, EFLAGS))]>, TB;
1143 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
1144 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1145 "cmovbe\t{$src2, $dst|$dst, $src2}",
1146 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1147 X86_COND_BE, EFLAGS))]>, TB;
1148 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
1149 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1150 "cmova\t{$src2, $dst|$dst, $src2}",
1151 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1152 X86_COND_A, EFLAGS))]>, TB;
1153 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
1154 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1155 "cmovl\t{$src2, $dst|$dst, $src2}",
1156 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1157 X86_COND_L, EFLAGS))]>, TB;
1158 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
1159 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1160 "cmovge\t{$src2, $dst|$dst, $src2}",
1161 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1162 X86_COND_GE, EFLAGS))]>, TB;
1163 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
1164 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1165 "cmovle\t{$src2, $dst|$dst, $src2}",
1166 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1167 X86_COND_LE, EFLAGS))]>, TB;
1168 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
1169 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1170 "cmovg\t{$src2, $dst|$dst, $src2}",
1171 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1172 X86_COND_G, EFLAGS))]>, TB;
1173 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
1174 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1175 "cmovs\t{$src2, $dst|$dst, $src2}",
1176 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1177 X86_COND_S, EFLAGS))]>, TB;
1178 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
1179 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1180 "cmovns\t{$src2, $dst|$dst, $src2}",
1181 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1182 X86_COND_NS, EFLAGS))]>, TB;
1183 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
1184 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1185 "cmovp\t{$src2, $dst|$dst, $src2}",
1186 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1187 X86_COND_P, EFLAGS))]>, TB;
1188 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
1189 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1190 "cmovnp\t{$src2, $dst|$dst, $src2}",
1191 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1192 X86_COND_NP, EFLAGS))]>, TB;
1193 def CMOVO64rr : RI<0x40, MRMSrcReg, // if overflow, GR64 = GR64
1194 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1195 "cmovo\t{$src2, $dst|$dst, $src2}",
1196 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1197 X86_COND_O, EFLAGS))]>, TB;
1198 def CMOVNO64rr : RI<0x41, MRMSrcReg, // if !overflow, GR64 = GR64
1199 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1200 "cmovno\t{$src2, $dst|$dst, $src2}",
1201 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
1202 X86_COND_NO, EFLAGS))]>, TB;
1203 } // isCommutable = 1
1205 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
1206 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1207 "cmovb\t{$src2, $dst|$dst, $src2}",
1208 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1209 X86_COND_B, EFLAGS))]>, TB;
1210 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
1211 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1212 "cmovae\t{$src2, $dst|$dst, $src2}",
1213 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1214 X86_COND_AE, EFLAGS))]>, TB;
1215 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
1216 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1217 "cmove\t{$src2, $dst|$dst, $src2}",
1218 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1219 X86_COND_E, EFLAGS))]>, TB;
1220 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
1221 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1222 "cmovne\t{$src2, $dst|$dst, $src2}",
1223 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1224 X86_COND_NE, EFLAGS))]>, TB;
1225 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
1226 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1227 "cmovbe\t{$src2, $dst|$dst, $src2}",
1228 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1229 X86_COND_BE, EFLAGS))]>, TB;
1230 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
1231 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1232 "cmova\t{$src2, $dst|$dst, $src2}",
1233 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1234 X86_COND_A, EFLAGS))]>, TB;
1235 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
1236 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1237 "cmovl\t{$src2, $dst|$dst, $src2}",
1238 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1239 X86_COND_L, EFLAGS))]>, TB;
1240 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
1241 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1242 "cmovge\t{$src2, $dst|$dst, $src2}",
1243 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1244 X86_COND_GE, EFLAGS))]>, TB;
1245 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
1246 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1247 "cmovle\t{$src2, $dst|$dst, $src2}",
1248 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1249 X86_COND_LE, EFLAGS))]>, TB;
1250 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
1251 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1252 "cmovg\t{$src2, $dst|$dst, $src2}",
1253 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1254 X86_COND_G, EFLAGS))]>, TB;
1255 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
1256 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1257 "cmovs\t{$src2, $dst|$dst, $src2}",
1258 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1259 X86_COND_S, EFLAGS))]>, TB;
1260 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
1261 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1262 "cmovns\t{$src2, $dst|$dst, $src2}",
1263 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1264 X86_COND_NS, EFLAGS))]>, TB;
1265 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
1266 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1267 "cmovp\t{$src2, $dst|$dst, $src2}",
1268 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1269 X86_COND_P, EFLAGS))]>, TB;
1270 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
1271 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1272 "cmovnp\t{$src2, $dst|$dst, $src2}",
1273 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1274 X86_COND_NP, EFLAGS))]>, TB;
1275 def CMOVO64rm : RI<0x40, MRMSrcMem, // if overflow, GR64 = [mem64]
1276 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1277 "cmovo\t{$src2, $dst|$dst, $src2}",
1278 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1279 X86_COND_O, EFLAGS))]>, TB;
1280 def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
1281 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
1282 "cmovno\t{$src2, $dst|$dst, $src2}",
1283 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
1284 X86_COND_NO, EFLAGS))]>, TB;
1285 } // isTwoAddress
1287 //===----------------------------------------------------------------------===//
1288 // Conversion Instructions...
1289 //
1291 // f64 -> signed i64
1292 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1293 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1294 [(set GR64:$dst,
1295 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
1296 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1297 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1298 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
1299 (load addr:$src)))]>;
1300 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1301 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1302 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
1303 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
1304 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1305 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1306 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1307 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1308 [(set GR64:$dst,
1309 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1310 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1311 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1312 [(set GR64:$dst,
1313 (int_x86_sse2_cvttsd2si64
1314 (load addr:$src)))]>;
1316 // Signed i64 -> f64
1317 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1318 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1319 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1320 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1321 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1322 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1324 let isTwoAddress = 1 in {
1325 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1326 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1327 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1328 [(set VR128:$dst,
1329 (int_x86_sse2_cvtsi642sd VR128:$src1,
1330 GR64:$src2))]>;
1331 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1332 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1333 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1334 [(set VR128:$dst,
1335 (int_x86_sse2_cvtsi642sd VR128:$src1,
1336 (loadi64 addr:$src2)))]>;
1337 } // isTwoAddress
1339 // Signed i64 -> f32
1340 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1341 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1342 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1343 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1344 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1345 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1347 let isTwoAddress = 1 in {
1348 def Int_CVTSI2SS64rr : RSSI<0x2A, MRMSrcReg,
1349 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1350 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1351 [(set VR128:$dst,
1352 (int_x86_sse_cvtsi642ss VR128:$src1,
1353 GR64:$src2))]>;
1354 def Int_CVTSI2SS64rm : RSSI<0x2A, MRMSrcMem,
1355 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1356 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1357 [(set VR128:$dst,
1358 (int_x86_sse_cvtsi642ss VR128:$src1,
1359 (loadi64 addr:$src2)))]>;
1360 }
1362 // f32 -> signed i64
1363 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1364 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1365 [(set GR64:$dst,
1366 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1367 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1368 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1369 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1370 (load addr:$src)))]>;
1371 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1372 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1373 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1374 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1375 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1376 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1377 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1378 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1379 [(set GR64:$dst,
1380 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1381 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1382 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1383 [(set GR64:$dst,
1384 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1386 //===----------------------------------------------------------------------===//
1387 // Alias Instructions
1388 //===----------------------------------------------------------------------===//
1390 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1391 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1392 // encoding.
1393 // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove
1394 // when we have a better way to specify isel priority.
1395 let AddedComplexity = 1 in
1396 def : Pat<(i64 0),
1397 (SUBREG_TO_REG (i64 0), (MOV32r0), x86_subreg_32bit)>;
1400 // Materialize i64 constant where top 32-bits are zero.
1401 let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1402 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1403 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1404 [(set GR64:$dst, i64immZExt32:$src)]>;
1406 //===----------------------------------------------------------------------===//
1407 // Thread Local Storage Instructions
1408 //===----------------------------------------------------------------------===//
1410 // All calls clobber the non-callee saved registers. RSP is marked as
1411 // a use to prevent stack-pointer assignments that appear immediately
1412 // before calls from potentially appearing dead.
1413 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
1414 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1,
1415 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
1416 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
1417 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
1418 Uses = [RSP] in
1419 def TLS_addr64 : I<0, Pseudo, (outs), (ins lea64mem:$sym),
1420 ".byte\t0x66; "
1421 "leaq\t$sym(%rip), %rdi; "
1422 ".word\t0x6666; "
1423 "rex64; "
1424 "call\t__tls_get_addr@PLT",
1425 [(X86tlsaddr tls64addr:$sym)]>,
1426 Requires<[In64BitMode]>;
1428 let AddedComplexity = 5, isCodeGenOnly = 1 in
1429 def MOV64GSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1430 "movq\t%gs:$src, $dst",
1431 [(set GR64:$dst, (gsload addr:$src))]>, SegGS;
1433 let AddedComplexity = 5, isCodeGenOnly = 1 in
1434 def MOV64FSrm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1435 "movq\t%fs:$src, $dst",
1436 [(set GR64:$dst, (fsload addr:$src))]>, SegFS;
1438 //===----------------------------------------------------------------------===//
1439 // Atomic Instructions
1440 //===----------------------------------------------------------------------===//
1442 let Defs = [RAX, EFLAGS], Uses = [RAX] in {
1443 def LCMPXCHG64 : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$ptr, GR64:$swap),
1444 "lock\n\t"
1445 "cmpxchgq\t$swap,$ptr",
1446 [(X86cas addr:$ptr, GR64:$swap, 8)]>, TB, LOCK;
1447 }
1449 let Constraints = "$val = $dst" in {
1450 let Defs = [EFLAGS] in
1451 def LXADD64 : RI<0xC1, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1452 "lock\n\t"
1453 "xadd\t$val, $ptr",
1454 [(set GR64:$dst, (atomic_load_add_64 addr:$ptr, GR64:$val))]>,
1455 TB, LOCK;
1457 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$ptr,GR64:$val),
1458 "xchg\t$val, $ptr",
1459 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>;
1460 }
1462 // Optimized codegen when the non-memory output is not used.
1463 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
1464 def LOCK_ADD64mr : RI<0x03, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1465 "lock\n\t"
1466 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1467 def LOCK_ADD64mi8 : RIi8<0x83, MRM0m, (outs),
1468 (ins i64mem:$dst, i64i8imm :$src2),
1469 "lock\n\t"
1470 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1471 def LOCK_ADD64mi32 : RIi32<0x81, MRM0m, (outs),
1472 (ins i64mem:$dst, i64i32imm :$src2),
1473 "lock\n\t"
1474 "add{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1475 def LOCK_SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
1476 "lock\n\t"
1477 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1478 def LOCK_SUB64mi8 : RIi8<0x83, MRM5m, (outs),
1479 (ins i64mem:$dst, i64i8imm :$src2),
1480 "lock\n\t"
1481 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1482 def LOCK_SUB64mi32 : RIi32<0x81, MRM5m, (outs),
1483 (ins i64mem:$dst, i64i32imm:$src2),
1484 "lock\n\t"
1485 "sub{q}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
1486 def LOCK_INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst),
1487 "lock\n\t"
1488 "inc{q}\t$dst", []>, LOCK;
1489 def LOCK_DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst),
1490 "lock\n\t"
1491 "dec{q}\t$dst", []>, LOCK;
1493 // Atomic exchange, and, or, xor
1494 let Constraints = "$val = $dst", Defs = [EFLAGS],
1495 usesCustomDAGSchedInserter = 1 in {
1496 def ATOMAND64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1497 "#ATOMAND64 PSEUDO!",
1498 [(set GR64:$dst, (atomic_load_and_64 addr:$ptr, GR64:$val))]>;
1499 def ATOMOR64 : I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1500 "#ATOMOR64 PSEUDO!",
1501 [(set GR64:$dst, (atomic_load_or_64 addr:$ptr, GR64:$val))]>;
1502 def ATOMXOR64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1503 "#ATOMXOR64 PSEUDO!",
1504 [(set GR64:$dst, (atomic_load_xor_64 addr:$ptr, GR64:$val))]>;
1505 def ATOMNAND64 : I<0, Pseudo,(outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1506 "#ATOMNAND64 PSEUDO!",
1507 [(set GR64:$dst, (atomic_load_nand_64 addr:$ptr, GR64:$val))]>;
1508 def ATOMMIN64: I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$ptr, GR64:$val),
1509 "#ATOMMIN64 PSEUDO!",
1510 [(set GR64:$dst, (atomic_load_min_64 addr:$ptr, GR64:$val))]>;
1511 def ATOMMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1512 "#ATOMMAX64 PSEUDO!",
1513 [(set GR64:$dst, (atomic_load_max_64 addr:$ptr, GR64:$val))]>;
1514 def ATOMUMIN64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1515 "#ATOMUMIN64 PSEUDO!",
1516 [(set GR64:$dst, (atomic_load_umin_64 addr:$ptr, GR64:$val))]>;
1517 def ATOMUMAX64: I<0, Pseudo, (outs GR64:$dst),(ins i64mem:$ptr, GR64:$val),
1518 "#ATOMUMAX64 PSEUDO!",
1519 [(set GR64:$dst, (atomic_load_umax_64 addr:$ptr, GR64:$val))]>;
1520 }
1522 //===----------------------------------------------------------------------===//
1523 // Non-Instruction Patterns
1524 //===----------------------------------------------------------------------===//
1526 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable when not in small
1527 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
1528 // 'movabs' predicate should handle this sort of thing.
1529 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1530 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1531 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1532 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1533 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1534 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1535 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1536 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1538 // In static codegen with small code model, we can get the address of a label
1539 // into a register with 'movl'. FIXME: This is a hack, the 'imm' predicate of
1540 // the MOV64ri64i32 should accept these.
1541 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1542 (MOV64ri64i32 tconstpool :$dst)>, Requires<[SmallCode]>;
1543 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1544 (MOV64ri64i32 tjumptable :$dst)>, Requires<[SmallCode]>;
1545 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1546 (MOV64ri64i32 tglobaladdr :$dst)>, Requires<[SmallCode]>;
1547 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1548 (MOV64ri64i32 texternalsym:$dst)>, Requires<[SmallCode]>;
1550 // In kernel code model, we can get the address of a label
1551 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1552 // the MOV64ri32 should accept these.
1553 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1554 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1555 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1556 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1557 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1558 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1559 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1560 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1562 // If we have small model and -static mode, it is safe to store global addresses
1563 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1564 // for MOV64mi32 should handle this sort of thing.
1565 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1566 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1567 Requires<[NearData, IsStatic]>;
1568 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1569 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1570 Requires<[NearData, IsStatic]>;
1571 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1572 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1573 Requires<[NearData, IsStatic]>;
1574 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1575 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1576 Requires<[NearData, IsStatic]>;
1578 // Calls
1579 // Direct PC relative function call for small code model. 32-bit displacement
1580 // sign extended to 64-bit.
1581 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1582 (CALL64pcrel32 tglobaladdr:$dst)>, Requires<[NotWin64]>;
1583 def : Pat<(X86call (i64 texternalsym:$dst)),
1584 (CALL64pcrel32 texternalsym:$dst)>, Requires<[NotWin64]>;
1586 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1587 (WINCALL64pcrel32 tglobaladdr:$dst)>, Requires<[IsWin64]>;
1588 def : Pat<(X86call (i64 texternalsym:$dst)),
1589 (WINCALL64pcrel32 texternalsym:$dst)>, Requires<[IsWin64]>;
1591 // tailcall stuff
1592 def : Pat<(X86tcret GR64:$dst, imm:$off),
1593 (TCRETURNri64 GR64:$dst, imm:$off)>;
1595 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1596 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1598 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1599 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1601 // Comparisons.
1603 // TEST R,R is smaller than CMP R,0
1604 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1605 (TEST64rr GR64:$src1, GR64:$src1)>;
1607 // Conditional moves with folded loads with operands swapped and conditions
1608 // inverted.
1609 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_B, EFLAGS),
1610 (CMOVAE64rm GR64:$src2, addr:$src1)>;
1611 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_AE, EFLAGS),
1612 (CMOVB64rm GR64:$src2, addr:$src1)>;
1613 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_E, EFLAGS),
1614 (CMOVNE64rm GR64:$src2, addr:$src1)>;
1615 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NE, EFLAGS),
1616 (CMOVE64rm GR64:$src2, addr:$src1)>;
1617 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_BE, EFLAGS),
1618 (CMOVA64rm GR64:$src2, addr:$src1)>;
1619 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_A, EFLAGS),
1620 (CMOVBE64rm GR64:$src2, addr:$src1)>;
1621 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_L, EFLAGS),
1622 (CMOVGE64rm GR64:$src2, addr:$src1)>;
1623 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_GE, EFLAGS),
1624 (CMOVL64rm GR64:$src2, addr:$src1)>;
1625 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_LE, EFLAGS),
1626 (CMOVG64rm GR64:$src2, addr:$src1)>;
1627 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_G, EFLAGS),
1628 (CMOVLE64rm GR64:$src2, addr:$src1)>;
1629 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_P, EFLAGS),
1630 (CMOVNP64rm GR64:$src2, addr:$src1)>;
1631 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NP, EFLAGS),
1632 (CMOVP64rm GR64:$src2, addr:$src1)>;
1633 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_S, EFLAGS),
1634 (CMOVNS64rm GR64:$src2, addr:$src1)>;
1635 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NS, EFLAGS),
1636 (CMOVS64rm GR64:$src2, addr:$src1)>;
1637 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_O, EFLAGS),
1638 (CMOVNO64rm GR64:$src2, addr:$src1)>;
1639 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, X86_COND_NO, EFLAGS),
1640 (CMOVO64rm GR64:$src2, addr:$src1)>;
1642 // zextload bool -> zextload byte
1643 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1645 // extload
1646 // When extloading from 16-bit and smaller memory locations into 64-bit registers,
1647 // use zero-extending loads so that the entire 64-bit register is defined, avoiding
1648 // partial-register updates.
1649 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1650 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1651 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1652 // For other extloads, use subregs, since the high contents of the register are
1653 // defined after an extload.
1654 def : Pat<(extloadi64i32 addr:$src),
1655 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src),
1656 x86_subreg_32bit)>;
1658 // anyext. Define these to do an explicit zero-extend to
1659 // avoid partial-register updates.
1660 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1661 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16 :$src)>;
1662 def : Pat<(i64 (anyext GR32:$src)),
1663 (SUBREG_TO_REG (i64 0), GR32:$src, x86_subreg_32bit)>;
1665 //===----------------------------------------------------------------------===//
1666 // Some peepholes
1667 //===----------------------------------------------------------------------===//
1669 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1670 // +128 doesn't, so in this special case use a sub instead of an add.
1671 def : Pat<(add GR64:$src1, 128),
1672 (SUB64ri8 GR64:$src1, -128)>;
1673 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1674 (SUB64mi8 addr:$dst, -128)>;
1676 // The same trick applies for 32-bit immediate fields in 64-bit
1677 // instructions.
1678 def : Pat<(add GR64:$src1, 0x0000000080000000),
1679 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1680 def : Pat<(store (add (loadi64 addr:$dst), 0x00000000800000000), addr:$dst),
1681 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1683 // r & (2^32-1) ==> movz
1684 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1685 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1686 // r & (2^16-1) ==> movz
1687 def : Pat<(and GR64:$src, 0xffff),
1688 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)))>;
1689 // r & (2^8-1) ==> movz
1690 def : Pat<(and GR64:$src, 0xff),
1691 (MOVZX64rr8 (i8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)))>;
1692 // r & (2^8-1) ==> movz
1693 def : Pat<(and GR32:$src1, 0xff),
1694 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, x86_subreg_8bit))>,
1695 Requires<[In64BitMode]>;
1696 // r & (2^8-1) ==> movz
1697 def : Pat<(and GR16:$src1, 0xff),
1698 (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, x86_subreg_8bit)))>,
1699 Requires<[In64BitMode]>;
1701 // sext_inreg patterns
1702 def : Pat<(sext_inreg GR64:$src, i32),
1703 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit))>;
1704 def : Pat<(sext_inreg GR64:$src, i16),
1705 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
1706 def : Pat<(sext_inreg GR64:$src, i8),
1707 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit))>;
1708 def : Pat<(sext_inreg GR32:$src, i8),
1709 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit))>,
1710 Requires<[In64BitMode]>;
1711 def : Pat<(sext_inreg GR16:$src, i8),
1712 (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)))>,
1713 Requires<[In64BitMode]>;
1715 // trunc patterns
1716 def : Pat<(i32 (trunc GR64:$src)),
1717 (EXTRACT_SUBREG GR64:$src, x86_subreg_32bit)>;
1718 def : Pat<(i16 (trunc GR64:$src)),
1719 (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit)>;
1720 def : Pat<(i8 (trunc GR64:$src)),
1721 (EXTRACT_SUBREG GR64:$src, x86_subreg_8bit)>;
1722 def : Pat<(i8 (trunc GR32:$src)),
1723 (EXTRACT_SUBREG GR32:$src, x86_subreg_8bit)>,
1724 Requires<[In64BitMode]>;
1725 def : Pat<(i8 (trunc GR16:$src)),
1726 (EXTRACT_SUBREG GR16:$src, x86_subreg_8bit)>,
1727 Requires<[In64BitMode]>;
1729 // h-register tricks.
1730 // For now, be conservative on x86-64 and use an h-register extract only if the
1731 // value is immediately zero-extended or stored, which are somewhat common
1732 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1733 // from being allocated in the same instruction as the h register, as there's
1734 // currently no way to describe this requirement to the register allocator.
1736 // h-register extract and zero-extend.
1737 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1738 (SUBREG_TO_REG
1739 (i64 0),
1740 (MOVZX32_NOREXrr8
1741 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1742 x86_subreg_8bit_hi)),
1743 x86_subreg_32bit)>;
1744 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1745 (MOVZX32_NOREXrr8
1746 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1747 x86_subreg_8bit_hi))>,
1748 Requires<[In64BitMode]>;
1749 def : Pat<(srl_su GR16:$src, (i8 8)),
1750 (EXTRACT_SUBREG
1751 (MOVZX32_NOREXrr8
1752 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1753 x86_subreg_8bit_hi)),
1754 x86_subreg_16bit)>,
1755 Requires<[In64BitMode]>;
1756 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1757 (MOVZX32_NOREXrr8
1758 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1759 x86_subreg_8bit_hi))>,
1760 Requires<[In64BitMode]>;
1761 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1762 (MOVZX32_NOREXrr8
1763 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1764 x86_subreg_8bit_hi))>,
1765 Requires<[In64BitMode]>;
1766 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1767 (SUBREG_TO_REG
1768 (i64 0),
1769 (MOVZX32_NOREXrr8
1770 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1771 x86_subreg_8bit_hi)),
1772 x86_subreg_32bit)>;
1773 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1774 (SUBREG_TO_REG
1775 (i64 0),
1776 (MOVZX32_NOREXrr8
1777 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1778 x86_subreg_8bit_hi)),
1779 x86_subreg_32bit)>;
1781 // h-register extract and store.
1782 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1783 (MOV8mr_NOREX
1784 addr:$dst,
1785 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
1786 x86_subreg_8bit_hi))>;
1787 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1788 (MOV8mr_NOREX
1789 addr:$dst,
1790 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
1791 x86_subreg_8bit_hi))>,
1792 Requires<[In64BitMode]>;
1793 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1794 (MOV8mr_NOREX
1795 addr:$dst,
1796 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
1797 x86_subreg_8bit_hi))>,
1798 Requires<[In64BitMode]>;
1800 // (shl x, 1) ==> (add x, x)
1801 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1803 // (shl x (and y, 63)) ==> (shl x, y)
1804 def : Pat<(shl GR64:$src1, (and CL:$amt, 63)),
1805 (SHL64rCL GR64:$src1)>;
1806 def : Pat<(store (shl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1807 (SHL64mCL addr:$dst)>;
1809 def : Pat<(srl GR64:$src1, (and CL:$amt, 63)),
1810 (SHR64rCL GR64:$src1)>;
1811 def : Pat<(store (srl (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1812 (SHR64mCL addr:$dst)>;
1814 def : Pat<(sra GR64:$src1, (and CL:$amt, 63)),
1815 (SAR64rCL GR64:$src1)>;
1816 def : Pat<(store (sra (loadi64 addr:$dst), (and CL:$amt, 63)), addr:$dst),
1817 (SAR64mCL addr:$dst)>;
1819 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1820 def : Pat<(or (srl GR64:$src1, CL:$amt),
1821 (shl GR64:$src2, (sub 64, CL:$amt))),
1822 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1824 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1825 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1826 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1828 def : Pat<(or (srl GR64:$src1, (i8 (trunc RCX:$amt))),
1829 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1830 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1832 def : Pat<(store (or (srl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1833 (shl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1834 addr:$dst),
1835 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1837 def : Pat<(shrd GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1838 (SHRD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1840 def : Pat<(store (shrd (loadi64 addr:$dst), (i8 imm:$amt1),
1841 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1842 (SHRD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1844 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1845 def : Pat<(or (shl GR64:$src1, CL:$amt),
1846 (srl GR64:$src2, (sub 64, CL:$amt))),
1847 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1849 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1850 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1851 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1853 def : Pat<(or (shl GR64:$src1, (i8 (trunc RCX:$amt))),
1854 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1855 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1857 def : Pat<(store (or (shl (loadi64 addr:$dst), (i8 (trunc RCX:$amt))),
1858 (srl GR64:$src2, (i8 (trunc (sub 64, RCX:$amt))))),
1859 addr:$dst),
1860 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1862 def : Pat<(shld GR64:$src1, (i8 imm:$amt1), GR64:$src2, (i8 imm:$amt2)),
1863 (SHLD64rri8 GR64:$src1, GR64:$src2, (i8 imm:$amt1))>;
1865 def : Pat<(store (shld (loadi64 addr:$dst), (i8 imm:$amt1),
1866 GR64:$src2, (i8 imm:$amt2)), addr:$dst),
1867 (SHLD64mri8 addr:$dst, GR64:$src2, (i8 imm:$amt1))>;
1869 // X86 specific add which produces a flag.
1870 def : Pat<(addc GR64:$src1, GR64:$src2),
1871 (ADD64rr GR64:$src1, GR64:$src2)>;
1872 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1873 (ADD64rm GR64:$src1, addr:$src2)>;
1874 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1875 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1876 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1877 (ADD64ri32 GR64:$src1, imm:$src2)>;
1879 def : Pat<(subc GR64:$src1, GR64:$src2),
1880 (SUB64rr GR64:$src1, GR64:$src2)>;
1881 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1882 (SUB64rm GR64:$src1, addr:$src2)>;
1883 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1884 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1885 def : Pat<(subc GR64:$src1, imm:$src2),
1886 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1888 //===----------------------------------------------------------------------===//
1889 // EFLAGS-defining Patterns
1890 //===----------------------------------------------------------------------===//
1892 // Register-Register Addition with EFLAGS result
1893 def : Pat<(parallel (X86add_flag GR64:$src1, GR64:$src2),
1894 (implicit EFLAGS)),
1895 (ADD64rr GR64:$src1, GR64:$src2)>;
1897 // Register-Integer Addition with EFLAGS result
1898 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt8:$src2),
1899 (implicit EFLAGS)),
1900 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1901 def : Pat<(parallel (X86add_flag GR64:$src1, i64immSExt32:$src2),
1902 (implicit EFLAGS)),
1903 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1905 // Register-Memory Addition with EFLAGS result
1906 def : Pat<(parallel (X86add_flag GR64:$src1, (loadi64 addr:$src2)),
1907 (implicit EFLAGS)),
1908 (ADD64rm GR64:$src1, addr:$src2)>;
1910 // Memory-Register Addition with EFLAGS result
1911 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), GR64:$src2),
1912 addr:$dst),
1913 (implicit EFLAGS)),
1914 (ADD64mr addr:$dst, GR64:$src2)>;
1915 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1916 addr:$dst),
1917 (implicit EFLAGS)),
1918 (ADD64mi8 addr:$dst, i64immSExt8:$src2)>;
1919 def : Pat<(parallel (store (X86add_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1920 addr:$dst),
1921 (implicit EFLAGS)),
1922 (ADD64mi32 addr:$dst, i64immSExt32:$src2)>;
1924 // Register-Register Subtraction with EFLAGS result
1925 def : Pat<(parallel (X86sub_flag GR64:$src1, GR64:$src2),
1926 (implicit EFLAGS)),
1927 (SUB64rr GR64:$src1, GR64:$src2)>;
1929 // Register-Memory Subtraction with EFLAGS result
1930 def : Pat<(parallel (X86sub_flag GR64:$src1, (loadi64 addr:$src2)),
1931 (implicit EFLAGS)),
1932 (SUB64rm GR64:$src1, addr:$src2)>;
1934 // Register-Integer Subtraction with EFLAGS result
1935 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt8:$src2),
1936 (implicit EFLAGS)),
1937 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1938 def : Pat<(parallel (X86sub_flag GR64:$src1, i64immSExt32:$src2),
1939 (implicit EFLAGS)),
1940 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1942 // Memory-Register Subtraction with EFLAGS result
1943 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), GR64:$src2),
1944 addr:$dst),
1945 (implicit EFLAGS)),
1946 (SUB64mr addr:$dst, GR64:$src2)>;
1948 // Memory-Integer Subtraction with EFLAGS result
1949 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt8:$src2),
1950 addr:$dst),
1951 (implicit EFLAGS)),
1952 (SUB64mi8 addr:$dst, i64immSExt8:$src2)>;
1953 def : Pat<(parallel (store (X86sub_flag (loadi64 addr:$dst), i64immSExt32:$src2),
1954 addr:$dst),
1955 (implicit EFLAGS)),
1956 (SUB64mi32 addr:$dst, i64immSExt32:$src2)>;
1958 // Register-Register Signed Integer Multiplication with EFLAGS result
1959 def : Pat<(parallel (X86smul_flag GR64:$src1, GR64:$src2),
1960 (implicit EFLAGS)),
1961 (IMUL64rr GR64:$src1, GR64:$src2)>;
1963 // Register-Memory Signed Integer Multiplication with EFLAGS result
1964 def : Pat<(parallel (X86smul_flag GR64:$src1, (loadi64 addr:$src2)),
1965 (implicit EFLAGS)),
1966 (IMUL64rm GR64:$src1, addr:$src2)>;
1968 // Register-Integer Signed Integer Multiplication with EFLAGS result
1969 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt8:$src2),
1970 (implicit EFLAGS)),
1971 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1972 def : Pat<(parallel (X86smul_flag GR64:$src1, i64immSExt32:$src2),
1973 (implicit EFLAGS)),
1974 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1976 // Memory-Integer Signed Integer Multiplication with EFLAGS result
1977 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt8:$src2),
1978 (implicit EFLAGS)),
1979 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1980 def : Pat<(parallel (X86smul_flag (loadi64 addr:$src1), i64immSExt32:$src2),
1981 (implicit EFLAGS)),
1982 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1984 // INC and DEC with EFLAGS result. Note that these do not set CF.
1985 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
1986 (INC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1987 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
1988 (implicit EFLAGS)),
1989 (INC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1990 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
1991 (DEC64_16r GR16:$src)>, Requires<[In64BitMode]>;
1992 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
1993 (implicit EFLAGS)),
1994 (DEC64_16m addr:$dst)>, Requires<[In64BitMode]>;
1996 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
1997 (INC64_32r GR32:$src)>, Requires<[In64BitMode]>;
1998 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
1999 (implicit EFLAGS)),
2000 (INC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2001 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
2002 (DEC64_32r GR32:$src)>, Requires<[In64BitMode]>;
2003 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
2004 (implicit EFLAGS)),
2005 (DEC64_32m addr:$dst)>, Requires<[In64BitMode]>;
2007 def : Pat<(parallel (X86inc_flag GR64:$src), (implicit EFLAGS)),
2008 (INC64r GR64:$src)>;
2009 def : Pat<(parallel (store (i64 (X86inc_flag (loadi64 addr:$dst))), addr:$dst),
2010 (implicit EFLAGS)),
2011 (INC64m addr:$dst)>;
2012 def : Pat<(parallel (X86dec_flag GR64:$src), (implicit EFLAGS)),
2013 (DEC64r GR64:$src)>;
2014 def : Pat<(parallel (store (i64 (X86dec_flag (loadi64 addr:$dst))), addr:$dst),
2015 (implicit EFLAGS)),
2016 (DEC64m addr:$dst)>;
2018 //===----------------------------------------------------------------------===//
2019 // X86-64 SSE Instructions
2020 //===----------------------------------------------------------------------===//
2022 // Move instructions...
2024 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2025 "mov{d|q}\t{$src, $dst|$dst, $src}",
2026 [(set VR128:$dst,
2027 (v2i64 (scalar_to_vector GR64:$src)))]>;
2028 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2029 "mov{d|q}\t{$src, $dst|$dst, $src}",
2030 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2031 (iPTR 0)))]>;
2033 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2034 "mov{d|q}\t{$src, $dst|$dst, $src}",
2035 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2036 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2037 "movq\t{$src, $dst|$dst, $src}",
2038 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2040 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2041 "mov{d|q}\t{$src, $dst|$dst, $src}",
2042 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2043 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2044 "movq\t{$src, $dst|$dst, $src}",
2045 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2047 //===----------------------------------------------------------------------===//
2048 // X86-64 SSE4.1 Instructions
2049 //===----------------------------------------------------------------------===//
2051 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
2052 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
2053 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
2054 (ins VR128:$src1, i32i8imm:$src2),
2055 !strconcat(OpcodeStr,
2056 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2057 [(set GR64:$dst,
2058 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
2059 def mr : SS4AIi8<opc, MRMDestMem, (outs),
2060 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
2061 !strconcat(OpcodeStr,
2062 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2063 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
2064 addr:$dst)]>, OpSize, REX_W;
2065 }
2067 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
2069 let isTwoAddress = 1 in {
2070 multiclass SS41I_insert64<bits<8> opc, string OpcodeStr> {
2071 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
2072 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2073 !strconcat(OpcodeStr,
2074 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2075 [(set VR128:$dst,
2076 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
2077 OpSize, REX_W;
2078 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
2079 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
2080 !strconcat(OpcodeStr,
2081 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2082 [(set VR128:$dst,
2083 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
2084 imm:$src3)))]>, OpSize, REX_W;
2085 }
2086 }
2088 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
2090 // -disable-16bit support.
2091 def : Pat<(truncstorei16 (i64 imm:$src), addr:$dst),
2092 (MOV16mi addr:$dst, imm:$src)>;
2093 def : Pat<(truncstorei16 GR64:$src, addr:$dst),
2094 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
2095 def : Pat<(i64 (sextloadi16 addr:$dst)),
2096 (MOVSX64rm16 addr:$dst)>;
2097 def : Pat<(i64 (zextloadi16 addr:$dst)),
2098 (MOVZX64rm16 addr:$dst)>;
2099 def : Pat<(i64 (extloadi16 addr:$dst)),
2100 (MOVZX64rm16 addr:$dst)>;