lib/Target/X86/X86InstrInfo.h

   1 //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the X86 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef X86INSTRUCTIONINFO_H
  15 #define X86INSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "X86.h"
  19 #include "X86RegisterInfo.h"
  20 #include "llvm/ADT/DenseMap.h"
  21 #include "llvm/Target/TargetRegisterInfo.h"
  22
  23 namespace llvm {
  24   class X86RegisterInfo;
  25   class X86TargetMachine;
  26
  27 namespace X86 {
  28   // X86 specific condition code. These correspond to X86_*_COND in
  29   // X86InstrInfo.td. They must be kept in synch.
  30   enum CondCode {
  31     COND_A  = 0,
  32     COND_AE = 1,
  33     COND_B  = 2,
  34     COND_BE = 3,
  35     COND_E  = 4,
  36     COND_G  = 5,
  37     COND_GE = 6,
  38     COND_L  = 7,
  39     COND_LE = 8,
  40     COND_NE = 9,
  41     COND_NO = 10,
  42     COND_NP = 11,
  43     COND_NS = 12,
  44     COND_O  = 13,
  45     COND_P  = 14,
  46     COND_S  = 15,
  47
  48     // Artificial condition codes. These are used by AnalyzeBranch
  49     // to indicate a block terminated with two conditional branches to
  50     // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
  51     // which can't be represented on x86 with a single condition. These
  52     // are never used in MachineInstrs.
  53     COND_NE_OR_P,
  54     COND_NP_OR_E,
  55
  56     COND_INVALID
  57   };
  58
  59   // Turn condition code into conditional branch opcode.
  60   unsigned GetCondBranchFromCond(CondCode CC);
  61
  62   /// GetOppositeBranchCondition - Return the inverse of the specified cond,
  63   /// e.g. turning COND_E to COND_NE.
  64   CondCode GetOppositeBranchCondition(X86::CondCode CC);
  65
  66 }
  67
  68 /// X86II - This namespace holds all of the target specific flags that
  69 /// instruction info tracks.
  70 ///
  71 namespace X86II {
  72   /// Target Operand Flag enum.
  73   enum TOF {
  74     //===------------------------------------------------------------------===//
  75     // X86 Specific MachineOperand flags.
  76
  77     MO_NO_FLAG = 0,
  78
  79     /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
  80     /// relocation of:
  81     ///    SYMBOL_LABEL + [. - PICBASELABEL]
  82     MO_GOT_ABSOLUTE_ADDRESS = 1,
  83
  84     /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
  85     /// immediate should get the value of the symbol minus the PIC base label:
  86     ///    SYMBOL_LABEL - PICBASELABEL
  87     MO_PIC_BASE_OFFSET = 2,
  88
  89     /// MO_GOT - On a symbol operand this indicates that the immediate is the
  90     /// offset to the GOT entry for the symbol name from the base of the GOT.
  91     ///
  92     /// See the X86-64 ELF ABI supplement for more details.
  93     ///    SYMBOL_LABEL @GOT
  94     MO_GOT = 3,
  95
  96     /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
  97     /// the offset to the location of the symbol name from the base of the GOT.
  98     ///
  99     /// See the X86-64 ELF ABI supplement for more details.
 100     ///    SYMBOL_LABEL @GOTOFF
 101     MO_GOTOFF = 4,
 102
 103     /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
 104     /// offset to the GOT entry for the symbol name from the current code
 105     /// location.
 106     ///
 107     /// See the X86-64 ELF ABI supplement for more details.
 108     ///    SYMBOL_LABEL @GOTPCREL
 109     MO_GOTPCREL = 5,
 110
 111     /// MO_PLT - On a symbol operand this indicates that the immediate is
 112     /// offset to the PLT entry of symbol name from the current code location.
 113     ///
 114     /// See the X86-64 ELF ABI supplement for more details.
 115     ///    SYMBOL_LABEL @PLT
 116     MO_PLT = 6,
 117
 118     /// MO_TLSGD - On a symbol operand this indicates that the immediate is
 119     /// some TLS offset.
 120     ///
 121     /// See 'ELF Handling for Thread-Local Storage' for more details.
 122     ///    SYMBOL_LABEL @TLSGD
 123     MO_TLSGD = 7,
 124
 125     /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
 126     /// some TLS offset.
 127     ///
 128     /// See 'ELF Handling for Thread-Local Storage' for more details.
 129     ///    SYMBOL_LABEL @GOTTPOFF
 130     MO_GOTTPOFF = 8,
 131
 132     /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
 133     /// some TLS offset.
 134     ///
 135     /// See 'ELF Handling for Thread-Local Storage' for more details.
 136     ///    SYMBOL_LABEL @INDNTPOFF
 137     MO_INDNTPOFF = 9,
 138
 139     /// MO_TPOFF - On a symbol operand this indicates that the immediate is
 140     /// some TLS offset.
 141     ///
 142     /// See 'ELF Handling for Thread-Local Storage' for more details.
 143     ///    SYMBOL_LABEL @TPOFF
 144     MO_TPOFF = 10,
 145
 146     /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
 147     /// some TLS offset.
 148     ///
 149     /// See 'ELF Handling for Thread-Local Storage' for more details.
 150     ///    SYMBOL_LABEL @NTPOFF
 151     MO_NTPOFF = 11,
 152
 153     /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
 154     /// reference is actually to the "__imp_FOO" symbol.  This is used for
 155     /// dllimport linkage on windows.
 156     MO_DLLIMPORT = 12,
 157
 158     /// MO_DARWIN_STUB - On a symbol operand "FOO", this indicates that the
 159     /// reference is actually to the "FOO$stub" symbol.  This is used for calls
 160     /// and jumps to external functions on Tiger and before.
 161     MO_DARWIN_STUB = 13,
 162
 163     /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
 164     /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
 165     /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 166     MO_DARWIN_NONLAZY = 14,
 167
 168     /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
 169     /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
 170     /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
 171     MO_DARWIN_NONLAZY_PIC_BASE = 15,
 172
 173     /// MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this
 174     /// indicates that the reference is actually to "FOO$non_lazy_ptr -PICBASE",
 175     /// which is a PIC-base-relative reference to a hidden dyld lazy pointer
 176     /// stub.
 177     MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE = 16
 178   };
 179 }
 180
 181 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
 182 /// a reference to a stub for a global, not the global itself.
 183 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
 184   switch (TargetFlag) {
 185   case X86II::MO_DLLIMPORT: // dllimport stub.
 186   case X86II::MO_GOTPCREL:  // rip-relative GOT reference.
 187   case X86II::MO_GOT:       // normal GOT reference.
 188   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Normal $non_lazy_ptr ref.
 189   case X86II::MO_DARWIN_NONLAZY:                 // Normal $non_lazy_ptr ref.
 190   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
 191     return true;
 192   default:
 193     return false;
 194   }
 195 }
 196
 197 /// isGlobalRelativeToPICBase - Return true if the specified global value
 198 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg).  If this
 199 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
 200 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
 201   switch (TargetFlag) {
 202   case X86II::MO_GOTOFF:                         // isPICStyleGOT: local global.
 203   case X86II::MO_GOT:                            // isPICStyleGOT: other global.
 204   case X86II::MO_PIC_BASE_OFFSET:                // Darwin local global.
 205   case X86II::MO_DARWIN_NONLAZY_PIC_BASE:        // Darwin/32 external global.
 206   case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
 207     return true;
 208   default:
 209     return false;
 210   }
 211 }
 212
 213 /// X86II - This namespace holds all of the target specific flags that
 214 /// instruction info tracks.
 215 ///
 216 namespace X86II {
 217   enum {
 218     //===------------------------------------------------------------------===//
 219     // Instruction encodings.  These are the standard/most common forms for X86
 220     // instructions.
 221     //
 222
 223     // PseudoFrm - This represents an instruction that is a pseudo instruction
 224     // or one that has not been implemented yet.  It is illegal to code generate
 225     // it, but tolerated for intermediate implementation stages.
 226     Pseudo         = 0,
 227
 228     /// Raw - This form is for instructions that don't have any operands, so
 229     /// they are just a fixed opcode value, like 'leave'.
 230     RawFrm         = 1,
 231
 232     /// AddRegFrm - This form is used for instructions like 'push r32' that have
 233     /// their one register operand added to their opcode.
 234     AddRegFrm      = 2,
 235
 236     /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
 237     /// to specify a destination, which in this case is a register.
 238     ///
 239     MRMDestReg     = 3,
 240
 241     /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
 242     /// to specify a destination, which in this case is memory.
 243     ///
 244     MRMDestMem     = 4,
 245
 246     /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
 247     /// to specify a source, which in this case is a register.
 248     ///
 249     MRMSrcReg      = 5,
 250
 251     /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
 252     /// to specify a source, which in this case is memory.
 253     ///
 254     MRMSrcMem      = 6,
 255
 256     /// MRM[0-7][rm] - These forms are used to represent instructions that use
 257     /// a Mod/RM byte, and use the middle field to hold extended opcode
 258     /// information.  In the intel manual these are represented as /0, /1, ...
 259     ///
 260
 261     // First, instructions that operate on a register r/m operand...
 262     MRM0r = 16,  MRM1r = 17,  MRM2r = 18,  MRM3r = 19, // Format /0 /1 /2 /3
 263     MRM4r = 20,  MRM5r = 21,  MRM6r = 22,  MRM7r = 23, // Format /4 /5 /6 /7
 264
 265     // Next, instructions that operate on a memory r/m operand...
 266     MRM0m = 24,  MRM1m = 25,  MRM2m = 26,  MRM3m = 27, // Format /0 /1 /2 /3
 267     MRM4m = 28,  MRM5m = 29,  MRM6m = 30,  MRM7m = 31, // Format /4 /5 /6 /7
 268
 269     // MRMInitReg - This form is used for instructions whose source and
 270     // destinations are the same register.
 271     MRMInitReg = 32,
 272
 273     FormMask       = 63,
 274
 275     //===------------------------------------------------------------------===//
 276     // Actual flags...
 277
 278     // OpSize - Set if this instruction requires an operand size prefix (0x66),
 279     // which most often indicates that the instruction operates on 16 bit data
 280     // instead of 32 bit data.
 281     OpSize      = 1 << 6,
 282
 283     // AsSize - Set if this instruction requires an operand size prefix (0x67),
 284     // which most often indicates that the instruction address 16 bit address
 285     // instead of 32 bit address (or 32 bit address in 64 bit mode).
 286     AdSize      = 1 << 7,
 287
 288     //===------------------------------------------------------------------===//
 289     // Op0Mask - There are several prefix bytes that are used to form two byte
 290     // opcodes.  These are currently 0x0F, 0xF3, and 0xD8-0xDF.  This mask is
 291     // used to obtain the setting of this field.  If no bits in this field is
 292     // set, there is no prefix byte for obtaining a multibyte opcode.
 293     //
 294     Op0Shift    = 8,
 295     Op0Mask     = 0xF << Op0Shift,
 296
 297     // TB - TwoByte - Set if this instruction has a two byte opcode, which
 298     // starts with a 0x0F byte before the real opcode.
 299     TB          = 1 << Op0Shift,
 300
 301     // REP - The 0xF3 prefix byte indicating repetition of the following
 302     // instruction.
 303     REP         = 2 << Op0Shift,
 304
 305     // D8-DF - These escape opcodes are used by the floating point unit.  These
 306     // values must remain sequential.
 307     D8 = 3 << Op0Shift,   D9 = 4 << Op0Shift,
 308     DA = 5 << Op0Shift,   DB = 6 << Op0Shift,
 309     DC = 7 << Op0Shift,   DD = 8 << Op0Shift,
 310     DE = 9 << Op0Shift,   DF = 10 << Op0Shift,
 311
 312     // XS, XD - These prefix codes are for single and double precision scalar
 313     // floating point operations performed in the SSE registers.
 314     XD = 11 << Op0Shift,  XS = 12 << Op0Shift,
 315
 316     // T8, TA - Prefix after the 0x0F prefix.
 317     T8 = 13 << Op0Shift,  TA = 14 << Op0Shift,
 318
 319     // TF - Prefix before and after 0x0F
 320     TF = 15 << Op0Shift,
 321
 322     //===------------------------------------------------------------------===//
 323     // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
 324     // They are used to specify GPRs and SSE registers, 64-bit operand size,
 325     // etc. We only cares about REX.W and REX.R bits and only the former is
 326     // statically determined.
 327     //
 328     REXShift    = 12,
 329     REX_W       = 1 << REXShift,
 330
 331     //===------------------------------------------------------------------===//
 332     // This three-bit field describes the size of an immediate operand.  Zero is
 333     // unused so that we can tell if we forgot to set a value.
 334     ImmShift = 13,
 335     ImmMask  = 7 << ImmShift,
 336     Imm8     = 1 << ImmShift,
 337     Imm16    = 2 << ImmShift,
 338     Imm32    = 3 << ImmShift,
 339     Imm64    = 4 << ImmShift,
 340
 341     //===------------------------------------------------------------------===//
 342     // FP Instruction Classification...  Zero is non-fp instruction.
 343
 344     // FPTypeMask - Mask for all of the FP types...
 345     FPTypeShift = 16,
 346     FPTypeMask  = 7 << FPTypeShift,
 347
 348     // NotFP - The default, set for instructions that do not use FP registers.
 349     NotFP      = 0 << FPTypeShift,
 350
 351     // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
 352     ZeroArgFP  = 1 << FPTypeShift,
 353
 354     // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
 355     OneArgFP   = 2 << FPTypeShift,
 356
 357     // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
 358     // result back to ST(0).  For example, fcos, fsqrt, etc.
 359     //
 360     OneArgFPRW = 3 << FPTypeShift,
 361
 362     // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
 363     // explicit argument, storing the result to either ST(0) or the implicit
 364     // argument.  For example: fadd, fsub, fmul, etc...
 365     TwoArgFP   = 4 << FPTypeShift,
 366
 367     // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
 368     // explicit argument, but have no destination.  Example: fucom, fucomi, ...
 369     CompareFP  = 5 << FPTypeShift,
 370
 371     // CondMovFP - "2 operand" floating point conditional move instructions.
 372     CondMovFP  = 6 << FPTypeShift,
 373
 374     // SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
 375     SpecialFP  = 7 << FPTypeShift,
 376
 377     // Lock prefix
 378     LOCKShift = 19,
 379     LOCK = 1 << LOCKShift,
 380
 381     // Segment override prefixes. Currently we just need ability to address
 382     // stuff in gs and fs segments.
 383     SegOvrShift = 20,
 384     SegOvrMask  = 3 << SegOvrShift,
 385     FS          = 1 << SegOvrShift,
 386     GS          = 2 << SegOvrShift,
 387
 388     // Bits 22 -> 23 are unused
 389     OpcodeShift   = 24,
 390     OpcodeMask    = 0xFF << OpcodeShift
 391   };
 392 }
 393
 394 const int X86AddrNumOperands = 5;
 395
 396 inline static bool isScale(const MachineOperand &MO) {
 397   return MO.isImm() &&
 398     (MO.getImm() == 1 || MO.getImm() == 2 ||
 399      MO.getImm() == 4 || MO.getImm() == 8);
 400 }
 401
 402 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
 403   if (MI->getOperand(Op).isFI()) return true;
 404   return Op+4 <= MI->getNumOperands() &&
 405     MI->getOperand(Op  ).isReg() && isScale(MI->getOperand(Op+1)) &&
 406     MI->getOperand(Op+2).isReg() &&
 407     (MI->getOperand(Op+3).isImm() ||
 408      MI->getOperand(Op+3).isGlobal() ||
 409      MI->getOperand(Op+3).isCPI() ||
 410      MI->getOperand(Op+3).isJTI());
 411 }
 412
 413 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
 414   if (MI->getOperand(Op).isFI()) return true;
 415   return Op+5 <= MI->getNumOperands() &&
 416     MI->getOperand(Op+4).isReg() &&
 417     isLeaMem(MI, Op);
 418 }
 419
 420 class X86InstrInfo : public TargetInstrInfoImpl {
 421   X86TargetMachine &TM;
 422   const X86RegisterInfo RI;
 423
 424   /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
 425   /// RegOp2MemOpTable2 - Load / store folding opcode maps.
 426   ///
 427   DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2Addr;
 428   DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable0;
 429   DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable1;
 430   DenseMap<unsigned*, std::pair<unsigned,unsigned> > RegOp2MemOpTable2;
 431
 432   /// MemOp2RegOpTable - Load / store unfolding opcode map.
 433   ///
 434   DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable;
 435
 436 public:
 437   explicit X86InstrInfo(X86TargetMachine &tm);
 438
 439   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 440   /// such, whenever a client has an instance of instruction info, it should
 441   /// always be able to get register info as well (through this method).
 442   ///
 443   virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
 444
 445   /// Return true if the instruction is a register to register move and return
 446   /// the source and dest operands and their sub-register indices by reference.
 447   virtual bool isMoveInstr(const MachineInstr &MI,
 448                            unsigned &SrcReg, unsigned &DstReg,
 449                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
 450
 451   unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
 452   unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
 453
 454   bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const;
 455   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 456                      unsigned DestReg, unsigned SubIdx,
 457                      const MachineInstr *Orig) const;
 458
 459   bool isInvariantLoad(const MachineInstr *MI) const;
 460
 461   /// convertToThreeAddress - This method must be implemented by targets that
 462   /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
 463   /// may be able to convert a two-address instruction into a true
 464   /// three-address instruction on demand.  This allows the X86 target (for
 465   /// example) to convert ADD and SHL instructions into LEA instructions if they
 466   /// would require register copies due to two-addressness.
 467   ///
 468   /// This method returns a null pointer if the transformation cannot be
 469   /// performed, otherwise it returns the new instruction.
 470   ///
 471   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
 472                                               MachineBasicBlock::iterator &MBBI,
 473                                               LiveVariables *LV) const;
 474
 475   /// commuteInstruction - We have a few instructions that must be hacked on to
 476   /// commute them.
 477   ///
 478   virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
 479
 480   // Branch analysis.
 481   virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
 482   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 483                              MachineBasicBlock *&FBB,
 484                              SmallVectorImpl<MachineOperand> &Cond,
 485                              bool AllowModify) const;
 486   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 487   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 488                                 MachineBasicBlock *FBB,
 489                             const SmallVectorImpl<MachineOperand> &Cond) const;
 490   virtual bool copyRegToReg(MachineBasicBlock &MBB,
 491                             MachineBasicBlock::iterator MI,
 492                             unsigned DestReg, unsigned SrcReg,
 493                             const TargetRegisterClass *DestRC,
 494                             const TargetRegisterClass *SrcRC) const;
 495   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 496                                    MachineBasicBlock::iterator MI,
 497                                    unsigned SrcReg, bool isKill, int FrameIndex,
 498                                    const TargetRegisterClass *RC) const;
 499
 500   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
 501                               SmallVectorImpl<MachineOperand> &Addr,
 502                               const TargetRegisterClass *RC,
 503                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
 504
 505   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 506                                     MachineBasicBlock::iterator MI,
 507                                     unsigned DestReg, int FrameIndex,
 508                                     const TargetRegisterClass *RC) const;
 509
 510   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 511                                SmallVectorImpl<MachineOperand> &Addr,
 512                                const TargetRegisterClass *RC,
 513                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
 514
 515   virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
 516                                          MachineBasicBlock::iterator MI,
 517                                  const std::vector<CalleeSavedInfo> &CSI) const;
 518
 519   virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
 520                                            MachineBasicBlock::iterator MI,
 521                                  const std::vector<CalleeSavedInfo> &CSI) const;
 522
 523   /// foldMemoryOperand - If this target supports it, fold a load or store of
 524   /// the specified stack slot into the specified machine instruction for the
 525   /// specified operand(s).  If this is possible, the target should perform the
 526   /// folding and return true, otherwise it should return false.  If it folds
 527   /// the instruction, it is likely that the MachineInstruction the iterator
 528   /// references has been changed.
 529   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 530                                               MachineInstr* MI,
 531                                            const SmallVectorImpl<unsigned> &Ops,
 532                                               int FrameIndex) const;
 533
 534   /// foldMemoryOperand - Same as the previous version except it allows folding
 535   /// of any load and store from / to any address, not just from a specific
 536   /// stack slot.
 537   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 538                                               MachineInstr* MI,
 539                                            const SmallVectorImpl<unsigned> &Ops,
 540                                               MachineInstr* LoadMI) const;
 541
 542   /// canFoldMemoryOperand - Returns true if the specified load / store is
 543   /// folding is possible.
 544   virtual bool canFoldMemoryOperand(const MachineInstr*,
 545                                     const SmallVectorImpl<unsigned> &) const;
 546
 547   /// unfoldMemoryOperand - Separate a single instruction which folded a load or
 548   /// a store or a load and a store into two or more instruction. If this is
 549   /// possible, returns true as well as the new instructions by reference.
 550   virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
 551                            unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
 552                            SmallVectorImpl<MachineInstr*> &NewMIs) const;
 553
 554   virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
 555                            SmallVectorImpl<SDNode*> &NewNodes) const;
 556
 557   /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
 558   /// instruction after load / store are unfolded from an instruction of the
 559   /// specified opcode. It returns zero if the specified unfolding is not
 560   /// possible.
 561   virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
 562                                       bool UnfoldLoad, bool UnfoldStore) const;
 563
 564   virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
 565   virtual
 566   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 567
 568   /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
 569   /// instruction that defines the specified register class.
 570   bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
 571
 572   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
 573   // specified machine instruction.
 574   //
 575   unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
 576     return TID->TSFlags >> X86II::OpcodeShift;
 577   }
 578   unsigned char getBaseOpcodeFor(unsigned Opcode) const {
 579     return getBaseOpcodeFor(&get(Opcode));
 580   }
 581
 582   static bool isX86_64NonExtLowByteReg(unsigned reg) {
 583     return (reg == X86::SPL || reg == X86::BPL ||
 584           reg == X86::SIL || reg == X86::DIL);
 585   }
 586
 587   static unsigned sizeOfImm(const TargetInstrDesc *Desc);
 588   static bool isX86_64ExtendedReg(const MachineOperand &MO);
 589   static unsigned determineREX(const MachineInstr &MI);
 590
 591   /// GetInstSize - Returns the size of the specified MachineInstr.
 592   ///
 593   virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
 594
 595   /// getGlobalBaseReg - Return a virtual register initialized with the
 596   /// the global base register value. Output instructions required to
 597   /// initialize the register in the function entry block, if necessary.
 598   ///
 599   unsigned getGlobalBaseReg(MachineFunction *MF) const;
 600
 601 private:
 602   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 603                                      MachineInstr* MI,
 604                                      unsigned OpNum,
 605                                      const SmallVectorImpl<MachineOperand> &MOs,
 606                                      unsigned Size, unsigned Alignment) const;
 607 };
 608
 609 } // End llvm namespace
 610
 611 #endif