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remove all but one reference to TargetRegisterDesc::AsmName.
[llvm/avr.git] / lib / Target / SystemZ / SystemZISelLowering.cpp
blobc965878ddf5fc1166455adc686a07022b4639c57
1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SystemZTargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #define DEBUG_TYPE "systemz-lower"
15
16 #include "SystemZISelLowering.h"
17 #include "SystemZ.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/VectorExtras.h"
39 using namespace llvm;
40
41 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
42 TargetLowering(tm, new TargetLoweringObjectFileELF()),
43 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
44
45 RegInfo = TM.getRegisterInfo();
46
47 // Set up the register classes.
48 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
49 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
50 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
51 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
52
53 if (!UseSoftFloat) {
54 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
55 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
56
57 addLegalFPImmediate(APFloat(+0.0)); // lzer
58 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
59 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
60 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
61 }
62
63 // Compute derived properties from the register classes
64 computeRegisterProperties();
65
66 // Set shifts properties
67 setShiftAmountType(MVT::i64);
68
69 // Provide all sorts of operation actions
70 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
71 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
72 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
73
74 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
75 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
76 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
77
78 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
79 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
80 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
81
82 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
83 setSchedulingPreference(SchedulingForLatency);
84 setBooleanContents(ZeroOrOneBooleanContent);
85
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
91 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
93 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
94 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
95 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
96 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
97
98 setOperationAction(ISD::SDIV, MVT::i32, Expand);
99 setOperationAction(ISD::UDIV, MVT::i32, Expand);
100 setOperationAction(ISD::SDIV, MVT::i64, Expand);
101 setOperationAction(ISD::UDIV, MVT::i64, Expand);
102 setOperationAction(ISD::SREM, MVT::i32, Expand);
103 setOperationAction(ISD::UREM, MVT::i32, Expand);
104 setOperationAction(ISD::SREM, MVT::i64, Expand);
105 setOperationAction(ISD::UREM, MVT::i64, Expand);
106
107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
108
109 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
110 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
111 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
112 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
113 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
114 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
115
116 // FIXME: Can we lower these 2 efficiently?
117 setOperationAction(ISD::SETCC, MVT::i32, Expand);
118 setOperationAction(ISD::SETCC, MVT::i64, Expand);
119 setOperationAction(ISD::SETCC, MVT::f32, Expand);
120 setOperationAction(ISD::SETCC, MVT::f64, Expand);
121 setOperationAction(ISD::SELECT, MVT::i32, Expand);
122 setOperationAction(ISD::SELECT, MVT::i64, Expand);
123 setOperationAction(ISD::SELECT, MVT::f32, Expand);
124 setOperationAction(ISD::SELECT, MVT::f64, Expand);
125 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
128 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
129
130 setOperationAction(ISD::MULHS, MVT::i64, Expand);
131 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
132
133 // FIXME: Can we support these natively?
134 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
135 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
136 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
137 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
138
139 // Lower some FP stuff
140 setOperationAction(ISD::FSIN, MVT::f32, Expand);
141 setOperationAction(ISD::FSIN, MVT::f64, Expand);
142 setOperationAction(ISD::FCOS, MVT::f32, Expand);
143 setOperationAction(ISD::FCOS, MVT::f64, Expand);
144 setOperationAction(ISD::FREM, MVT::f32, Expand);
145 setOperationAction(ISD::FREM, MVT::f64, Expand);
146
147 // We have only 64-bit bitconverts
148 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
149 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
150
151 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
152 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
153 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
154 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
155
156 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
157 }
158
159 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
160 switch (Op.getOpcode()) {
161 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
162 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
163 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
164 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
165 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
166 default:
167 llvm_unreachable("Should not custom lower this!");
168 return SDValue();
169 }
170 }
171
172 //===----------------------------------------------------------------------===//
173 // SystemZ Inline Assembly Support
174 //===----------------------------------------------------------------------===//
175
176 /// getConstraintType - Given a constraint letter, return the type of
177 /// constraint it is for this target.
178 TargetLowering::ConstraintType
179 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
180 if (Constraint.size() == 1) {
181 switch (Constraint[0]) {
182 case 'r':
183 return C_RegisterClass;
184 default:
185 break;
186 }
187 }
188 return TargetLowering::getConstraintType(Constraint);
189 }
190
191 std::pair<unsigned, const TargetRegisterClass*>
192 SystemZTargetLowering::
193 getRegForInlineAsmConstraint(const std::string &Constraint,
194 EVT VT) const {
195 if (Constraint.size() == 1) {
196 // GCC Constraint Letters
197 switch (Constraint[0]) {
198 default: break;
199 case 'r': // GENERAL_REGS
200 if (VT == MVT::i32)
201 return std::make_pair(0U, SystemZ::GR32RegisterClass);
202 else if (VT == MVT::i128)
203 return std::make_pair(0U, SystemZ::GR128RegisterClass);
204
205 return std::make_pair(0U, SystemZ::GR64RegisterClass);
206 }
207 }
208
209 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
210 }
211
212 //===----------------------------------------------------------------------===//
213 // Calling Convention Implementation
214 //===----------------------------------------------------------------------===//
215
216 #include "SystemZGenCallingConv.inc"
217
218 SDValue
219 SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
220 CallingConv::ID CallConv,
221 bool isVarArg,
222 const SmallVectorImpl<ISD::InputArg>
223 &Ins,
224 DebugLoc dl,
225 SelectionDAG &DAG,
226 SmallVectorImpl<SDValue> &InVals) {
227
228 switch (CallConv) {
229 default:
230 llvm_unreachable("Unsupported calling convention");
231 case CallingConv::C:
232 case CallingConv::Fast:
233 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
234 }
235 }
236
237 SDValue
238 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
239 CallingConv::ID CallConv, bool isVarArg,
240 bool isTailCall,
241 const SmallVectorImpl<ISD::OutputArg> &Outs,
242 const SmallVectorImpl<ISD::InputArg> &Ins,
243 DebugLoc dl, SelectionDAG &DAG,
244 SmallVectorImpl<SDValue> &InVals) {
245
246 switch (CallConv) {
247 default:
248 llvm_unreachable("Unsupported calling convention");
249 case CallingConv::Fast:
250 case CallingConv::C:
251 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
252 Outs, Ins, dl, DAG, InVals);
253 }
254 }
255
256 /// LowerCCCArguments - transform physical registers into virtual registers and
257 /// generate load operations for arguments places on the stack.
258 // FIXME: struct return stuff
259 // FIXME: varargs
260 SDValue
261 SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
262 CallingConv::ID CallConv,
263 bool isVarArg,
264 const SmallVectorImpl<ISD::InputArg>
265 &Ins,
266 DebugLoc dl,
267 SelectionDAG &DAG,
268 SmallVectorImpl<SDValue> &InVals) {
269
270 MachineFunction &MF = DAG.getMachineFunction();
271 MachineFrameInfo *MFI = MF.getFrameInfo();
272 MachineRegisterInfo &RegInfo = MF.getRegInfo();
273
274 // Assign locations to all of the incoming arguments.
275 SmallVector<CCValAssign, 16> ArgLocs;
276 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
277 ArgLocs, *DAG.getContext());
278 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
279
280 if (isVarArg)
281 llvm_report_error("Varargs not supported yet");
282
283 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
284 SDValue ArgValue;
285 CCValAssign &VA = ArgLocs[i];
286 EVT LocVT = VA.getLocVT();
287 if (VA.isRegLoc()) {
288 // Arguments passed in registers
289 TargetRegisterClass *RC;
290 switch (LocVT.getSimpleVT().SimpleTy) {
291 default:
292 #ifndef NDEBUG
293 errs() << "LowerFormalArguments Unhandled argument type: "
294 << LocVT.getSimpleVT().SimpleTy
295 << "\n";
296 #endif
297 llvm_unreachable(0);
298 case MVT::i64:
299 RC = SystemZ::GR64RegisterClass;
300 break;
301 case MVT::f32:
302 RC = SystemZ::FP32RegisterClass;
303 break;
304 case MVT::f64:
305 RC = SystemZ::FP64RegisterClass;
306 break;
307 }
308
309 unsigned VReg = RegInfo.createVirtualRegister(RC);
310 RegInfo.addLiveIn(VA.getLocReg(), VReg);
311 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
312 } else {
313 // Sanity check
314 assert(VA.isMemLoc());
315
316 // Create the nodes corresponding to a load from this parameter slot.
317 // Create the frame index object for this incoming parameter...
318 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
319 VA.getLocMemOffset());
320
321 // Create the SelectionDAG nodes corresponding to a load
322 // from this parameter
323 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
324 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
325 PseudoSourceValue::getFixedStack(FI), 0);
326 }
327
328 // If this is an 8/16/32-bit value, it is really passed promoted to 64
329 // bits. Insert an assert[sz]ext to capture this, then truncate to the
330 // right size.
331 if (VA.getLocInfo() == CCValAssign::SExt)
332 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
333 DAG.getValueType(VA.getValVT()));
334 else if (VA.getLocInfo() == CCValAssign::ZExt)
335 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
336 DAG.getValueType(VA.getValVT()));
337
338 if (VA.getLocInfo() != CCValAssign::Full)
339 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
340
341 InVals.push_back(ArgValue);
342 }
343
344 return Chain;
345 }
346
347 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
348 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
349 /// TODO: sret.
350 SDValue
351 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
352 CallingConv::ID CallConv, bool isVarArg,
353 bool isTailCall,
354 const SmallVectorImpl<ISD::OutputArg>
355 &Outs,
356 const SmallVectorImpl<ISD::InputArg> &Ins,
357 DebugLoc dl, SelectionDAG &DAG,
358 SmallVectorImpl<SDValue> &InVals) {
359
360 MachineFunction &MF = DAG.getMachineFunction();
361
362 // Offset to first argument stack slot.
363 const unsigned FirstArgOffset = 160;
364
365 // Analyze operands of the call, assigning locations to each operand.
366 SmallVector<CCValAssign, 16> ArgLocs;
367 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
368 ArgLocs, *DAG.getContext());
369
370 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
371
372 // Get a count of how many bytes are to be pushed on the stack.
373 unsigned NumBytes = CCInfo.getNextStackOffset();
374
375 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
376 getPointerTy(), true));
377
378 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
379 SmallVector<SDValue, 12> MemOpChains;
380 SDValue StackPtr;
381
382 // Walk the register/memloc assignments, inserting copies/loads.
383 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
384 CCValAssign &VA = ArgLocs[i];
385
386 SDValue Arg = Outs[i].Val;
387
388 // Promote the value if needed.
389 switch (VA.getLocInfo()) {
390 default: assert(0 && "Unknown loc info!");
391 case CCValAssign::Full: break;
392 case CCValAssign::SExt:
393 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
394 break;
395 case CCValAssign::ZExt:
396 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
397 break;
398 case CCValAssign::AExt:
399 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
400 break;
401 }
402
403 // Arguments that can be passed on register must be kept at RegsToPass
404 // vector
405 if (VA.isRegLoc()) {
406 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
407 } else {
408 assert(VA.isMemLoc());
409
410 if (StackPtr.getNode() == 0)
411 StackPtr =
412 DAG.getCopyFromReg(Chain, dl,
413 (RegInfo->hasFP(MF) ?
414 SystemZ::R11D : SystemZ::R15D),
415 getPointerTy());
416
417 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
418 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
419 StackPtr,
420 DAG.getIntPtrConstant(Offset));
421
422 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
423 PseudoSourceValue::getStack(), Offset));
424 }
425 }
426
427 // Transform all store nodes into one single node because all store nodes are
428 // independent of each other.
429 if (!MemOpChains.empty())
430 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
431 &MemOpChains[0], MemOpChains.size());
432
433 // Build a sequence of copy-to-reg nodes chained together with token chain and
434 // flag operands which copy the outgoing args into registers. The InFlag in
435 // necessary since all emited instructions must be stuck together.
436 SDValue InFlag;
437 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
438 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
439 RegsToPass[i].second, InFlag);
440 InFlag = Chain.getValue(1);
441 }
442
443 // If the callee is a GlobalAddress node (quite common, every direct call is)
444 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
445 // Likewise ExternalSymbol -> TargetExternalSymbol.
446 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
447 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
448 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
449 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
450
451 // Returns a chain & a flag for retval copy to use.
452 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
453 SmallVector<SDValue, 8> Ops;
454 Ops.push_back(Chain);
455 Ops.push_back(Callee);
456
457 // Add argument registers to the end of the list so that they are
458 // known live into the call.
459 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
460 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
461 RegsToPass[i].second.getValueType()));
462
463 if (InFlag.getNode())
464 Ops.push_back(InFlag);
465
466 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
467 InFlag = Chain.getValue(1);
468
469 // Create the CALLSEQ_END node.
470 Chain = DAG.getCALLSEQ_END(Chain,
471 DAG.getConstant(NumBytes, getPointerTy(), true),
472 DAG.getConstant(0, getPointerTy(), true),
473 InFlag);
474 InFlag = Chain.getValue(1);
475
476 // Handle result values, copying them out of physregs into vregs that we
477 // return.
478 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
479 DAG, InVals);
480 }
481
482 /// LowerCallResult - Lower the result values of a call into the
483 /// appropriate copies out of appropriate physical registers.
484 ///
485 SDValue
486 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
487 CallingConv::ID CallConv, bool isVarArg,
488 const SmallVectorImpl<ISD::InputArg>
489 &Ins,
490 DebugLoc dl, SelectionDAG &DAG,
491 SmallVectorImpl<SDValue> &InVals) {
492
493 // Assign locations to each value returned by this call.
494 SmallVector<CCValAssign, 16> RVLocs;
495 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
496 *DAG.getContext());
497
498 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
499
500 // Copy all of the result registers out of their specified physreg.
501 for (unsigned i = 0; i != RVLocs.size(); ++i) {
502 CCValAssign &VA = RVLocs[i];
503
504 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
505 VA.getLocVT(), InFlag).getValue(1);
506 SDValue RetValue = Chain.getValue(0);
507 InFlag = Chain.getValue(2);
508
509 // If this is an 8/16/32-bit value, it is really passed promoted to 64
510 // bits. Insert an assert[sz]ext to capture this, then truncate to the
511 // right size.
512 if (VA.getLocInfo() == CCValAssign::SExt)
513 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
514 DAG.getValueType(VA.getValVT()));
515 else if (VA.getLocInfo() == CCValAssign::ZExt)
516 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
517 DAG.getValueType(VA.getValVT()));
518
519 if (VA.getLocInfo() != CCValAssign::Full)
520 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
521
522 InVals.push_back(RetValue);
523 }
524
525 return Chain;
526 }
527
528
529 SDValue
530 SystemZTargetLowering::LowerReturn(SDValue Chain,
531 CallingConv::ID CallConv, bool isVarArg,
532 const SmallVectorImpl<ISD::OutputArg> &Outs,
533 DebugLoc dl, SelectionDAG &DAG) {
534
535 // CCValAssign - represent the assignment of the return value to a location
536 SmallVector<CCValAssign, 16> RVLocs;
537
538 // CCState - Info about the registers and stack slot.
539 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
540 RVLocs, *DAG.getContext());
541
542 // Analize return values.
543 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
544
545 // If this is the first return lowered for this function, add the regs to the
546 // liveout set for the function.
547 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
548 for (unsigned i = 0; i != RVLocs.size(); ++i)
549 if (RVLocs[i].isRegLoc())
550 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
551 }
552
553 SDValue Flag;
554
555 // Copy the result values into the output registers.
556 for (unsigned i = 0; i != RVLocs.size(); ++i) {
557 CCValAssign &VA = RVLocs[i];
558 SDValue ResValue = Outs[i].Val;
559 assert(VA.isRegLoc() && "Can only return in registers!");
560
561 // If this is an 8/16/32-bit value, it is really should be passed promoted
562 // to 64 bits.
563 if (VA.getLocInfo() == CCValAssign::SExt)
564 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
565 else if (VA.getLocInfo() == CCValAssign::ZExt)
566 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
567 else if (VA.getLocInfo() == CCValAssign::AExt)
568 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
569
570 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
571
572 // Guarantee that all emitted copies are stuck together,
573 // avoiding something bad.
574 Flag = Chain.getValue(1);
575 }
576
577 if (Flag.getNode())
578 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
579
580 // Return Void
581 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
582 }
583
584 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
585 ISD::CondCode CC, SDValue &SystemZCC,
586 SelectionDAG &DAG) {
587 // FIXME: Emit a test if RHS is zero
588
589 bool isUnsigned = false;
590 SystemZCC::CondCodes TCC;
591 switch (CC) {
592 default:
593 llvm_unreachable("Invalid integer condition!");
594 case ISD::SETEQ:
595 case ISD::SETOEQ:
596 TCC = SystemZCC::E;
597 break;
598 case ISD::SETUEQ:
599 TCC = SystemZCC::NLH;
600 break;
601 case ISD::SETNE:
602 case ISD::SETONE:
603 TCC = SystemZCC::NE;
604 break;
605 case ISD::SETUNE:
606 TCC = SystemZCC::LH;
607 break;
608 case ISD::SETO:
609 TCC = SystemZCC::O;
610 break;
611 case ISD::SETUO:
612 TCC = SystemZCC::NO;
613 break;
614 case ISD::SETULE:
615 if (LHS.getValueType().isFloatingPoint()) {
616 TCC = SystemZCC::NH;
617 break;
618 }
619 isUnsigned = true; // FALLTHROUGH
620 case ISD::SETLE:
621 case ISD::SETOLE:
622 TCC = SystemZCC::LE;
623 break;
624 case ISD::SETUGE:
625 if (LHS.getValueType().isFloatingPoint()) {
626 TCC = SystemZCC::NL;
627 break;
628 }
629 isUnsigned = true; // FALLTHROUGH
630 case ISD::SETGE:
631 case ISD::SETOGE:
632 TCC = SystemZCC::HE;
633 break;
634 case ISD::SETUGT:
635 if (LHS.getValueType().isFloatingPoint()) {
636 TCC = SystemZCC::NLE;
637 break;
638 }
639 isUnsigned = true; // FALLTHROUGH
640 case ISD::SETGT:
641 case ISD::SETOGT:
642 TCC = SystemZCC::H;
643 break;
644 case ISD::SETULT:
645 if (LHS.getValueType().isFloatingPoint()) {
646 TCC = SystemZCC::NHE;
647 break;
648 }
649 isUnsigned = true; // FALLTHROUGH
650 case ISD::SETLT:
651 case ISD::SETOLT:
652 TCC = SystemZCC::L;
653 break;
654 }
655
656 SystemZCC = DAG.getConstant(TCC, MVT::i32);
657
658 DebugLoc dl = LHS.getDebugLoc();
659 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
660 dl, MVT::Flag, LHS, RHS);
661 }
662
663
664 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
665 SDValue Chain = Op.getOperand(0);
666 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
667 SDValue LHS = Op.getOperand(2);
668 SDValue RHS = Op.getOperand(3);
669 SDValue Dest = Op.getOperand(4);
670 DebugLoc dl = Op.getDebugLoc();
671
672 SDValue SystemZCC;
673 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
674 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
675 Chain, Dest, SystemZCC, Flag);
676 }
677
678 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
679 SDValue LHS = Op.getOperand(0);
680 SDValue RHS = Op.getOperand(1);
681 SDValue TrueV = Op.getOperand(2);
682 SDValue FalseV = Op.getOperand(3);
683 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
684 DebugLoc dl = Op.getDebugLoc();
685
686 SDValue SystemZCC;
687 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
688
689 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
690 SmallVector<SDValue, 4> Ops;
691 Ops.push_back(TrueV);
692 Ops.push_back(FalseV);
693 Ops.push_back(SystemZCC);
694 Ops.push_back(Flag);
695
696 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
697 }
698
699 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
700 SelectionDAG &DAG) {
701 DebugLoc dl = Op.getDebugLoc();
702 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
703 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
704
705 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
706 bool ExtraLoadRequired =
707 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
708
709 SDValue Result;
710 if (!IsPic && !ExtraLoadRequired) {
711 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
712 Offset = 0;
713 } else {
714 unsigned char OpFlags = 0;
715 if (ExtraLoadRequired)
716 OpFlags = SystemZII::MO_GOTENT;
717
718 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
719 }
720
721 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
722 getPointerTy(), Result);
723
724 if (ExtraLoadRequired)
725 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
726 PseudoSourceValue::getGOT(), 0);
727
728 // If there was a non-zero offset that we didn't fold, create an explicit
729 // addition for it.
730 if (Offset != 0)
731 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
732 DAG.getConstant(Offset, getPointerTy()));
733
734 return Result;
735 }
736
737 // FIXME: PIC here
738 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
739 SelectionDAG &DAG) {
740 DebugLoc dl = Op.getDebugLoc();
741 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
742 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
743
744 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
745 }
746
747
748 // FIXME: PIC here
749 // FIXME: This is just dirty hack. We need to lower cpool properly
750 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
751 SelectionDAG &DAG) {
752 DebugLoc dl = Op.getDebugLoc();
753 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
754
755 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
756 CP->getAlignment(),
757 CP->getOffset());
758
759 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
760 }
761
762 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
763 switch (Opcode) {
764 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
765 case SystemZISD::CALL: return "SystemZISD::CALL";
766 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
767 case SystemZISD::CMP: return "SystemZISD::CMP";
768 case SystemZISD::UCMP: return "SystemZISD::UCMP";
769 case SystemZISD::SELECT: return "SystemZISD::SELECT";
770 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
771 default: return NULL;
772 }
773 }
774
775 //===----------------------------------------------------------------------===//
776 // Other Lowering Code
777 //===----------------------------------------------------------------------===//
778
779 MachineBasicBlock*
780 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
781 MachineBasicBlock *BB) const {
782 const SystemZInstrInfo &TII = *TM.getInstrInfo();
783 DebugLoc dl = MI->getDebugLoc();
784 assert((MI->getOpcode() == SystemZ::Select32 ||
785 MI->getOpcode() == SystemZ::SelectF32 ||
786 MI->getOpcode() == SystemZ::Select64 ||
787 MI->getOpcode() == SystemZ::SelectF64) &&
788 "Unexpected instr type to insert");
789
790 // To "insert" a SELECT instruction, we actually have to insert the diamond
791 // control-flow pattern. The incoming instruction knows the destination vreg
792 // to set, the condition code register to branch on, the true/false values to
793 // select between, and a branch opcode to use.
794 const BasicBlock *LLVM_BB = BB->getBasicBlock();
795 MachineFunction::iterator I = BB;
796 ++I;
797
798 // thisMBB:
799 // ...
800 // TrueVal = ...
801 // cmpTY ccX, r1, r2
802 // jCC copy1MBB
803 // fallthrough --> copy0MBB
804 MachineBasicBlock *thisMBB = BB;
805 MachineFunction *F = BB->getParent();
806 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
807 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
808 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
809 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
810 F->insert(I, copy0MBB);
811 F->insert(I, copy1MBB);
812 // Update machine-CFG edges by transferring all successors of the current
813 // block to the new block which will contain the Phi node for the select.
814 copy1MBB->transferSuccessors(BB);
815 // Next, add the true and fallthrough blocks as its successors.
816 BB->addSuccessor(copy0MBB);
817 BB->addSuccessor(copy1MBB);
818
819 // copy0MBB:
820 // %FalseValue = ...
821 // # fallthrough to copy1MBB
822 BB = copy0MBB;
823
824 // Update machine-CFG edges
825 BB->addSuccessor(copy1MBB);
826
827 // copy1MBB:
828 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
829 // ...
830 BB = copy1MBB;
831 BuildMI(BB, dl, TII.get(SystemZ::PHI),
832 MI->getOperand(0).getReg())
833 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
834 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
835
836 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
837 return BB;
838 }
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