| blob | 2471e9d20cc495d84b53ecc88b51d1ddea60daea |
3 <html>
4 <head>
8 </head>
9 <body>
12 The LLVM Target-Independent Code Generator
13 </div>
15 <ol>
17 <ul>
20 generator</a></li>
22 </ul>
23 </li>
25 <ul>
34 </ul>
35 </li>
37 <ul>
40 class</a></li>
42 </ul>
43 </li>
45 <ul>
47 <ul>
50 Process</a></li>
52 Construction</a></li>
56 Phase: the DAG Combiner</a></li>
59 Phase</a></li>
61 SelectionDAG</a></li>
62 </ul></li>
64 <ul>
67 </ul></li>
69 <ul>
71 LLVM</a></li>
73 registers</a></li>
78 </ul></li>
80 <ul>
83 </ul></li>
84 </ul>
85 </li>
87 <ul>
91 <ul>
96 </ul></li>
97 </ul></li>
99 </ol>
105 Pereira</a> and
107 </div>
111 </div>
113 <!-- *********************************************************************** -->
116 </div>
117 <!-- *********************************************************************** -->
121 <p>The LLVM target-independent code generator is a framework that provides a
122 suite of reusable components for translating the LLVM internal representation
123 to the machine code for a specified target—either in assembly form
124 (suitable for a static compiler) or in binary machine code format (usable for
125 a JIT compiler). The LLVM target-independent code generator consists of five
126 main components:</p>
128 <ol>
130 capture important properties about various aspects of the machine,
131 independently of how they will be used. These interfaces are defined in
135 being generated for a target. These classes are intended to be abstract
140 various phases of native code generation (register allocation, scheduling,
141 stack frame representation, etc). This code lives
145 interfaces</a> for particular targets. These machine descriptions make
146 use of the components provided by LLVM, and can optionally provide custom
147 target-specific passes, to build complete code generators for a specific
152 structure to interface for target-specific issues. The code for the
154 </ol>
156 <p>Depending on which part of the code generator you are interested in working
157 on, different pieces of this will be useful to you. In any case, you should
160 want to add a backend for a new target, you will need
163 representation</a>. If you are interested in implementing a
165 depend on the target-description and machine code representation classes,
166 ensuring that it is portable.</p>
168 </div>
170 <!-- ======================================================================= -->
173 </div>
177 <p>The two pieces of the LLVM code generator are the high-level interface to the
178 code generator and the set of reusable components that can be used to build
179 target-specific backends. The two most important interfaces
182 required to be defined for a backend to fit into the LLVM system, but the
183 others must be defined if the reusable code generator components are going to
184 be used.</p>
186 <p>This design has two important implications. The first is that LLVM can
187 support completely non-traditional code generation targets. For example, the
188 C backend does not require register allocation, instruction selection, or any
189 of the other standard components provided by the system. As such, it only
190 implements these two interfaces, and does its own thing. Another example of
191 a code generator like this is a (purely hypothetical) backend that converts
192 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
194 <p>This design also implies that it is possible to design and implement
195 radically different code generators in the LLVM system that do not make use
196 of any of the built-in components. Doing so is not recommended at all, but
197 could be required for radically different targets that do not fit into the
198 LLVM machine description model: FPGAs for example.</p>
200 </div>
202 <!-- ======================================================================= -->
205 </div>
209 <p>The LLVM target-independent code generator is designed to support efficient
210 and quality code generation for standard register-based microprocessors.
211 Code generation in this model is divided into the following stages:</p>
213 <ol>
215 determines an efficient way to express the input LLVM code in the target
216 instruction set. This stage produces the initial code for the program in
217 the target instruction set, then makes use of virtual registers in SSA
218 form and physical registers that represent any required register
219 assignments due to target constraints or calling conventions. This step
220 turns the LLVM code into a DAG of target instructions.</li>
223 This phase takes the DAG of target instructions produced by the
224 instruction selection phase, determines an ordering of the instructions,
225 then emits the instructions
228 selection section</a> because it operates on
232 This optional stage consists of a series of machine-code optimizations
233 that operate on the SSA-form produced by the instruction selector.
234 Optimizations like modulo-scheduling or peephole optimization work
235 here.</li>
238 is transformed from an infinite virtual register file in SSA form to the
239 concrete register file used by the target. This phase introduces spill
240 code and eliminates all virtual register references from the program.</li>
243 the machine code has been generated for the function and the amount of
244 stack space required is known (used for LLVM alloca's and spill slots),
245 the prolog and epilog code for the function can be inserted and "abstract
246 stack location references" can be eliminated. This stage is responsible
247 for implementing optimizations like frame-pointer elimination and stack
248 packing.</li>
251 Optimizations that operate on "final" machine code can go here, such as
252 spill code scheduling and peephole optimizations.</li>
255 actually puts out the code for the current function, either in the target
256 assembler format or in machine code.</li>
257 </ol>
259 <p>The code generator is based on the assumption that the instruction selector
260 will use an optimal pattern matching selector to create high-quality
261 sequences of native instructions. Alternative code generator designs based
262 on pattern expansion and aggressive iterative peephole optimization are much
263 slower. This design permits efficient compilation (important for JIT
264 environments) and aggressive optimization (used when generating code offline)
265 by allowing components of varying levels of sophistication to be used for any
266 step of compilation.</p>
268 <p>In addition to these stages, target implementations can insert arbitrary
269 target-specific passes into the flow. For example, the X86 target uses a
270 special pass to handle the 80x87 floating point stack architecture. Other
271 targets with unusual requirements can be supported with custom passes as
272 needed.</p>
274 </div>
276 <!-- ======================================================================= -->
279 </div>
283 <p>The target description classes require a detailed description of the target
284 architecture. These target descriptions often have a large amount of common
287 commonality to be factored out, the LLVM code generator uses
289 chunks of the target machine, which allows the use of domain-specific and
290 target-specific abstractions to reduce the amount of repetition.</p>
292 <p>As LLVM continues to be developed and refined, we plan to move more and more
294 number of advantages. The most important is that it makes it easier to port
295 LLVM because it reduces the amount of C++ code that has to be written, and
296 the surface area of the code generator that needs to be understood before
297 someone can get something working. Second, it makes it easier to change
298 things. In particular, if tables and other things are all emitted
300 update all of the targets to a new interface.</p>
302 </div>
304 <!-- *********************************************************************** -->
307 </div>
308 <!-- *********************************************************************** -->
312 <p>The LLVM target description classes (located in the
314 the target machine independent of any particular client. These classes are
316 instructions and registers it has), and do not incorporate any particular
317 pieces of code generation algorithms.</p>
319 <p>All of the target description classes (except the
321 subclassed by the concrete target implementation, and have virtual methods
322 implemented. To get to these implementations, the
324 that should be implemented by the target.</p>
326 </div>
328 <!-- ======================================================================= -->
331 </div>
336 access the target-specific implementations of the various target description
339 designed to be specialized by a concrete target implementation
341 methods. The only required target description class is
343 generator components are to be used, the other interfaces should be
344 implemented as well.</p>
346 </div>
348 <!-- ======================================================================= -->
351 </div>
356 and it is the only class that is not extensible (you cannot derived a new
358 target lays out memory for structures, the alignment requirements for various
359 data types, the size of pointers in the target, and whether the target is
360 little-endian or big-endian.</p>
362 </div>
364 <!-- ======================================================================= -->
367 </div>
372 selectors primarily to describe how LLVM code should be lowered to
373 SelectionDAG operations. Among other things, this class indicates:</p>
375 <ul>
384 <li>various high-level characteristics, like whether it is profitable to turn
385 division by a constant into a multiplication sequence</li>
386 </ul>
388 </div>
390 <!-- ======================================================================= -->
393 </div>
398 of the target and any interactions between the registers.</p>
400 <p>Registers in the code generator are represented in the code generator by
401 unsigned integers. Physical registers (those that actually exist in the
402 target description) are unique small numbers, and virtual registers are
405 <p>Each register in the processor description has an associated
407 register (used for assembly output and debugging dumps) and a set of aliases
408 (used to indicate whether one register overlaps with another).</p>
411 class exposes a set of processor specific register classes (instances of the
413 registers that have the same properties (for example, they are all 32-bit
414 integer registers). Each SSA virtual register created by the instruction
415 selector has an associated register class. When the register allocator runs,
416 it replaces virtual registers with a physical register in the set.</p>
418 <p>The target-specific implementations of these classes is auto-generated from
420 register file.</p>
422 </div>
424 <!-- ======================================================================= -->
427 </div>
432 instructions supported by the target. It is essentially an array of
434 instruction the target supports. Descriptors define things like the mnemonic
435 for the opcode, the number of operands, the list of implicit register uses
436 and defs, whether the instruction has certain target-independent properties
437 (accesses memory, is commutable, etc), and holds any target-specific
438 flags.</p>
440 </div>
442 <!-- ======================================================================= -->
445 </div>
450 stack frame layout of the target. It holds the direction of stack growth, the
451 known stack alignment on entry to each function, and the offset to the local
452 area. The offset to the local area is the offset from the stack pointer on
453 function entry to the first location where function data (local variables,
454 spill locations) can be stored.</p>
456 </div>
458 <!-- ======================================================================= -->
461 </div>
466 specific chip set being targeted. A sub-target informs code generation of
467 which instructions are supported, instruction latencies and instruction
468 execution itinerary; i.e., which processing units are used, in what order,
469 and for how long.</p>
471 </div>
474 <!-- ======================================================================= -->
477 </div>
482 Just-In-Time code generator to perform target-specific activities, such as
485 method.</p>
487 </div>
489 <!-- *********************************************************************** -->
492 </div>
493 <!-- *********************************************************************** -->
497 <p>At the high-level, LLVM code is translated to a machine specific
498 representation formed out of
503 agnostic, representing instructions in their most abstract form: an opcode
504 and a series of operands. This representation is designed to support both an
505 SSA representation for machine code, as well as a register allocated, non-SSA
506 form.</p>
508 </div>
510 <!-- ======================================================================= -->
513 </div>
517 <p>Target machine instructions are represented as instances of the
519 representing machine instructions. In particular, it only keeps track of an
520 opcode number and a set of operands.</p>
522 <p>The opcode number is a simple unsigned integer that only has meaning to a
523 specific backend. All of the instructions for a target should be defined in
526 not have any information about how to interpret the instruction (i.e., what
527 the semantics of the instruction are); for that you must refer to the
530 <p>The operands of a machine instruction can be of several different types: a
531 register reference, a constant integer, a basic block reference, etc. In
532 addition, a machine operand should be marked as a def or a use of the value
533 (though only registers are allowed to be defs).</p>
535 <p>By convention, the LLVM code generator orders instruction operands so that
536 all register definitions come before the register uses, even on architectures
537 that are normally printed in other orders. For example, the SPARC add
539 and stores the result into the "%i3" register. In the LLVM code generator,
540 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
541 destination first.</p>
543 <p>Keeping destination (definition) operands at the beginning of the operand
544 list has several advantages. In particular, the debugging printer will print
545 the instruction like this:</p>
548 <pre>
549 %r3 = add %i1, %i2
550 </pre>
551 </div>
556 </div>
558 <!-- _______________________________________________________________________ -->
561 </div>
571 <pre>
573 // instruction. The '1' specifies how many operands will be added.
576 // Create the same instr, but insert it at the end of a basic block.
577 MachineBasicBlock &MBB = ...
580 // Create the same instr, but insert it before a specified iterator point.
581 MachineBasicBlock::iterator MBBI = ...
584 // Create a 'cmp Reg, 0' instruction, no destination reg.
586 // Create an 'sahf' instruction which takes no operands and stores nothing.
587 MI = BuildMI(X86::SAHF, 0);
589 // Create a self looping branch instruction.
591 </pre>
592 </div>
595 have to specify the number of operands that the machine instruction will
596 take. This allows for efficient memory allocation. You also need to specify
597 if operands default to be uses of values, not definitions. If you need to
598 add a definition operand (other than the optional destination register), you
599 must explicitly mark it as such:</p>
602 <pre>
603 MI.addReg(Reg, MachineOperand::Def);
604 </pre>
605 </div>
607 </div>
609 <!-- _______________________________________________________________________ -->
612 </div>
616 <p>One important issue that the code generator needs to be aware of is the
617 presence of fixed registers. In particular, there are often places in the
619 particular value to be in a particular register. This can occur due to
620 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
622 calling conventions. In any case, the instruction selector should emit code
623 that copies a virtual register into or out of a physical register when
624 needed.</p>
629 <pre>
630 define i32 @test(i32 %X, i32 %Y) {
631 %Z = udiv i32 %X, %Y
632 ret i32 %Z
633 }
634 </pre>
635 </div>
639 get this):</p>
642 <pre>
643 ;; Start of div
644 %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
645 %reg1027 = sar %reg1024, 31
646 %EDX = mov %reg1027 ;; Sign extend X into EDX
647 idiv %reg1025 ;; Divide by Y (in reg1025)
648 %reg1026 = mov %EAX ;; Read the result (Z) out of EAX
650 ;; Start of ret
651 %EAX = mov %reg1026 ;; 32-bit return value goes in EAX
652 ret
653 </pre>
654 </div>
656 <p>By the end of code generation, the register allocator has coalesced the
657 registers and deleted the resultant identity moves producing the following
658 code:</p>
661 <pre>
662 ;; X is in EAX, Y is in ECX
663 mov %EAX, %EDX
664 sar %EDX, 31
665 idiv %ECX
666 ret
667 </pre>
668 </div>
670 <p>This approach is extremely general (if it can handle the X86 architecture, it
671 can handle anything!) and allows all of the target specific knowledge about
672 the instruction stream to be isolated in the instruction selector. Note that
673 physical registers should have a short lifetime for good code generation, and
674 all physical registers are assumed dead on entry to and exit from basic
675 blocks (before register allocation). Thus, if you need a value to be live
677 register.</p>
679 </div>
681 <!-- _______________________________________________________________________ -->
684 </div>
689 maintained in SSA-form until register allocation happens. For the most part,
690 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
691 become machine code PHI nodes, and virtual registers are only allowed to have
692 a single definition.</p>
694 <p>After register allocation, machine code is no longer in SSA-form because
695 there are no virtual registers left in the code.</p>
697 </div>
699 <!-- ======================================================================= -->
702 </div>
708 corresponds to the LLVM code input to the instruction selector, but there can
709 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
711 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
712 comes from.</p>
714 </div>
716 <!-- ======================================================================= -->
719 </div>
725 corresponds one-to-one with the LLVM function input to the instruction
726 selector. In addition to a list of basic blocks,
732 </div>
734 <!-- *********************************************************************** -->
737 </div>
738 <!-- *********************************************************************** -->
742 <p>This section documents the phases described in the
744 It explains how they work and some of the rationale behind their design.</p>
746 </div>
748 <!-- ======================================================================= -->
751 </div>
755 <p>Instruction Selection is the process of translating LLVM code presented to
756 the code generator into target-specific machine instructions. There are
757 several well-known ways to do this in the literature. LLVM uses a
758 SelectionDAG based instruction selector.</p>
760 <p>Portions of the DAG instruction selector are generated from the target
763 there are still things that require custom C++ code.</p>
765 </div>
767 <!-- _______________________________________________________________________ -->
770 </div>
774 <p>The SelectionDAG provides an abstraction for code representation in a way
775 that is amenable to instruction selection using automatic techniques
776 (e.g. dynamic-programming based optimal pattern matching selectors). It is
777 also well-suited to other phases of code generation; in particular,
778 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
779 post-selection). Additionally, the SelectionDAG provides a host
780 representation where a large variety of very-low-level (but
782 performed; ones which require extensive information about the instructions
783 efficiently supported by the target.</p>
785 <p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
787 operation code (Opcode) that indicates what operation the node performs and
788 the operands to the operation. The various operation node types are
790 file.</p>
792 <p>Although most operations define a single value, each node in the graph may
793 define multiple values. For example, a combined div/rem operation will
794 define both the dividend and the remainder. Many other situations require
795 multiple values as well. Each node also has some number of operands, which
796 are edges to the node defining the used value. Because nodes may define
799 and result value being used, respectively. Each value produced by
801 indicating what the type of the value is.</p>
803 <p>SelectionDAGs contain two different kinds of values: those that represent
804 data flow and those that represent control flow dependencies. Data values
805 are simple edges with an integer or floating point value type. Control edges
807 These edges provide an ordering between nodes that have side effects (such as
808 loads, stores, calls, returns, etc). All nodes that have side effects should
809 take a token chain as input and produce a new one as output. By convention,
810 token chain inputs are always operand #0, and chain results are always the
811 last value produced by an operation.</p>
815 node is the final side-effecting node in the token chain. For example, in a
816 single basic block function it would be the return node.</p>
819 "illegal" DAG. A legal DAG for a target is one that only uses supported
820 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
821 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
822 uses a SREM or UREM operation. The
825 responsible for turning an illegal DAG into a legal DAG.</p>
827 </div>
829 <!-- _______________________________________________________________________ -->
832 </div>
838 <ol>
840 performs a simple translation from the input LLVM code to an illegal
841 SelectionDAG.</li>
844 stage performs simple optimizations on the SelectionDAG to simplify it,
845 and recognize meta instructions (like rotates
847 operations. This makes the resultant code more efficient and
849 (below) simpler.</li>
852 — This stage transforms SelectionDAG nodes to eliminate any types
853 that are unsupported on the target.</li>
856 SelectionDAG optimizer is run to clean up redundancies exposed by type
857 legalization.</li>
860 This stage transforms SelectionDAG nodes to eliminate any types that are
861 unsupported on the target.</li>
864 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
865 operation legalization.</li>
868 Finally, the target instruction selector matches the DAG operations to
869 target instructions. This process translates the target-independent input
870 DAG into another DAG of target instructions.</li>
873 — The last phase assigns a linear order to the instructions in the
874 target-instruction DAG and emits them into the MachineFunction being
875 compiled. This step uses traditional prepass scheduling techniques.</li>
876 </ol>
878 <p>After all of these steps are complete, the SelectionDAG is destroyed and the
879 rest of the code generation passes are run.</p>
881 <p>One great way to visualize what is going on here is to take advantage of a
882 few LLC command line options. The following options pop up a window
883 displaying the SelectionDAG at specific times (if you only get errors printed
884 to the console while using this, you probably
886 to add support for it).</p>
888 <ul>
890 before the first optimization pass.</li>
895 optimization pass.</li>
900 </ul>
903 This graph is based on the final SelectionDAG, with nodes that must be
904 scheduled together bundled into a single scheduling-unit node, and with
905 immediate operands and other nodes that aren't relevant for scheduling
906 omitted.</p>
908 </div>
910 <!-- _______________________________________________________________________ -->
913 </div>
920 this pass is to expose as much low-level, target-specific details to the
921 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
924 requires target-specific hooks to lower calls, returns, varargs, etc. For
926 interface is used.</p>
928 </div>
930 <!-- _______________________________________________________________________ -->
933 </div>
937 <p>The Legalize phase is in charge of converting a DAG to only use the types
938 that are natively supported by the target.</p>
940 <p>There are two main ways of converting values of unsupported scalar types to
941 values of supported types: converting small types to larger types
942 ("promoting"), and breaking up large integer types into smaller ones
943 ("expanding"). For example, a target might require that all f32 values are
944 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
945 target might require that all i64 values be expanded into pairs of i32
946 values. These changes can insert sign and zero extensions as needed to make
947 sure that the final code has the same behavior as the input.</p>
949 <p>There are two main ways of converting values of unsupported vector types to
950 value of supported types: splitting vector types, multiple times if
951 necessary, until a legal type is found, and extending vector types by adding
952 elements to the end to round them out to legal types ("widening"). If a
953 vector gets split all the way down to single-element parts with no supported
954 vector type being found, the elements are converted to scalars
957 <p>A target implementation tells the legalizer which types are supported (and
958 which register class to use for them) by calling the
961 </div>
963 <!-- _______________________________________________________________________ -->
966 </div>
970 <p>The Legalize phase is in charge of converting a DAG to only use the
971 operations that are natively supported by the target.</p>
973 <p>Targets often have weird constraints, such as not supporting every operation
974 on every supported datatype (e.g. X86 does not support byte conditional moves
975 and PowerPC does not support sign-extending loads from a 16-bit memory
976 location). Legalize takes care of this by open-coding another sequence of
977 operations to emulate the operation ("expansion"), by promoting one type to a
978 larger type that supports the operation ("promotion"), or by using a
981 <p>A target implementation tells the legalizer which operations are not
982 supported (and which of the above three actions to take) by calling the
984 constructor.</p>
986 <p>Prior to the existence of the Legalize passes, we required that every target
988 operator and type even if they are not natively supported. The introduction
989 of the Legalize phases allows all of the canonicalization patterns to be
990 shared across targets, and makes it very easy to optimize the canonicalized
991 code because it is still in the form of a DAG.</p>
993 </div>
995 <!-- _______________________________________________________________________ -->
998 Combiner</a>
999 </div>
1003 <p>The SelectionDAG optimization phase is run multiple times for code
1004 generation, immediately after the DAG is built and once after each
1005 legalization. The first run of the pass allows the initial code to be
1006 cleaned up (e.g. performing optimizations that depend on knowing that the
1007 operators have restricted type inputs). Subsequent runs of the pass clean up
1008 the messy code generated by the Legalize passes, which allows Legalize to be
1009 very simple (it can focus on making code legal instead of focusing on
1012 <p>One important class of optimizations performed is optimizing inserted sign
1013 and zero extension instructions. We currently use ad-hoc techniques, but
1014 could move to more rigorous techniques in the future. Here are some good
1015 papers on the subject:</p>
1019 Kevin Redwine and Norman Ramsey<br>
1024 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1025 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1026 and Implementation.</p>
1028 </div>
1030 <!-- _______________________________________________________________________ -->
1033 </div>
1037 <p>The Select phase is the bulk of the target-specific code for instruction
1038 selection. This phase takes a legal SelectionDAG as input, pattern matches
1039 the instructions supported by the target to this DAG, and produces a new DAG
1040 of target code. For example, consider the following LLVM fragment:</p>
1043 <pre>
1044 %t1 = add float %W, %X
1045 %t2 = mul float %t1, %Y
1046 %t3 = add float %t2, %Z
1047 </pre>
1048 </div>
1050 <p>This LLVM code corresponds to a SelectionDAG that looks basically like
1051 this:</p>
1054 <pre>
1055 (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
1056 </pre>
1057 </div>
1059 <p>If a target supports floating point multiply-and-add (FMA) operations, one of
1060 the adds can be merged with the multiply. On the PowerPC, for example, the
1061 output of the instruction selector might look like this DAG:</p>
1064 <pre>
1065 (FMADDS (FADDS W, X), Y, Z)
1066 </pre>
1067 </div>
1070 first two operands and adds the third (as single-precision floating-point
1072 add instruction. To perform this pattern match, the PowerPC backend includes
1073 the following instruction definitions:</p>
1076 <pre>
1078 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1079 "fmadds $FRT, $FRA, $FRC, $FRB",
1080 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1083 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1084 "fadds $FRT, $FRA, $FRB",
1086 </pre>
1087 </div>
1089 <p>The portion of the instruction definition in bold indicates the pattern used
1090 to match the instruction. The DAG operators
1093 register class of the input and result values.</p>
1095 <p>The TableGen DAG instruction selector generator reads the instruction
1097 pattern matching code for your target. It has the following strengths:</p>
1099 <ul>
1100 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1101 you if your patterns make sense or not.</li>
1103 <li>It can handle arbitrary constraints on operands for the pattern match. In
1104 particular, it is straight-forward to say things like "match any immediate
1105 that is a 13-bit sign-extended value". For examples, see the
1107 backend.</li>
1109 <li>It knows several important identities for the patterns defined. For
1110 example, it knows that addition is commutative, so it allows the
1112 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1113 to specially handle this case.</li>
1115 <li>It has a full-featured type-inferencing system. In particular, you should
1116 rarely have to explicitly tell the system what type parts of your patterns
1119 It was able to infer and propagate this knowledge from the fact that
1123 Pattern fragments are chunks of reusable patterns that get inlined into
1124 your patterns during compiler-compiler time. For example, the integer
1125 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1126 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1128 short-hand fragments as they see fit. See the definition of
1131 <li>In addition to instructions, targets can specify arbitrary patterns that
1132 map to one or more instructions using the 'Pat' class. For example, the
1133 PowerPC has no way to load an arbitrary integer immediate into a register
1134 in one instruction. To tell tblgen how to do this, it defines:
1135 <br>
1136 <br>
1138 <pre>
1139 // Arbitrary immediate support. Implement in terms of LIS/ORI.
1140 def : Pat<(i32 imm:$imm),
1141 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
1142 </pre>
1143 </div>
1144 <br>
1145 If none of the single-instruction patterns for loading an immediate into a
1146 register match, this will be used. This rule says "match an arbitrary i32
1147 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1148 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1149 the left 16 bits') instruction". To make this work, the
1151 the input immediate (in this case, take the high or low 16-bits of the
1152 immediate).</li>
1154 <li>While the system does automate a lot, it still allows you to write custom
1155 C++ code to match special cases if there is something that is hard to
1156 express.</li>
1157 </ul>
1159 <p>While it has many strengths, the system currently has some limitations,
1160 primarily because it is a work in progress and is not yet finished:</p>
1162 <ul>
1163 <li>Overall, there is no way to define or match SelectionDAG nodes that define
1165 etc). This is the biggest reason that you currently still <em>have
1168 <li>There is no great way to support matching complex addressing modes yet.
1169 In the future, we will extend pattern fragments to allow them to define
1171 addressing mode</a>, which are currently matched with custom C++ code).
1172 In addition, we'll extend fragments so that a fragment can match multiple
1173 different patterns.</li>
1177 <li>We don't automatically generate the set of supported registers and
1179 yet.</li>
1182 </ul>
1184 <p>Despite these limitations, the instruction selector generator is still quite
1185 useful for most of the binary and logical operations in typical instruction
1186 sets. If you run into any problems or can't figure out how to do something,
1187 please let Chris know!</p>
1189 </div>
1191 <!-- _______________________________________________________________________ -->
1194 </div>
1198 <p>The scheduling phase takes the DAG of target instructions from the selection
1199 phase and assigns an order. The scheduler can pick an order depending on
1200 various constraints of the machines (i.e. order for minimal register pressure
1201 or try to cover instruction latencies). Once an order is established, the
1202 DAG is converted to a list
1204 destroyed.</p>
1206 <p>Note that this phase is logically separate from the instruction selection
1207 phase, but is tied to it closely in the code because it operates on
1208 SelectionDAGs.</p>
1210 </div>
1212 <!-- _______________________________________________________________________ -->
1215 </div>
1219 <ol>
1223 </ol>
1225 </div>
1227 <!-- ======================================================================= -->
1230 </div>
1233 <!-- ======================================================================= -->
1236 </div>
1242 determine if two or more virtual registers which require the same physical
1243 register are live at the same point in the program (i.e., they conflict).
1246 </div>
1248 <!-- _______________________________________________________________________ -->
1251 </div>
1255 <p>The first step in determining the live intervals of variables is to calculate
1256 the set of registers that are immediately dead after the instruction (i.e.,
1257 the instruction calculates the value, but it is never used) and the set of
1258 registers that are used by the instruction, but are never used after the
1259 instruction (i.e., they are killed). Live variable information is computed
1261 register in the function. This is done in a very efficient manner because it
1262 uses SSA to sparsely compute lifetime information for virtual registers
1263 (which are in SSA form) and only has to track physical registers within a
1264 block. Before register allocation, LLVM can assume that physical registers
1265 are only live within a single basic block. This allows it to do a single,
1266 local analysis to resolve physical register lifetimes within each basic
1267 block. If a physical register is not register allocatable (e.g., a stack
1268 pointer or condition codes), it is not tracked.</p>
1270 <p>Physical registers may be live in to or out of a function. Live in values are
1271 typically arguments in registers. Live out values are typically return values
1272 in registers. Live in values are marked as such, and are given a dummy
1273 "defining" instruction during live intervals analysis. If the last basic
1275 out values in the function.</p>
1278 the live variable information from a depth first traversal of the CFG of the
1281 only the definition is handled, because the uses will be handled in other
1282 basic blocks.</p>
1285 assignment at the end of the current basic block and traverse the successor
1289 of its predecessor basic blocks, until the basic block with the defining
1290 instruction is encountered.</p>
1292 </div>
1294 <!-- _______________________________________________________________________ -->
1297 </div>
1301 <p>We now have the information available to perform the live intervals analysis
1302 and build the live intervals themselves. We start off by numbering the basic
1303 blocks and machine instructions. We then handle the "live-in" values. These
1304 are in physical registers, so the physical register is assumed to be killed
1305 by the end of the basic block. Live intervals for virtual registers are
1312 </div>
1314 <!-- ======================================================================= -->
1317 </div>
1324 number of physical registers. Each target architecture has a different number
1325 of physical registers. If the number of physical registers is not enough to
1326 accommodate all the virtual registers, some of them will have to be mapped
1329 </div>
1331 <!-- _______________________________________________________________________ -->
1335 </div>
1339 <p>In LLVM, physical registers are denoted by integer numbers that normally
1342 architecture. For instance, by
1347 <p>Some architectures contain registers that share the same physical location. A
1348 notable example is the X86 platform. For instance, in the X86 architecture,
1351 particular architecture, you can check which registers are aliased by
1357 Elements in the same register class are functionally equivalent, and can be
1358 interchangeably used. Each virtual register can only be mapped to physical
1359 registers of a particular class. For instance, in the X86 architecture, some
1360 virtuals can only be allocated to 8 bit registers. A register class is
1362 register is compatible with a given physical, this code can be used:</p>
1365 <pre>
1366 bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1367 unsigned v_reg,
1368 unsigned p_reg) {
1369 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &&
1370 "Target register must be physical");
1371 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1372 return trc->contains(p_reg);
1373 }
1374 </pre>
1375 </div>
1377 <p>Sometimes, mostly for debugging purposes, it is useful to change the number
1378 of physical registers available in the target architecture. This must be done
1381 registers. Just commenting some out is one simple way to avoid them being
1382 used. A more polite way is to explicitly exclude some registers from
1387 <p>Virtual registers are also denoted by integer numbers. Contrary to physical
1388 registers, different virtual registers never share the same number. The
1389 smallest virtual register is normally assigned the number 1024. This may
1390 change, so, in order to know which is the first virtual register, you should
1392 number is greater than or equal
1394 register. Whereas physical registers are statically defined in
1396 application developer, that is not the case with virtual registers. In order
1397 to create new virtual registers, use the
1399 will return a virtual register with the highest code.</p>
1401 <p>Before register allocation, the operands of an instruction are mostly virtual
1402 registers, although physical registers may also be used. In order to check if
1403 a given machine operand is a register, use the boolean
1409 register is being used by the instruction. The
1411 defined.</p>
1413 <p>We will call physical registers present in the LLVM bitcode before register
1415 many different situations, for instance, to pass parameters of functions
1416 calls, and to store results of particular instructions. There are two types
1419 operands, and can be accessed
1421 which registers are implicitly defined by an instruction, use
1424 difference between explicit and implicit physical registers is that the
1425 latter are defined statically for each instruction, whereas the former may
1426 vary depending on the program being compiled. For example, an instruction
1427 that represents a function call will always implicitly define or use the same
1428 set of physical registers. To read the registers implicitly used by an
1429 instruction,
1431 registers impose constraints on any register allocation algorithm. The
1432 register allocator must make sure that none of them is been overwritten by
1433 the values of virtual registers while still alive.</p>
1435 </div>
1437 <!-- _______________________________________________________________________ -->
1441 </div>
1445 <p>There are two ways to map virtual registers to physical registers (or to
1450 and stores sending and getting values to and from memory.</p>
1452 <p>The direct mapping provides more flexibility to the developer of the register
1453 allocator; however, it is more error prone, and demands more implementation
1454 work. Basically, the programmer will have to specify where load and store
1455 instructions should be inserted in the target function being compiled in
1456 order to get and store values in memory. To assign a physical register to a
1457 virtual register present in a given operand,
1462 <p>The indirect mapping shields the application developer from the complexities
1463 of inserting load and store instructions. In order to map a virtual register
1465 order to map a certain virtual register to memory,
1468 necessary to map another virtual register to the same stack slot,
1470 important point to consider when using the indirect mapping, is that even if
1471 a virtual register is mapped to memory, it still needs to be mapped to a
1472 physical register. This physical register is the location where the virtual
1473 register is supposed to be found before being stored or after being
1474 reloaded.</p>
1476 <p>If the indirect strategy is used, after all the virtual registers have been
1477 mapped to physical registers or stack slots, it is necessary to use a spiller
1478 object to place load and store instructions in the code. Every virtual that
1479 has been mapped to a stack slot will be stored to memory after been defined
1480 and will be loaded before being used. The implementation of the spiller tries
1481 to recycle load/store instructions, avoiding unnecessary instructions. For an
1482 example of how to invoke the spiller,
1486 </div>
1488 <!-- _______________________________________________________________________ -->
1491 </div>
1495 <p>With very rare exceptions (e.g., function calls), the LLVM machine code
1496 instructions are three address instructions. That is, each instruction is
1497 expected to define at most one register, and to use at most two registers.
1498 However, some architectures use two address instructions. In this case, the
1499 defined register is also one of the used register. For instance, an
1503 <p>In order to produce correct code, LLVM must convert three address
1504 instructions that represent two address instructions into true two address
1506 this specific purpose. It must be run before register allocation takes
1507 place. After its execution, the resulting code may no longer be in SSA
1508 form. This happens, for instance, in situations where an instruction such
1512 <pre>
1513 %a = MOVE %b
1514 %a = ADD %a %c
1515 </pre>
1516 </div>
1518 <p>Notice that, internally, the second instruction is represented as
1520 used and defined by the instruction.</p>
1522 </div>
1524 <!-- _______________________________________________________________________ -->
1527 </div>
1531 <p>An important transformation that happens during register allocation is called
1533 that are performed on the control flow graph of programs. However,
1534 traditional instruction sets do not implement PHI instructions. Thus, in
1535 order to generate executable code, compilers must replace PHI instructions
1536 with other instructions that preserve their semantics.</p>
1538 <p>There are many ways in which PHI instructions can safely be removed from the
1539 target code. The most traditional PHI deconstruction algorithm replaces PHI
1540 instructions with copy instructions. That is the strategy adopted by
1541 LLVM. The SSA deconstruction algorithm is implemented
1544 of the register allocator.</p>
1546 </div>
1548 <!-- _______________________________________________________________________ -->
1551 </div>
1556 allocation that removes unnecessary copy instructions. For instance, a
1557 sequence of instructions such as:</p>
1560 <pre>
1561 %EBX = LOAD %mem_address
1562 %EAX = COPY %EBX
1563 </pre>
1564 </div>
1569 <pre>
1570 %EAX = LOAD %mem_address
1571 </pre>
1572 </div>
1574 <p>Instructions can be folded with
1576 taken when folding instructions; a folded instruction can be quite different
1577 from the original
1580 use.</p>
1582 </div>
1584 <!-- _______________________________________________________________________ -->
1588 </div>
1592 <p>The LLVM infrastructure provides the application developer with three
1593 different register allocators:</p>
1595 <ul>
1597 keep values in registers across instructions. This register allocator
1598 immediately spills every value right after it is computed, and reloads all
1599 used operands from memory to temporary registers before each
1600 instruction.</li>
1604 level, attempting to keep values in registers and reusing registers as
1605 appropriate.</li>
1608 well-know linear scan register allocator. Whereas the
1611 uses a spiller in order to place load and stores.</li>
1612 </ul>
1618 <pre>
1619 $ llc -f -regalloc=simple file.bc -o sp.s;
1620 $ llc -f -regalloc=local file.bc -o lc.s;
1621 $ llc -f -regalloc=linearscan file.bc -o ln.s;
1622 </pre>
1623 </div>
1625 </div>
1627 <!-- ======================================================================= -->
1630 </div>
1632 <!-- ======================================================================= -->
1635 </div>
1637 <!-- ======================================================================= -->
1640 </div>
1642 <!-- _______________________________________________________________________ -->
1645 </div>
1647 <!-- _______________________________________________________________________ -->
1650 </div>
1654 </div>
1657 <!-- *********************************************************************** -->
1660 </div>
1661 <!-- *********************************************************************** -->
1665 <p>This section of the document explains features or design decisions that are
1666 specific to the code generator for a particular target.</p>
1668 </div>
1670 <!-- ======================================================================= -->
1673 </div>
1677 <p>Tail call optimization, callee reusing the stack of the caller, is currently
1680 <ul>
1683 <li>The call is a tail call - in tail position (ret immediately follows call
1684 and ret uses value of call or is void).</li>
1689 </ul>
1693 <ul>
1697 = hidden or protected) are supported.</li>
1698 </ul>
1702 <ul>
1707 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
1708 </ul>
1715 <pre>
1716 declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
1718 define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
1719 %l1 = add i32 %in1, %in2
1720 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
1721 ret i32 %tmp
1722 }
1723 </pre>
1724 </div>
1728 <p>To support tail call optimization in situations where the callee has more
1729 arguments than the caller a 'callee pops arguments' convention is used. This
1731 (because one or more of above constraints are not met) to be followed by a
1732 readjustment of the stack. So performance might be worse in such cases.</p>
1735 function pointer). So there is one less register for integer argument
1739 </div>
1740 <!-- ======================================================================= -->
1743 </div>
1749 processors, and includes support for ISA extensions such as MMX and SSE.</p>
1751 </div>
1753 <!-- _______________________________________________________________________ -->
1756 </div>
1760 <p>The following are the known target triples that are supported by the X86
1761 backend. This is not an exhaustive list, and it would be useful to add those
1762 that people test.</p>
1764 <ul>
1776 </ul>
1778 </div>
1780 <!-- _______________________________________________________________________ -->
1783 </div>
1790 <ul>
1796 </ul>
1798 </div>
1800 <!-- _______________________________________________________________________ -->
1803 </div>
1807 <p>The x86 has a very flexible way of accessing memory. It is capable of
1808 forming memory addresses of the following expression directly in integer
1809 instructions (which use ModR/M addressing):</p>
1812 <pre>
1814 </pre>
1815 </div>
1818 memory operand of this form. This means that the "load" form of
1822 <pre>
1824 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1825 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1826 </pre>
1827 </div>
1829 <p>Stores, and all other instructions, treat the four memory operands in the
1830 same way and in the same order.</p>
1832 </div>
1834 <!-- _______________________________________________________________________ -->
1837 </div>
1841 <p>x86 has the ability to perform loads and stores to different address spaces
1842 via the x86 segment registers. A segment override prefix byte on an
1843 instruction causes the instruction's memory access to go to the specified
1844 segment. LLVM address space 0 is the default address space, which includes
1845 the stack, and any unqualified memory accesses in a program. Address spaces
1847 represented by address space 256. Other x86 segments have yet to be
1848 allocated address space numbers.</p>
1850 <p>Some operating systems use the GS-segment to implement TLS, so care should be
1853 </div>
1855 <!-- _______________________________________________________________________ -->
1858 </div>
1862 <p>An instruction name consists of the base name, a default operand size, and a
1863 a character per operand with an optional special size. For example:</p>
1866 <pre>
1871 </pre>
1872 </div>
1874 </div>
1876 <!-- ======================================================================= -->
1879 </div>
1883 <p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
1885 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
1887 </div>
1889 <!-- _______________________________________________________________________ -->
1892 </div>
1896 <p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
1897 relative (PIC) or static addressing for accessing global values, so no TOC
1898 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
1899 of a stack frame. LLVM takes advantage of having no TOC to provide space to
1900 save the frame pointer in the PowerPC linkage area of the caller frame.
1901 Other details of PowerPC ABI can be found at <a href=
1902 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
1905 for system use.</p>
1907 </div>
1909 <!-- _______________________________________________________________________ -->
1912 </div>
1916 <p>The size of a PowerPC frame is usually fixed for the duration of a
1917 function's invocation. Since the frame is fixed size, all references
1918 into the frame can be accessed via fixed offsets from the stack pointer. The
1919 exception to this is when dynamic alloca or variable sized arrays are
1920 present, then a base pointer (r31) is used as a proxy for the stack pointer
1921 and stack pointer is free to grow or shrink. A base pointer is also used if
1922 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
1923 always aligned to 16 bytes, so that space allocated for altivec vectors will
1924 be properly aligned.</p>
1929 <tr>
1931 </tr>
1932 <tr>
1934 </tr>
1935 <tr>
1937 </tr>
1938 <tr>
1940 </tr>
1941 <tr>
1943 </tr>
1945 <td><br></td>
1946 </tr>
1947 <tr>
1949 </tr>
1950 </table>
1953 to allocating its own frame. Only three entries are relevant to LLVM. The
1954 first entry is the previous stack pointer (sp), aka link. This allows
1955 probing tools like gdb or exception handlers to quickly scan the frames in
1956 the stack. A function epilog can also use the link to pop the frame from the
1957 stack. The third entry in the linkage area is used to save the return
1958 address from the lr register. Finally, as mentioned above, the last entry is
1959 used to save the previous frame pointer (r31.) The entries in the linkage
1966 <tr>
1969 </tr>
1970 <tr>
1973 </tr>
1974 <tr>
1977 </tr>
1978 <tr>
1981 </tr>
1982 <tr>
1985 </tr>
1986 <tr>
1989 </tr>
1990 </table>
1995 <tr>
1998 </tr>
1999 <tr>
2002 </tr>
2003 <tr>
2006 </tr>
2007 <tr>
2010 </tr>
2011 <tr>
2014 </tr>
2015 <tr>
2018 </tr>
2019 </table>
2022 function. Following the PowerPC ABI, the first few arguments are actually
2023 passed in registers, with the space in the parameter area unused. However,
2024 if there are not enough registers or the callee is a thunk or vararg
2025 function, these register arguments can be spilled into the parameter area.
2026 Thus, the parameter area must be large enough to store all the parameters for
2027 the largest call sequence made by the caller. The size must also be
2028 minimally large enough to spill registers r3-r10. This allows callees blind
2029 to the call signature, such as thunks and vararg functions, enough space to
2030 cache the argument registers. Therefore, the parameter area is minimally 32
2032 a fixed offset from the top of the frame, that a callee can access its spilt
2033 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
2035 <p>Combining the information about the linkage, parameter areas and alignment. A
2037 mode.</p>
2040 alloca then space is added to the stack, the linkage and parameter areas are
2041 shifted to top of stack, and the new space is available immediately below the
2042 linkage and parameter areas. The cost of shifting the linkage and parameter
2043 areas is minor since only the link value needs to be copied. The link value
2044 can be easily fetched by adding the original frame size to the base pointer.
2045 Note that allocations in the dynamic space need to observe 16 byte
2046 alignment.</p>
2049 variables.</p>
2052 saved registers on entry to the callee.</p>
2054 </div>
2056 <!-- _______________________________________________________________________ -->
2059 </div>
2063 <p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
2064 the following exceptions. Callee saved registers are spilled after the frame
2065 is created. This allows the llvm epilog/prolog support to be common with
2066 other targets. The base pointer callee saved register r31 is saved in the
2067 TOC slot of linkage area. This simplifies allocation of space for the base
2068 pointer and makes it convenient to locate programatically and during
2069 debugging.</p>
2071 </div>
2073 <!-- _______________________________________________________________________ -->
2076 </div>
2082 </div>
2085 <!-- *********************************************************************** -->
2086 <hr>
2087 <address>
2095 Last modified: $Date$
2096 </address>
2098 </body>
2099 </html>