lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

   1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements the ScheduleDAG class, which is a base class used by
  11 // scheduling implementation classes.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "pre-RA-sched"
  16 #include "ScheduleDAGSDNodes.h"
  17 #include "llvm/CodeGen/SelectionDAG.h"
  18 #include "llvm/Target/TargetMachine.h"
  19 #include "llvm/Target/TargetInstrInfo.h"
  20 #include "llvm/Target/TargetRegisterInfo.h"
  21 #include "llvm/Support/Debug.h"
  22 #include "llvm/Support/raw_ostream.h"
  23 using namespace llvm;
  24
  25 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
  26   : ScheduleDAG(mf) {
  27 }
  28
  29 /// Run - perform scheduling.
  30 ///
  31 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb,
  32                              MachineBasicBlock::iterator insertPos) {
  33   DAG = dag;
  34   ScheduleDAG::Run(bb, insertPos);
  35 }
  36
  37 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
  38   SUnit *SU = NewSUnit(Old->getNode());
  39   SU->OrigNode = Old->OrigNode;
  40   SU->Latency = Old->Latency;
  41   SU->isTwoAddress = Old->isTwoAddress;
  42   SU->isCommutable = Old->isCommutable;
  43   SU->hasPhysRegDefs = Old->hasPhysRegDefs;
  44   SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
  45   Old->isCloned = true;
  46   return SU;
  47 }
  48
  49 /// CheckForPhysRegDependency - Check if the dependency between def and use of
  50 /// a specified operand is a physical register dependency. If so, returns the
  51 /// register and the cost of copying the register.
  52 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
  53                                       const TargetRegisterInfo *TRI,
  54                                       const TargetInstrInfo *TII,
  55                                       unsigned &PhysReg, int &Cost) {
  56   if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
  57     return;
  58
  59   unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
  60   if (TargetRegisterInfo::isVirtualRegister(Reg))
  61     return;
  62
  63   unsigned ResNo = User->getOperand(2).getResNo();
  64   if (Def->isMachineOpcode()) {
  65     const TargetInstrDesc &II = TII->get(Def->getMachineOpcode());
  66     if (ResNo >= II.getNumDefs() &&
  67         II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
  68       PhysReg = Reg;
  69       const TargetRegisterClass *RC =
  70         TRI->getPhysicalRegisterRegClass(Reg, Def->getValueType(ResNo));
  71       Cost = RC->getCopyCost();
  72     }
  73   }
  74 }
  75
  76 void ScheduleDAGSDNodes::BuildSchedUnits() {
  77   // During scheduling, the NodeId field of SDNode is used to map SDNodes
  78   // to their associated SUnits by holding SUnits table indices. A value
  79   // of -1 means the SDNode does not yet have an associated SUnit.
  80   unsigned NumNodes = 0;
  81   for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
  82        E = DAG->allnodes_end(); NI != E; ++NI) {
  83     NI->setNodeId(-1);
  84     ++NumNodes;
  85   }
  86
  87   // Reserve entries in the vector for each of the SUnits we are creating.  This
  88   // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
  89   // invalidated.
  90   // FIXME: Multiply by 2 because we may clone nodes during scheduling.
  91   // This is a temporary workaround.
  92   SUnits.reserve(NumNodes * 2);
  93
  94   // Check to see if the scheduler cares about latencies.
  95   bool UnitLatencies = ForceUnitLatencies();
  96
  97   for (SelectionDAG::allnodes_iterator NI = DAG->allnodes_begin(),
  98        E = DAG->allnodes_end(); NI != E; ++NI) {
  99     if (isPassiveNode(NI))  // Leaf node, e.g. a TargetImmediate.
 100       continue;
 101
 102     // If this node has already been processed, stop now.
 103     if (NI->getNodeId() != -1) continue;
 104
 105     SUnit *NodeSUnit = NewSUnit(NI);
 106
 107     // See if anything is flagged to this node, if so, add them to flagged
 108     // nodes.  Nodes can have at most one flag input and one flag output.  Flags
 109     // are required to be the last operand and result of a node.
 110
 111     // Scan up to find flagged preds.
 112     SDNode *N = NI;
 113     while (N->getNumOperands() &&
 114            N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
 115       N = N->getOperand(N->getNumOperands()-1).getNode();
 116       assert(N->getNodeId() == -1 && "Node already inserted!");
 117       N->setNodeId(NodeSUnit->NodeNum);
 118     }
 119
 120     // Scan down to find any flagged succs.
 121     N = NI;
 122     while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
 123       SDValue FlagVal(N, N->getNumValues()-1);
 124
 125       // There are either zero or one users of the Flag result.
 126       bool HasFlagUse = false;
 127       for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
 128            UI != E; ++UI)
 129         if (FlagVal.isOperandOf(*UI)) {
 130           HasFlagUse = true;
 131           assert(N->getNodeId() == -1 && "Node already inserted!");
 132           N->setNodeId(NodeSUnit->NodeNum);
 133           N = *UI;
 134           break;
 135         }
 136       if (!HasFlagUse) break;
 137     }
 138
 139     // If there are flag operands involved, N is now the bottom-most node
 140     // of the sequence of nodes that are flagged together.
 141     // Update the SUnit.
 142     NodeSUnit->setNode(N);
 143     assert(N->getNodeId() == -1 && "Node already inserted!");
 144     N->setNodeId(NodeSUnit->NodeNum);
 145
 146     // Assign the Latency field of NodeSUnit using target-provided information.
 147     if (UnitLatencies)
 148       NodeSUnit->Latency = 1;
 149     else
 150       ComputeLatency(NodeSUnit);
 151   }
 152 }
 153
 154 void ScheduleDAGSDNodes::AddSchedEdges() {
 155   // Pass 2: add the preds, succs, etc.
 156   for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
 157     SUnit *SU = &SUnits[su];
 158     SDNode *MainNode = SU->getNode();
 159
 160     if (MainNode->isMachineOpcode()) {
 161       unsigned Opc = MainNode->getMachineOpcode();
 162       const TargetInstrDesc &TID = TII->get(Opc);
 163       for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
 164         if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
 165           SU->isTwoAddress = true;
 166           break;
 167         }
 168       }
 169       if (TID.isCommutable())
 170         SU->isCommutable = true;
 171     }
 172
 173     // Find all predecessors and successors of the group.
 174     for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode()) {
 175       if (N->isMachineOpcode() &&
 176           TII->get(N->getMachineOpcode()).getImplicitDefs()) {
 177         SU->hasPhysRegClobbers = true;
 178         unsigned NumUsed = CountResults(N);
 179         while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
 180           --NumUsed;    // Skip over unused values at the end.
 181         if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
 182           SU->hasPhysRegDefs = true;
 183       }
 184
 185       for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
 186         SDNode *OpN = N->getOperand(i).getNode();
 187         if (isPassiveNode(OpN)) continue;   // Not scheduled.
 188         SUnit *OpSU = &SUnits[OpN->getNodeId()];
 189         assert(OpSU && "Node has no SUnit!");
 190         if (OpSU == SU) continue;           // In the same group.
 191
 192         MVT OpVT = N->getOperand(i).getValueType();
 193         assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
 194         bool isChain = OpVT == MVT::Other;
 195
 196         unsigned PhysReg = 0;
 197         int Cost = 1;
 198         // Determine if this is a physical register dependency.
 199         CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
 200         assert((PhysReg == 0 || !isChain) &&
 201                "Chain dependence via physreg data?");
 202         // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
 203         // emits a copy from the physical register to a virtual register unless
 204         // it requires a cross class copy (cost < 0). That means we are only
 205         // treating "expensive to copy" register dependency as physical register
 206         // dependency. This may change in the future though.
 207         if (Cost >= 0)
 208           PhysReg = 0;
 209         SU->addPred(SDep(OpSU, isChain ? SDep::Order : SDep::Data,
 210                          OpSU->Latency, PhysReg));
 211       }
 212     }
 213   }
 214 }
 215
 216 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
 217 /// are input.  This SUnit graph is similar to the SelectionDAG, but
 218 /// excludes nodes that aren't interesting to scheduling, and represents
 219 /// flagged together nodes with a single SUnit.
 220 void ScheduleDAGSDNodes::BuildSchedGraph() {
 221   // Populate the SUnits array.
 222   BuildSchedUnits();
 223   // Compute all the scheduling dependencies between nodes.
 224   AddSchedEdges();
 225 }
 226
 227 void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
 228   const InstrItineraryData &InstrItins = TM.getInstrItineraryData();
 229
 230   // Compute the latency for the node.  We use the sum of the latencies for
 231   // all nodes flagged together into this SUnit.
 232   SU->Latency = 0;
 233   bool SawMachineOpcode = false;
 234   for (SDNode *N = SU->getNode(); N; N = N->getFlaggedNode())
 235     if (N->isMachineOpcode()) {
 236       SawMachineOpcode = true;
 237       SU->Latency +=
 238         InstrItins.getLatency(TII->get(N->getMachineOpcode()).getSchedClass());
 239     }
 240 }
 241
 242 /// CountResults - The results of target nodes have register or immediate
 243 /// operands first, then an optional chain, and optional flag operands (which do
 244 /// not go into the resulting MachineInstr).
 245 unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
 246   unsigned N = Node->getNumValues();
 247   while (N && Node->getValueType(N - 1) == MVT::Flag)
 248     --N;
 249   if (N && Node->getValueType(N - 1) == MVT::Other)
 250     --N;    // Skip over chain result.
 251   return N;
 252 }
 253
 254 /// CountOperands - The inputs to target nodes have any actual inputs first,
 255 /// followed by special operands that describe memory references, then an
 256 /// optional chain operand, then an optional flag operand.  Compute the number
 257 /// of actual operands that will go into the resulting MachineInstr.
 258 unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) {
 259   unsigned N = ComputeMemOperandsEnd(Node);
 260   while (N && isa<MemOperandSDNode>(Node->getOperand(N - 1).getNode()))
 261     --N; // Ignore MEMOPERAND nodes
 262   return N;
 263 }
 264
 265 /// ComputeMemOperandsEnd - Find the index one past the last MemOperandSDNode
 266 /// operand
 267 unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
 268   unsigned N = Node->getNumOperands();
 269   while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
 270     --N;
 271   if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
 272     --N; // Ignore chain if it exists.
 273   return N;
 274 }
 275
 276
 277 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
 278   if (!SU->getNode()) {
 279     cerr << "PHYS REG COPY\n";
 280     return;
 281   }
 282
 283   SU->getNode()->dump(DAG);
 284   cerr << "\n";
 285   SmallVector<SDNode *, 4> FlaggedNodes;
 286   for (SDNode *N = SU->getNode()->getFlaggedNode(); N; N = N->getFlaggedNode())
 287     FlaggedNodes.push_back(N);
 288   while (!FlaggedNodes.empty()) {
 289     cerr << "    ";
 290     FlaggedNodes.back()->dump(DAG);
 291     cerr << "\n";
 292     FlaggedNodes.pop_back();
 293   }
 294 }