lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp

   1 //===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This implements the Emit routines for the ScheduleDAG class, which creates
  11 // MachineInstrs according to the computed schedule.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "pre-RA-sched"
  16 #include "ScheduleDAGSDNodes.h"
  17 #include "llvm/CodeGen/MachineConstantPool.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/Target/TargetData.h"
  22 #include "llvm/Target/TargetMachine.h"
  23 #include "llvm/Target/TargetInstrInfo.h"
  24 #include "llvm/Target/TargetLowering.h"
  25 #include "llvm/ADT/Statistic.h"
  26 #include "llvm/Support/CommandLine.h"
  27 #include "llvm/Support/Debug.h"
  28 #include "llvm/Support/MathExtras.h"
  29 using namespace llvm;
  30
  31 /// getInstrOperandRegClass - Return register class of the operand of an
  32 /// instruction of the specified TargetInstrDesc.
  33 static const TargetRegisterClass*
  34 getInstrOperandRegClass(const TargetRegisterInfo *TRI,
  35                         const TargetInstrDesc &II, unsigned Op) {
  36   if (Op >= II.getNumOperands()) {
  37     assert(II.isVariadic() && "Invalid operand # of instruction");
  38     return NULL;
  39   }
  40   if (II.OpInfo[Op].isLookupPtrRegClass())
  41     return TRI->getPointerRegClass();
  42   return TRI->getRegClass(II.OpInfo[Op].RegClass);
  43 }
  44
  45 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
  46 /// implicit physical register output.
  47 void ScheduleDAGSDNodes::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
  48                                          bool IsClone, bool IsCloned,
  49                                          unsigned SrcReg,
  50                                          DenseMap<SDValue, unsigned> &VRBaseMap) {
  51   unsigned VRBase = 0;
  52   if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
  53     // Just use the input register directly!
  54     SDValue Op(Node, ResNo);
  55     if (IsClone)
  56       VRBaseMap.erase(Op);
  57     bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
  58     isNew = isNew; // Silence compiler warning.
  59     assert(isNew && "Node emitted out of order - early");
  60     return;
  61   }
  62
  63   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
  64   // the CopyToReg'd destination register instead of creating a new vreg.
  65   bool MatchReg = true;
  66   const TargetRegisterClass *UseRC = NULL;
  67   if (!IsClone && !IsCloned)
  68     for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
  69          UI != E; ++UI) {
  70       SDNode *User = *UI;
  71       bool Match = true;
  72       if (User->getOpcode() == ISD::CopyToReg &&
  73           User->getOperand(2).getNode() == Node &&
  74           User->getOperand(2).getResNo() == ResNo) {
  75         unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
  76         if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
  77           VRBase = DestReg;
  78           Match = false;
  79         } else if (DestReg != SrcReg)
  80           Match = false;
  81       } else {
  82         for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
  83           SDValue Op = User->getOperand(i);
  84           if (Op.getNode() != Node || Op.getResNo() != ResNo)
  85             continue;
  86           MVT VT = Node->getValueType(Op.getResNo());
  87           if (VT == MVT::Other || VT == MVT::Flag)
  88             continue;
  89           Match = false;
  90           if (User->isMachineOpcode()) {
  91             const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
  92             const TargetRegisterClass *RC =
  93               getInstrOperandRegClass(TRI, II, i+II.getNumDefs());
  94             if (!UseRC)
  95               UseRC = RC;
  96             else if (RC) {
  97               if (UseRC->hasSuperClass(RC))
  98                 UseRC = RC;
  99               else
 100                 assert((UseRC == RC || RC->hasSuperClass(UseRC)) &&
 101                        "Multiple uses expecting different register classes!");
 102             }
 103           }
 104         }
 105       }
 106       MatchReg &= Match;
 107       if (VRBase)
 108         break;
 109     }
 110
 111   MVT VT = Node->getValueType(ResNo);
 112   const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
 113   SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
 114
 115   // Figure out the register class to create for the destreg.
 116   if (VRBase) {
 117     DstRC = MRI.getRegClass(VRBase);
 118   } else if (UseRC) {
 119     assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
 120     DstRC = UseRC;
 121   } else {
 122     DstRC = TLI->getRegClassFor(VT);
 123   }
 124
 125   // If all uses are reading from the src physical register and copying the
 126   // register is either impossible or very expensive, then don't create a copy.
 127   if (MatchReg && SrcRC->getCopyCost() < 0) {
 128     VRBase = SrcReg;
 129   } else {
 130     // Create the reg, emit the copy.
 131     VRBase = MRI.createVirtualRegister(DstRC);
 132     bool Emitted = TII->copyRegToReg(*BB, InsertPos, VRBase, SrcReg,
 133                                      DstRC, SrcRC);
 134
 135     assert(Emitted && "Unable to issue a copy instruction!\n");
 136   }
 137
 138   SDValue Op(Node, ResNo);
 139   if (IsClone)
 140     VRBaseMap.erase(Op);
 141   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 142   isNew = isNew; // Silence compiler warning.
 143   assert(isNew && "Node emitted out of order - early");
 144 }
 145
 146 /// getDstOfCopyToRegUse - If the only use of the specified result number of
 147 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
 148 unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
 149                                                       unsigned ResNo) const {
 150   if (!Node->hasOneUse())
 151     return 0;
 152
 153   SDNode *User = *Node->use_begin();
 154   if (User->getOpcode() == ISD::CopyToReg &&
 155       User->getOperand(2).getNode() == Node &&
 156       User->getOperand(2).getResNo() == ResNo) {
 157     unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 158     if (TargetRegisterInfo::isVirtualRegister(Reg))
 159       return Reg;
 160   }
 161   return 0;
 162 }
 163
 164 void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
 165                                        const TargetInstrDesc &II,
 166                                        bool IsClone, bool IsCloned,
 167                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
 168   assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
 169          "IMPLICIT_DEF should have been handled as a special case elsewhere!");
 170
 171   for (unsigned i = 0; i < II.getNumDefs(); ++i) {
 172     // If the specific node value is only used by a CopyToReg and the dest reg
 173     // is a vreg in the same register class, use the CopyToReg'd destination
 174     // register instead of creating a new vreg.
 175     unsigned VRBase = 0;
 176     const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, II, i);
 177
 178     if (!IsClone && !IsCloned)
 179       for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 180            UI != E; ++UI) {
 181         SDNode *User = *UI;
 182         if (User->getOpcode() == ISD::CopyToReg &&
 183             User->getOperand(2).getNode() == Node &&
 184             User->getOperand(2).getResNo() == i) {
 185           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 186           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
 187             const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
 188             if (RegRC == RC) {
 189               VRBase = Reg;
 190               MI->addOperand(MachineOperand::CreateReg(Reg, true));
 191               break;
 192             }
 193           }
 194         }
 195       }
 196
 197     // Create the result registers for this node and add the result regs to
 198     // the machine instruction.
 199     if (VRBase == 0) {
 200       assert(RC && "Isn't a register operand!");
 201       VRBase = MRI.createVirtualRegister(RC);
 202       MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 203     }
 204
 205     SDValue Op(Node, i);
 206     if (IsClone)
 207       VRBaseMap.erase(Op);
 208     bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 209     isNew = isNew; // Silence compiler warning.
 210     assert(isNew && "Node emitted out of order - early");
 211   }
 212 }
 213
 214 /// getVR - Return the virtual register corresponding to the specified result
 215 /// of the specified node.
 216 unsigned ScheduleDAGSDNodes::getVR(SDValue Op,
 217                                    DenseMap<SDValue, unsigned> &VRBaseMap) {
 218   if (Op.isMachineOpcode() &&
 219       Op.getMachineOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
 220     // Add an IMPLICIT_DEF instruction before every use.
 221     unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
 222     // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
 223     // does not include operand register class info.
 224     if (!VReg) {
 225       const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
 226       VReg = MRI.createVirtualRegister(RC);
 227     }
 228     BuildMI(BB, Op.getDebugLoc(), TII->get(TargetInstrInfo::IMPLICIT_DEF),VReg);
 229     return VReg;
 230   }
 231
 232   DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
 233   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
 234   return I->second;
 235 }
 236
 237
 238 /// AddRegisterOperand - Add the specified register as an operand to the
 239 /// specified machine instr. Insert register copies if the register is
 240 /// not in the required register class.
 241 void
 242 ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op,
 243                                        unsigned IIOpNum,
 244                                        const TargetInstrDesc *II,
 245                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
 246   assert(Op.getValueType() != MVT::Other &&
 247          Op.getValueType() != MVT::Flag &&
 248          "Chain and flag operands should occur at end of operand list!");
 249   // Get/emit the operand.
 250   unsigned VReg = getVR(Op, VRBaseMap);
 251   assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
 252
 253   const TargetInstrDesc &TID = MI->getDesc();
 254   bool isOptDef = IIOpNum < TID.getNumOperands() &&
 255     TID.OpInfo[IIOpNum].isOptionalDef();
 256
 257   // If the instruction requires a register in a different class, create
 258   // a new virtual register and copy the value into it.
 259   if (II) {
 260     const TargetRegisterClass *SrcRC =
 261       MRI.getRegClass(VReg);
 262     const TargetRegisterClass *DstRC =
 263       getInstrOperandRegClass(TRI, *II, IIOpNum);
 264     assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
 265            "Don't have operand info for this instruction!");
 266     if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
 267       unsigned NewVReg = MRI.createVirtualRegister(DstRC);
 268       bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
 269                                        DstRC, SrcRC);
 270       assert(Emitted && "Unable to issue a copy instruction!\n");
 271       VReg = NewVReg;
 272     }
 273   }
 274
 275   MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
 276 }
 277
 278 /// AddOperand - Add the specified operand to the specified machine instr.  II
 279 /// specifies the instruction information for the node, and IIOpNum is the
 280 /// operand number (in the II) that we are adding. IIOpNum and II are used for
 281 /// assertions only.
 282 void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op,
 283                                     unsigned IIOpNum,
 284                                     const TargetInstrDesc *II,
 285                                     DenseMap<SDValue, unsigned> &VRBaseMap) {
 286   if (Op.isMachineOpcode()) {
 287     AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
 288   } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
 289     MI->addOperand(MachineOperand::CreateImm(C->getZExtValue()));
 290   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
 291     const ConstantFP *CFP = F->getConstantFPValue();
 292     MI->addOperand(MachineOperand::CreateFPImm(CFP));
 293   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
 294     MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
 295   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
 296     MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
 297   } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
 298     MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
 299   } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
 300     MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
 301   } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
 302     MI->addOperand(MachineOperand::CreateJTI(JT->getIndex()));
 303   } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
 304     int Offset = CP->getOffset();
 305     unsigned Align = CP->getAlignment();
 306     const Type *Type = CP->getType();
 307     // MachineConstantPool wants an explicit alignment.
 308     if (Align == 0) {
 309       Align = TM.getTargetData()->getPrefTypeAlignment(Type);
 310       if (Align == 0) {
 311         // Alignment of vector types.  FIXME!
 312         Align = TM.getTargetData()->getTypePaddedSize(Type);
 313       }
 314     }
 315
 316     unsigned Idx;
 317     if (CP->isMachineConstantPoolEntry())
 318       Idx = ConstPool->getConstantPoolIndex(CP->getMachineCPVal(), Align);
 319     else
 320       Idx = ConstPool->getConstantPoolIndex(CP->getConstVal(), Align);
 321     MI->addOperand(MachineOperand::CreateCPI(Idx, Offset));
 322   } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
 323     MI->addOperand(MachineOperand::CreateES(ES->getSymbol()));
 324   } else {
 325     assert(Op.getValueType() != MVT::Other &&
 326            Op.getValueType() != MVT::Flag &&
 327            "Chain and flag operands should occur at end of operand list!");
 328     AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
 329   }
 330 }
 331
 332 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
 333 /// "SubIdx"'th sub-register class is the specified register class and whose
 334 /// type matches the specified type.
 335 static const TargetRegisterClass*
 336 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
 337                          unsigned SubIdx, MVT VT) {
 338   // Pick the register class of the superegister for this type
 339   for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
 340          E = TRC->superregclasses_end(); I != E; ++I)
 341     if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
 342       return *I;
 343   assert(false && "Couldn't find the register class");
 344   return 0;
 345 }
 346
 347 /// EmitSubregNode - Generate machine code for subreg nodes.
 348 ///
 349 void ScheduleDAGSDNodes::EmitSubregNode(SDNode *Node,
 350                                         DenseMap<SDValue, unsigned> &VRBaseMap) {
 351   unsigned VRBase = 0;
 352   unsigned Opc = Node->getMachineOpcode();
 353
 354   // If the node is only used by a CopyToReg and the dest reg is a vreg, use
 355   // the CopyToReg'd destination register instead of creating a new vreg.
 356   for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
 357        UI != E; ++UI) {
 358     SDNode *User = *UI;
 359     if (User->getOpcode() == ISD::CopyToReg &&
 360         User->getOperand(2).getNode() == Node) {
 361       unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
 362       if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
 363         VRBase = DestReg;
 364         break;
 365       }
 366     }
 367   }
 368
 369   if (Opc == TargetInstrInfo::EXTRACT_SUBREG) {
 370     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 371
 372     // Create the extract_subreg machine instruction.
 373     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
 374                                TII->get(TargetInstrInfo::EXTRACT_SUBREG));
 375
 376     // Figure out the register class to create for the destreg.
 377     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 378     const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
 379     const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
 380     assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
 381
 382     // Figure out the register class to create for the destreg.
 383     // Note that if we're going to directly use an existing register,
 384     // it must be precisely the required class, and not a subclass
 385     // thereof.
 386     if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
 387       // Create the reg
 388       assert(SRC && "Couldn't find source register class");
 389       VRBase = MRI.createVirtualRegister(SRC);
 390     }
 391
 392     // Add def, source, and subreg index
 393     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 394     AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
 395     MI->addOperand(MachineOperand::CreateImm(SubIdx));
 396     BB->insert(InsertPos, MI);
 397   } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
 398              Opc == TargetInstrInfo::SUBREG_TO_REG) {
 399     SDValue N0 = Node->getOperand(0);
 400     SDValue N1 = Node->getOperand(1);
 401     SDValue N2 = Node->getOperand(2);
 402     unsigned SubReg = getVR(N1, VRBaseMap);
 403     unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
 404     const TargetRegisterClass *TRC = MRI.getRegClass(SubReg);
 405     const TargetRegisterClass *SRC =
 406       getSuperRegisterRegClass(TRC, SubIdx,
 407                                Node->getValueType(0));
 408
 409     // Figure out the register class to create for the destreg.
 410     // Note that if we're going to directly use an existing register,
 411     // it must be precisely the required class, and not a subclass
 412     // thereof.
 413     if (VRBase == 0 || SRC != MRI.getRegClass(VRBase)) {
 414       // Create the reg
 415       assert(SRC && "Couldn't find source register class");
 416       VRBase = MRI.createVirtualRegister(SRC);
 417     }
 418
 419     // Create the insert_subreg or subreg_to_reg machine instruction.
 420     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), TII->get(Opc));
 421     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
 422
 423     // If creating a subreg_to_reg, then the first input operand
 424     // is an implicit value immediate, otherwise it's a register
 425     if (Opc == TargetInstrInfo::SUBREG_TO_REG) {
 426       const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
 427       MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
 428     } else
 429       AddOperand(MI, N0, 0, 0, VRBaseMap);
 430     // Add the subregster being inserted
 431     AddOperand(MI, N1, 0, 0, VRBaseMap);
 432     MI->addOperand(MachineOperand::CreateImm(SubIdx));
 433     BB->insert(InsertPos, MI);
 434   } else
 435     assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
 436
 437   SDValue Op(Node, 0);
 438   bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
 439   isNew = isNew; // Silence compiler warning.
 440   assert(isNew && "Node emitted out of order - early");
 441 }
 442
 443 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
 444 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
 445 /// register is constrained to be in a particular register class.
 446 ///
 447 void
 448 ScheduleDAGSDNodes::EmitCopyToRegClassNode(SDNode *Node,
 449                                        DenseMap<SDValue, unsigned> &VRBaseMap) {
 450   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 451   const TargetRegisterClass *SrcRC = MRI.getRegClass(VReg);
 452
 453   unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
 454   const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
 455
 456   // Create the new VReg in the destination class and emit a copy.
 457   unsigned NewVReg = MRI.createVirtualRegister(DstRC);
 458   bool Emitted = TII->copyRegToReg(*BB, InsertPos, NewVReg, VReg,
 459                                    DstRC, SrcRC);
 460   assert(Emitted &&
 461          "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
 462
 463   SDValue Op(Node, 0);
 464   bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
 465   isNew = isNew; // Silence compiler warning.
 466   assert(isNew && "Node emitted out of order - early");
 467 }
 468
 469 /// EmitNode - Generate machine code for an node and needed dependencies.
 470 ///
 471 void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
 472                                   DenseMap<SDValue, unsigned> &VRBaseMap) {
 473   // If machine instruction
 474   if (Node->isMachineOpcode()) {
 475     unsigned Opc = Node->getMachineOpcode();
 476
 477     // Handle subreg insert/extract specially
 478     if (Opc == TargetInstrInfo::EXTRACT_SUBREG ||
 479         Opc == TargetInstrInfo::INSERT_SUBREG ||
 480         Opc == TargetInstrInfo::SUBREG_TO_REG) {
 481       EmitSubregNode(Node, VRBaseMap);
 482       return;
 483     }
 484
 485     // Handle COPY_TO_REGCLASS specially.
 486     if (Opc == TargetInstrInfo::COPY_TO_REGCLASS) {
 487       EmitCopyToRegClassNode(Node, VRBaseMap);
 488       return;
 489     }
 490
 491     if (Opc == TargetInstrInfo::IMPLICIT_DEF)
 492       // We want a unique VR for each IMPLICIT_DEF use.
 493       return;
 494
 495     const TargetInstrDesc &II = TII->get(Opc);
 496     unsigned NumResults = CountResults(Node);
 497     unsigned NodeOperands = CountOperands(Node);
 498     unsigned MemOperandsEnd = ComputeMemOperandsEnd(Node);
 499     bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
 500                           II.getImplicitDefs() != 0;
 501 #ifndef NDEBUG
 502     unsigned NumMIOperands = NodeOperands + NumResults;
 503     assert((II.getNumOperands() == NumMIOperands ||
 504             HasPhysRegOuts || II.isVariadic()) &&
 505            "#operands for dag node doesn't match .td file!");
 506 #endif
 507
 508     // Create the new machine instruction.
 509     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(), II);
 510
 511     // Add result register values for things that are defined by this
 512     // instruction.
 513     if (NumResults)
 514       CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
 515
 516     // Emit all of the actual operands of this instruction, adding them to the
 517     // instruction as appropriate.
 518     for (unsigned i = 0; i != NodeOperands; ++i)
 519       AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
 520
 521     // Emit all of the memory operands of this instruction
 522     for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
 523       AddMemOperand(MI, cast<MemOperandSDNode>(Node->getOperand(i))->MO);
 524
 525     if (II.usesCustomDAGSchedInsertionHook()) {
 526       // Insert this instruction into the basic block using a target
 527       // specific inserter which may returns a new basic block.
 528       BB = TLI->EmitInstrWithCustomInserter(MI, BB);
 529       InsertPos = BB->end();
 530     } else {
 531       BB->insert(InsertPos, MI);
 532     }
 533
 534     // Additional results must be an physical register def.
 535     if (HasPhysRegOuts) {
 536       for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
 537         unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
 538         if (Node->hasAnyUseOfValue(i))
 539           EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
 540       }
 541     }
 542     return;
 543   }
 544
 545   switch (Node->getOpcode()) {
 546   default:
 547 #ifndef NDEBUG
 548     Node->dump(DAG);
 549 #endif
 550     assert(0 && "This target-independent node should have been selected!");
 551     break;
 552   case ISD::EntryToken:
 553     assert(0 && "EntryToken should have been excluded from the schedule!");
 554     break;
 555   case ISD::TokenFactor: // fall thru
 556     break;
 557   case ISD::CopyToReg: {
 558     unsigned SrcReg;
 559     SDValue SrcVal = Node->getOperand(2);
 560     if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
 561       SrcReg = R->getReg();
 562     else
 563       SrcReg = getVR(SrcVal, VRBaseMap);
 564
 565     unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 566     if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
 567       break;
 568
 569     const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
 570     // Get the register classes of the src/dst.
 571     if (TargetRegisterInfo::isVirtualRegister(SrcReg))
 572       SrcTRC = MRI.getRegClass(SrcReg);
 573     else
 574       SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
 575
 576     if (TargetRegisterInfo::isVirtualRegister(DestReg))
 577       DstTRC = MRI.getRegClass(DestReg);
 578     else
 579       DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
 580                                             Node->getOperand(1).getValueType());
 581
 582     bool Emitted = TII->copyRegToReg(*BB, InsertPos, DestReg, SrcReg,
 583                                      DstTRC, SrcTRC);
 584     assert(Emitted && "Unable to issue a copy instruction!\n");
 585     break;
 586   }
 587   case ISD::CopyFromReg: {
 588     unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
 589     EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
 590     break;
 591   }
 592   case ISD::INLINEASM: {
 593     unsigned NumOps = Node->getNumOperands();
 594     if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
 595       --NumOps;  // Ignore the flag operand.
 596
 597     // Create the inline asm machine instruction.
 598     MachineInstr *MI = BuildMI(MF, Node->getDebugLoc(),
 599                                TII->get(TargetInstrInfo::INLINEASM));
 600
 601     // Add the asm string as an external symbol operand.
 602     const char *AsmStr =
 603       cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
 604     MI->addOperand(MachineOperand::CreateES(AsmStr));
 605
 606     // Add all of the operand registers to the instruction.
 607     for (unsigned i = 2; i != NumOps;) {
 608       unsigned Flags =
 609         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
 610       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 611
 612       MI->addOperand(MachineOperand::CreateImm(Flags));
 613       ++i;  // Skip the ID value.
 614
 615       switch (Flags & 7) {
 616       default: assert(0 && "Bad flags!");
 617       case 2:   // Def of register.
 618         for (; NumVals; --NumVals, ++i) {
 619           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 620           MI->addOperand(MachineOperand::CreateReg(Reg, true));
 621         }
 622         break;
 623       case 6:   // Def of earlyclobber register.
 624         for (; NumVals; --NumVals, ++i) {
 625           unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
 626           MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
 627                                                    false, 0, true));
 628         }
 629         break;
 630       case 1:  // Use of register.
 631       case 3:  // Immediate.
 632       case 4:  // Addressing mode.
 633         // The addressing mode has been selected, just add all of the
 634         // operands to the machine instruction.
 635         for (; NumVals; --NumVals, ++i)
 636           AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
 637         break;
 638       }
 639     }
 640     BB->insert(InsertPos, MI);
 641     break;
 642   }
 643   }
 644 }
 645
 646 /// EmitSchedule - Emit the machine code in scheduled order.
 647 MachineBasicBlock *ScheduleDAGSDNodes::EmitSchedule() {
 648   DenseMap<SDValue, unsigned> VRBaseMap;
 649   DenseMap<SUnit*, unsigned> CopyVRBaseMap;
 650   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
 651     SUnit *SU = Sequence[i];
 652     if (!SU) {
 653       // Null SUnit* is a noop.
 654       EmitNoop();
 655       continue;
 656     }
 657
 658     // For pre-regalloc scheduling, create instructions corresponding to the
 659     // SDNode and any flagged SDNodes and append them to the block.
 660     if (!SU->getNode()) {
 661       // Emit a copy.
 662       EmitPhysRegCopy(SU, CopyVRBaseMap);
 663       continue;
 664     }
 665
 666     SmallVector<SDNode *, 4> FlaggedNodes;
 667     for (SDNode *N = SU->getNode()->getFlaggedNode(); N;
 668          N = N->getFlaggedNode())
 669       FlaggedNodes.push_back(N);
 670     while (!FlaggedNodes.empty()) {
 671       EmitNode(FlaggedNodes.back(), SU->OrigNode != SU, SU->isCloned,VRBaseMap);
 672       FlaggedNodes.pop_back();
 673     }
 674     EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned, VRBaseMap);
 675   }
 676
 677   return BB;
 678 }