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We're not going to spend 100% of time in interrupts, do we? :)
[llvm/msp430.git] / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob0e5e0c066ce297966e3760744db3091b5c0696b8
1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/Target/TargetAsmInfo.h"
15 #include "llvm/Target/TargetLowering.h"
16 #include "llvm/Target/TargetSubtarget.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 #include "llvm/GlobalVariable.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/Support/MathExtras.h"
27 using namespace llvm;
28
29 namespace llvm {
30 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
31 bool isLocal = GV->hasLocalLinkage();
32 bool isDeclaration = GV->isDeclaration();
33 // FIXME: what should we do for protected and internal visibility?
34 // For variables, is internal different from hidden?
35 bool isHidden = GV->hasHiddenVisibility();
36
37 if (reloc == Reloc::PIC_) {
38 if (isLocal || isHidden)
39 return TLSModel::LocalDynamic;
40 else
41 return TLSModel::GeneralDynamic;
42 } else {
43 if (!isDeclaration || isHidden)
44 return TLSModel::LocalExec;
45 else
46 return TLSModel::InitialExec;
47 }
48 }
49 }
50
51 /// InitLibcallNames - Set default libcall names.
52 ///
53 static void InitLibcallNames(const char **Names) {
54 Names[RTLIB::SHL_I16] = "__ashli16";
55 Names[RTLIB::SHL_I32] = "__ashlsi3";
56 Names[RTLIB::SHL_I64] = "__ashldi3";
57 Names[RTLIB::SHL_I128] = "__ashlti3";
58 Names[RTLIB::SRL_I16] = "__lshri16";
59 Names[RTLIB::SRL_I32] = "__lshrsi3";
60 Names[RTLIB::SRL_I64] = "__lshrdi3";
61 Names[RTLIB::SRL_I128] = "__lshrti3";
62 Names[RTLIB::SRA_I16] = "__ashri16";
63 Names[RTLIB::SRA_I32] = "__ashrsi3";
64 Names[RTLIB::SRA_I64] = "__ashrdi3";
65 Names[RTLIB::SRA_I128] = "__ashrti3";
66 Names[RTLIB::MUL_I16] = "__muli16";
67 Names[RTLIB::MUL_I32] = "__mulsi3";
68 Names[RTLIB::MUL_I64] = "__muldi3";
69 Names[RTLIB::MUL_I128] = "__multi3";
70 Names[RTLIB::SDIV_I32] = "__divsi3";
71 Names[RTLIB::SDIV_I64] = "__divdi3";
72 Names[RTLIB::SDIV_I128] = "__divti3";
73 Names[RTLIB::UDIV_I32] = "__udivsi3";
74 Names[RTLIB::UDIV_I64] = "__udivdi3";
75 Names[RTLIB::UDIV_I128] = "__udivti3";
76 Names[RTLIB::SREM_I32] = "__modsi3";
77 Names[RTLIB::SREM_I64] = "__moddi3";
78 Names[RTLIB::SREM_I128] = "__modti3";
79 Names[RTLIB::UREM_I32] = "__umodsi3";
80 Names[RTLIB::UREM_I64] = "__umoddi3";
81 Names[RTLIB::UREM_I128] = "__umodti3";
82 Names[RTLIB::NEG_I32] = "__negsi2";
83 Names[RTLIB::NEG_I64] = "__negdi2";
84 Names[RTLIB::ADD_F32] = "__addsf3";
85 Names[RTLIB::ADD_F64] = "__adddf3";
86 Names[RTLIB::ADD_F80] = "__addxf3";
87 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
88 Names[RTLIB::SUB_F32] = "__subsf3";
89 Names[RTLIB::SUB_F64] = "__subdf3";
90 Names[RTLIB::SUB_F80] = "__subxf3";
91 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
92 Names[RTLIB::MUL_F32] = "__mulsf3";
93 Names[RTLIB::MUL_F64] = "__muldf3";
94 Names[RTLIB::MUL_F80] = "__mulxf3";
95 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
96 Names[RTLIB::DIV_F32] = "__divsf3";
97 Names[RTLIB::DIV_F64] = "__divdf3";
98 Names[RTLIB::DIV_F80] = "__divxf3";
99 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
100 Names[RTLIB::REM_F32] = "fmodf";
101 Names[RTLIB::REM_F64] = "fmod";
102 Names[RTLIB::REM_F80] = "fmodl";
103 Names[RTLIB::REM_PPCF128] = "fmodl";
104 Names[RTLIB::POWI_F32] = "__powisf2";
105 Names[RTLIB::POWI_F64] = "__powidf2";
106 Names[RTLIB::POWI_F80] = "__powixf2";
107 Names[RTLIB::POWI_PPCF128] = "__powitf2";
108 Names[RTLIB::SQRT_F32] = "sqrtf";
109 Names[RTLIB::SQRT_F64] = "sqrt";
110 Names[RTLIB::SQRT_F80] = "sqrtl";
111 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
112 Names[RTLIB::LOG_F32] = "logf";
113 Names[RTLIB::LOG_F64] = "log";
114 Names[RTLIB::LOG_F80] = "logl";
115 Names[RTLIB::LOG_PPCF128] = "logl";
116 Names[RTLIB::LOG2_F32] = "log2f";
117 Names[RTLIB::LOG2_F64] = "log2";
118 Names[RTLIB::LOG2_F80] = "log2l";
119 Names[RTLIB::LOG2_PPCF128] = "log2l";
120 Names[RTLIB::LOG10_F32] = "log10f";
121 Names[RTLIB::LOG10_F64] = "log10";
122 Names[RTLIB::LOG10_F80] = "log10l";
123 Names[RTLIB::LOG10_PPCF128] = "log10l";
124 Names[RTLIB::EXP_F32] = "expf";
125 Names[RTLIB::EXP_F64] = "exp";
126 Names[RTLIB::EXP_F80] = "expl";
127 Names[RTLIB::EXP_PPCF128] = "expl";
128 Names[RTLIB::EXP2_F32] = "exp2f";
129 Names[RTLIB::EXP2_F64] = "exp2";
130 Names[RTLIB::EXP2_F80] = "exp2l";
131 Names[RTLIB::EXP2_PPCF128] = "exp2l";
132 Names[RTLIB::SIN_F32] = "sinf";
133 Names[RTLIB::SIN_F64] = "sin";
134 Names[RTLIB::SIN_F80] = "sinl";
135 Names[RTLIB::SIN_PPCF128] = "sinl";
136 Names[RTLIB::COS_F32] = "cosf";
137 Names[RTLIB::COS_F64] = "cos";
138 Names[RTLIB::COS_F80] = "cosl";
139 Names[RTLIB::COS_PPCF128] = "cosl";
140 Names[RTLIB::POW_F32] = "powf";
141 Names[RTLIB::POW_F64] = "pow";
142 Names[RTLIB::POW_F80] = "powl";
143 Names[RTLIB::POW_PPCF128] = "powl";
144 Names[RTLIB::CEIL_F32] = "ceilf";
145 Names[RTLIB::CEIL_F64] = "ceil";
146 Names[RTLIB::CEIL_F80] = "ceill";
147 Names[RTLIB::CEIL_PPCF128] = "ceill";
148 Names[RTLIB::TRUNC_F32] = "truncf";
149 Names[RTLIB::TRUNC_F64] = "trunc";
150 Names[RTLIB::TRUNC_F80] = "truncl";
151 Names[RTLIB::TRUNC_PPCF128] = "truncl";
152 Names[RTLIB::RINT_F32] = "rintf";
153 Names[RTLIB::RINT_F64] = "rint";
154 Names[RTLIB::RINT_F80] = "rintl";
155 Names[RTLIB::RINT_PPCF128] = "rintl";
156 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
157 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
158 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
159 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
160 Names[RTLIB::FLOOR_F32] = "floorf";
161 Names[RTLIB::FLOOR_F64] = "floor";
162 Names[RTLIB::FLOOR_F80] = "floorl";
163 Names[RTLIB::FLOOR_PPCF128] = "floorl";
164 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
165 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
166 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
167 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
168 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
169 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
170 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
171 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
172 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
173 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
174 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
175 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
176 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
177 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
178 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
179 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
180 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
181 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
182 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
183 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
184 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
185 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
186 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
187 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
188 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
189 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
190 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
191 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
192 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
193 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
194 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
195 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
196 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
197 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
198 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
199 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
200 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
201 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
202 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
203 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
204 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
205 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
206 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
207 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
208 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
209 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
210 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
211 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
212 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
213 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
214 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
215 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
216 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
217 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
218 Names[RTLIB::OEQ_F32] = "__eqsf2";
219 Names[RTLIB::OEQ_F64] = "__eqdf2";
220 Names[RTLIB::UNE_F32] = "__nesf2";
221 Names[RTLIB::UNE_F64] = "__nedf2";
222 Names[RTLIB::OGE_F32] = "__gesf2";
223 Names[RTLIB::OGE_F64] = "__gedf2";
224 Names[RTLIB::OLT_F32] = "__ltsf2";
225 Names[RTLIB::OLT_F64] = "__ltdf2";
226 Names[RTLIB::OLE_F32] = "__lesf2";
227 Names[RTLIB::OLE_F64] = "__ledf2";
228 Names[RTLIB::OGT_F32] = "__gtsf2";
229 Names[RTLIB::OGT_F64] = "__gtdf2";
230 Names[RTLIB::UO_F32] = "__unordsf2";
231 Names[RTLIB::UO_F64] = "__unorddf2";
232 Names[RTLIB::O_F32] = "__unordsf2";
233 Names[RTLIB::O_F64] = "__unorddf2";
234 }
235
236 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
237 /// UNKNOWN_LIBCALL if there is none.
238 RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) {
239 if (OpVT == MVT::f32) {
240 if (RetVT == MVT::f64)
241 return FPEXT_F32_F64;
242 }
243 return UNKNOWN_LIBCALL;
244 }
245
246 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
247 /// UNKNOWN_LIBCALL if there is none.
248 RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) {
249 if (RetVT == MVT::f32) {
250 if (OpVT == MVT::f64)
251 return FPROUND_F64_F32;
252 if (OpVT == MVT::f80)
253 return FPROUND_F80_F32;
254 if (OpVT == MVT::ppcf128)
255 return FPROUND_PPCF128_F32;
256 } else if (RetVT == MVT::f64) {
257 if (OpVT == MVT::f80)
258 return FPROUND_F80_F64;
259 if (OpVT == MVT::ppcf128)
260 return FPROUND_PPCF128_F64;
261 }
262 return UNKNOWN_LIBCALL;
263 }
264
265 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
266 /// UNKNOWN_LIBCALL if there is none.
267 RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) {
268 if (OpVT == MVT::f32) {
269 if (RetVT == MVT::i32)
270 return FPTOSINT_F32_I32;
271 if (RetVT == MVT::i64)
272 return FPTOSINT_F32_I64;
273 if (RetVT == MVT::i128)
274 return FPTOSINT_F32_I128;
275 } else if (OpVT == MVT::f64) {
276 if (RetVT == MVT::i32)
277 return FPTOSINT_F64_I32;
278 if (RetVT == MVT::i64)
279 return FPTOSINT_F64_I64;
280 if (RetVT == MVT::i128)
281 return FPTOSINT_F64_I128;
282 } else if (OpVT == MVT::f80) {
283 if (RetVT == MVT::i32)
284 return FPTOSINT_F80_I32;
285 if (RetVT == MVT::i64)
286 return FPTOSINT_F80_I64;
287 if (RetVT == MVT::i128)
288 return FPTOSINT_F80_I128;
289 } else if (OpVT == MVT::ppcf128) {
290 if (RetVT == MVT::i32)
291 return FPTOSINT_PPCF128_I32;
292 if (RetVT == MVT::i64)
293 return FPTOSINT_PPCF128_I64;
294 if (RetVT == MVT::i128)
295 return FPTOSINT_PPCF128_I128;
296 }
297 return UNKNOWN_LIBCALL;
298 }
299
300 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
301 /// UNKNOWN_LIBCALL if there is none.
302 RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) {
303 if (OpVT == MVT::f32) {
304 if (RetVT == MVT::i32)
305 return FPTOUINT_F32_I32;
306 if (RetVT == MVT::i64)
307 return FPTOUINT_F32_I64;
308 if (RetVT == MVT::i128)
309 return FPTOUINT_F32_I128;
310 } else if (OpVT == MVT::f64) {
311 if (RetVT == MVT::i32)
312 return FPTOUINT_F64_I32;
313 if (RetVT == MVT::i64)
314 return FPTOUINT_F64_I64;
315 if (RetVT == MVT::i128)
316 return FPTOUINT_F64_I128;
317 } else if (OpVT == MVT::f80) {
318 if (RetVT == MVT::i32)
319 return FPTOUINT_F80_I32;
320 if (RetVT == MVT::i64)
321 return FPTOUINT_F80_I64;
322 if (RetVT == MVT::i128)
323 return FPTOUINT_F80_I128;
324 } else if (OpVT == MVT::ppcf128) {
325 if (RetVT == MVT::i32)
326 return FPTOUINT_PPCF128_I32;
327 if (RetVT == MVT::i64)
328 return FPTOUINT_PPCF128_I64;
329 if (RetVT == MVT::i128)
330 return FPTOUINT_PPCF128_I128;
331 }
332 return UNKNOWN_LIBCALL;
333 }
334
335 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
336 /// UNKNOWN_LIBCALL if there is none.
337 RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) {
338 if (OpVT == MVT::i32) {
339 if (RetVT == MVT::f32)
340 return SINTTOFP_I32_F32;
341 else if (RetVT == MVT::f64)
342 return SINTTOFP_I32_F64;
343 else if (RetVT == MVT::f80)
344 return SINTTOFP_I32_F80;
345 else if (RetVT == MVT::ppcf128)
346 return SINTTOFP_I32_PPCF128;
347 } else if (OpVT == MVT::i64) {
348 if (RetVT == MVT::f32)
349 return SINTTOFP_I64_F32;
350 else if (RetVT == MVT::f64)
351 return SINTTOFP_I64_F64;
352 else if (RetVT == MVT::f80)
353 return SINTTOFP_I64_F80;
354 else if (RetVT == MVT::ppcf128)
355 return SINTTOFP_I64_PPCF128;
356 } else if (OpVT == MVT::i128) {
357 if (RetVT == MVT::f32)
358 return SINTTOFP_I128_F32;
359 else if (RetVT == MVT::f64)
360 return SINTTOFP_I128_F64;
361 else if (RetVT == MVT::f80)
362 return SINTTOFP_I128_F80;
363 else if (RetVT == MVT::ppcf128)
364 return SINTTOFP_I128_PPCF128;
365 }
366 return UNKNOWN_LIBCALL;
367 }
368
369 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
370 /// UNKNOWN_LIBCALL if there is none.
371 RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) {
372 if (OpVT == MVT::i32) {
373 if (RetVT == MVT::f32)
374 return UINTTOFP_I32_F32;
375 else if (RetVT == MVT::f64)
376 return UINTTOFP_I32_F64;
377 else if (RetVT == MVT::f80)
378 return UINTTOFP_I32_F80;
379 else if (RetVT == MVT::ppcf128)
380 return UINTTOFP_I32_PPCF128;
381 } else if (OpVT == MVT::i64) {
382 if (RetVT == MVT::f32)
383 return UINTTOFP_I64_F32;
384 else if (RetVT == MVT::f64)
385 return UINTTOFP_I64_F64;
386 else if (RetVT == MVT::f80)
387 return UINTTOFP_I64_F80;
388 else if (RetVT == MVT::ppcf128)
389 return UINTTOFP_I64_PPCF128;
390 } else if (OpVT == MVT::i128) {
391 if (RetVT == MVT::f32)
392 return UINTTOFP_I128_F32;
393 else if (RetVT == MVT::f64)
394 return UINTTOFP_I128_F64;
395 else if (RetVT == MVT::f80)
396 return UINTTOFP_I128_F80;
397 else if (RetVT == MVT::ppcf128)
398 return UINTTOFP_I128_PPCF128;
399 }
400 return UNKNOWN_LIBCALL;
401 }
402
403 /// InitCmpLibcallCCs - Set default comparison libcall CC.
404 ///
405 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
406 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
407 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
408 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
409 CCs[RTLIB::UNE_F32] = ISD::SETNE;
410 CCs[RTLIB::UNE_F64] = ISD::SETNE;
411 CCs[RTLIB::OGE_F32] = ISD::SETGE;
412 CCs[RTLIB::OGE_F64] = ISD::SETGE;
413 CCs[RTLIB::OLT_F32] = ISD::SETLT;
414 CCs[RTLIB::OLT_F64] = ISD::SETLT;
415 CCs[RTLIB::OLE_F32] = ISD::SETLE;
416 CCs[RTLIB::OLE_F64] = ISD::SETLE;
417 CCs[RTLIB::OGT_F32] = ISD::SETGT;
418 CCs[RTLIB::OGT_F64] = ISD::SETGT;
419 CCs[RTLIB::UO_F32] = ISD::SETNE;
420 CCs[RTLIB::UO_F64] = ISD::SETNE;
421 CCs[RTLIB::O_F32] = ISD::SETEQ;
422 CCs[RTLIB::O_F64] = ISD::SETEQ;
423 }
424
425 TargetLowering::TargetLowering(TargetMachine &tm)
426 : TM(tm), TD(TM.getTargetData()) {
427 // All operations default to being supported.
428 memset(OpActions, 0, sizeof(OpActions));
429 memset(LoadExtActions, 0, sizeof(LoadExtActions));
430 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
431 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
432 memset(ConvertActions, 0, sizeof(ConvertActions));
433 memset(CondCodeActions, 0, sizeof(CondCodeActions));
434
435 // Set default actions for various operations.
436 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
437 // Default all indexed load / store to expand.
438 for (unsigned IM = (unsigned)ISD::PRE_INC;
439 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
440 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
441 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
442 }
443
444 // These operations default to expand.
445 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
446 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
447 }
448
449 // Most targets ignore the @llvm.prefetch intrinsic.
450 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
451
452 // ConstantFP nodes default to expand. Targets can either change this to
453 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
454 // to optimize expansions for certain constants.
455 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
456 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
457 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
458
459 // These library functions default to expand.
460 setOperationAction(ISD::FLOG , MVT::f64, Expand);
461 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
462 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
463 setOperationAction(ISD::FEXP , MVT::f64, Expand);
464 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
465 setOperationAction(ISD::FLOG , MVT::f32, Expand);
466 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
467 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
468 setOperationAction(ISD::FEXP , MVT::f32, Expand);
469 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
470
471 // Default ISD::TRAP to expand (which turns it into abort).
472 setOperationAction(ISD::TRAP, MVT::Other, Expand);
473
474 IsLittleEndian = TD->isLittleEndian();
475 UsesGlobalOffsetTable = false;
476 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
477 ShiftAmtHandling = Undefined;
478 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
479 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
480 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
481 allowUnalignedMemoryAccesses = false;
482 UseUnderscoreSetJmp = false;
483 UseUnderscoreLongJmp = false;
484 SelectIsExpensive = false;
485 IntDivIsCheap = false;
486 Pow2DivIsCheap = false;
487 StackPointerRegisterToSaveRestore = 0;
488 ExceptionPointerRegister = 0;
489 ExceptionSelectorRegister = 0;
490 BooleanContents = UndefinedBooleanContent;
491 SchedPreferenceInfo = SchedulingForLatency;
492 JumpBufSize = 0;
493 JumpBufAlignment = 0;
494 IfCvtBlockSizeLimit = 2;
495 IfCvtDupBlockSizeLimit = 0;
496 PrefLoopAlignment = 0;
497
498 InitLibcallNames(LibcallRoutineNames);
499 InitCmpLibcallCCs(CmpLibcallCCs);
500
501 // Tell Legalize whether the assembler supports DEBUG_LOC.
502 const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
503 if (!TASM || !TASM->hasDotLocAndDotFile())
504 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
505 }
506
507 TargetLowering::~TargetLowering() {}
508
509 /// computeRegisterProperties - Once all of the register classes are added,
510 /// this allows us to compute derived properties we expose.
511 void TargetLowering::computeRegisterProperties() {
512 assert(MVT::LAST_VALUETYPE <= 32 &&
513 "Too many value types for ValueTypeActions to hold!");
514
515 // Everything defaults to needing one register.
516 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
517 NumRegistersForVT[i] = 1;
518 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
519 }
520 // ...except isVoid, which doesn't need any registers.
521 NumRegistersForVT[MVT::isVoid] = 0;
522
523 // Find the largest integer register class.
524 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
525 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
526 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
527
528 // Every integer value type larger than this largest register takes twice as
529 // many registers to represent as the previous ValueType.
530 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
531 MVT EVT = (MVT::SimpleValueType)ExpandedReg;
532 if (!EVT.isInteger())
533 break;
534 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
535 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
536 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
537 ValueTypeActions.setTypeAction(EVT, Expand);
538 }
539
540 // Inspect all of the ValueType's smaller than the largest integer
541 // register to see which ones need promotion.
542 unsigned LegalIntReg = LargestIntReg;
543 for (unsigned IntReg = LargestIntReg - 1;
544 IntReg >= (unsigned)MVT::i1; --IntReg) {
545 MVT IVT = (MVT::SimpleValueType)IntReg;
546 if (isTypeLegal(IVT)) {
547 LegalIntReg = IntReg;
548 } else {
549 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
550 (MVT::SimpleValueType)LegalIntReg;
551 ValueTypeActions.setTypeAction(IVT, Promote);
552 }
553 }
554
555 // ppcf128 type is really two f64's.
556 if (!isTypeLegal(MVT::ppcf128)) {
557 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
558 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
559 TransformToType[MVT::ppcf128] = MVT::f64;
560 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
561 }
562
563 // Decide how to handle f64. If the target does not have native f64 support,
564 // expand it to i64 and we will be generating soft float library calls.
565 if (!isTypeLegal(MVT::f64)) {
566 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
567 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
568 TransformToType[MVT::f64] = MVT::i64;
569 ValueTypeActions.setTypeAction(MVT::f64, Expand);
570 }
571
572 // Decide how to handle f32. If the target does not have native support for
573 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
574 if (!isTypeLegal(MVT::f32)) {
575 if (isTypeLegal(MVT::f64)) {
576 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
577 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
578 TransformToType[MVT::f32] = MVT::f64;
579 ValueTypeActions.setTypeAction(MVT::f32, Promote);
580 } else {
581 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
582 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
583 TransformToType[MVT::f32] = MVT::i32;
584 ValueTypeActions.setTypeAction(MVT::f32, Expand);
585 }
586 }
587
588 // Loop over all of the vector value types to see which need transformations.
589 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
590 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
591 MVT VT = (MVT::SimpleValueType)i;
592 if (!isTypeLegal(VT)) {
593 MVT IntermediateVT, RegisterVT;
594 unsigned NumIntermediates;
595 NumRegistersForVT[i] =
596 getVectorTypeBreakdown(VT,
597 IntermediateVT, NumIntermediates,
598 RegisterVT);
599 RegisterTypeForVT[i] = RegisterVT;
600
601 // Determine if there is a legal wider type.
602 bool IsLegalWiderType = false;
603 MVT EltVT = VT.getVectorElementType();
604 unsigned NElts = VT.getVectorNumElements();
605 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
606 MVT SVT = (MVT::SimpleValueType)nVT;
607 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
608 SVT.getVectorNumElements() > NElts) {
609 TransformToType[i] = SVT;
610 ValueTypeActions.setTypeAction(VT, Promote);
611 IsLegalWiderType = true;
612 break;
613 }
614 }
615 if (!IsLegalWiderType) {
616 MVT NVT = VT.getPow2VectorType();
617 if (NVT == VT) {
618 // Type is already a power of 2. The default action is to split.
619 TransformToType[i] = MVT::Other;
620 ValueTypeActions.setTypeAction(VT, Expand);
621 } else {
622 TransformToType[i] = NVT;
623 ValueTypeActions.setTypeAction(VT, Promote);
624 }
625 }
626 }
627 }
628 }
629
630 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
631 return NULL;
632 }
633
634
635 MVT TargetLowering::getSetCCResultType(MVT VT) const {
636 return getValueType(TD->getIntPtrType());
637 }
638
639
640 /// getVectorTypeBreakdown - Vector types are broken down into some number of
641 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
642 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
643 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
644 ///
645 /// This method returns the number of registers needed, and the VT for each
646 /// register. It also returns the VT and quantity of the intermediate values
647 /// before they are promoted/expanded.
648 ///
649 unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
650 MVT &IntermediateVT,
651 unsigned &NumIntermediates,
652 MVT &RegisterVT) const {
653 // Figure out the right, legal destination reg to copy into.
654 unsigned NumElts = VT.getVectorNumElements();
655 MVT EltTy = VT.getVectorElementType();
656
657 unsigned NumVectorRegs = 1;
658
659 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
660 // could break down into LHS/RHS like LegalizeDAG does.
661 if (!isPowerOf2_32(NumElts)) {
662 NumVectorRegs = NumElts;
663 NumElts = 1;
664 }
665
666 // Divide the input until we get to a supported size. This will always
667 // end with a scalar if the target doesn't support vectors.
668 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
669 NumElts >>= 1;
670 NumVectorRegs <<= 1;
671 }
672
673 NumIntermediates = NumVectorRegs;
674
675 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
676 if (!isTypeLegal(NewVT))
677 NewVT = EltTy;
678 IntermediateVT = NewVT;
679
680 MVT DestVT = getRegisterType(NewVT);
681 RegisterVT = DestVT;
682 if (DestVT.bitsLT(NewVT)) {
683 // Value is expanded, e.g. i64 -> i16.
684 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
685 } else {
686 // Otherwise, promotion or legal types use the same number of registers as
687 // the vector decimated to the appropriate level.
688 return NumVectorRegs;
689 }
690
691 return 1;
692 }
693
694 /// getWidenVectorType: given a vector type, returns the type to widen to
695 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
696 /// If there is no vector type that we want to widen to, returns MVT::Other
697 /// When and where to widen is target dependent based on the cost of
698 /// scalarizing vs using the wider vector type.
699 MVT TargetLowering::getWidenVectorType(MVT VT) const {
700 assert(VT.isVector());
701 if (isTypeLegal(VT))
702 return VT;
703
704 // Default is not to widen until moved to LegalizeTypes
705 return MVT::Other;
706 }
707
708 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
709 /// function arguments in the caller parameter area. This is the actual
710 /// alignment, not its logarithm.
711 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
712 return TD->getCallFrameTypeAlignment(Ty);
713 }
714
715 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
716 SelectionDAG &DAG) const {
717 if (usesGlobalOffsetTable())
718 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
719 return Table;
720 }
721
722 bool
723 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
724 // Assume that everything is safe in static mode.
725 if (getTargetMachine().getRelocationModel() == Reloc::Static)
726 return true;
727
728 // In dynamic-no-pic mode, assume that known defined values are safe.
729 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
730 GA &&
731 !GA->getGlobal()->isDeclaration() &&
732 !GA->getGlobal()->isWeakForLinker())
733 return true;
734
735 // Otherwise assume nothing is safe.
736 return false;
737 }
738
739 //===----------------------------------------------------------------------===//
740 // Optimization Methods
741 //===----------------------------------------------------------------------===//
742
743 /// ShrinkDemandedConstant - Check to see if the specified operand of the
744 /// specified instruction is a constant integer. If so, check to see if there
745 /// are any bits set in the constant that are not demanded. If so, shrink the
746 /// constant and return true.
747 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
748 const APInt &Demanded) {
749 DebugLoc dl = Op.getDebugLoc();
750
751 // FIXME: ISD::SELECT, ISD::SELECT_CC
752 switch (Op.getOpcode()) {
753 default: break;
754 case ISD::XOR:
755 case ISD::AND:
756 case ISD::OR: {
757 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
758 if (!C) return false;
759
760 if (Op.getOpcode() == ISD::XOR &&
761 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
762 return false;
763
764 // if we can expand it to have all bits set, do it
765 if (C->getAPIntValue().intersects(~Demanded)) {
766 MVT VT = Op.getValueType();
767 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
768 DAG.getConstant(Demanded &
769 C->getAPIntValue(),
770 VT));
771 return CombineTo(Op, New);
772 }
773
774 break;
775 }
776 }
777
778 return false;
779 }
780
781 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
782 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
783 /// cast, but it could be generalized for targets with other types of
784 /// implicit widening casts.
785 bool
786 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
787 unsigned BitWidth,
788 const APInt &Demanded,
789 DebugLoc dl) {
790 assert(Op.getNumOperands() == 2 &&
791 "ShrinkDemandedOp only supports binary operators!");
792 assert(Op.getNode()->getNumValues() == 1 &&
793 "ShrinkDemandedOp only supports nodes with one result!");
794
795 // Don't do this if the node has another user, which may require the
796 // full value.
797 if (!Op.getNode()->hasOneUse())
798 return false;
799
800 // Search for the smallest integer type with free casts to and from
801 // Op's type. For expedience, just check power-of-2 integer types.
802 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
803 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
804 if (!isPowerOf2_32(SmallVTBits))
805 SmallVTBits = NextPowerOf2(SmallVTBits);
806 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
807 MVT SmallVT = MVT::getIntegerVT(SmallVTBits);
808 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
809 TLI.isZExtFree(SmallVT, Op.getValueType())) {
810 // We found a type with free casts.
811 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
812 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
813 Op.getNode()->getOperand(0)),
814 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
815 Op.getNode()->getOperand(1)));
816 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
817 return CombineTo(Op, Z);
818 }
819 }
820 return false;
821 }
822
823 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
824 /// DemandedMask bits of the result of Op are ever used downstream. If we can
825 /// use this information to simplify Op, create a new simplified DAG node and
826 /// return true, returning the original and new nodes in Old and New. Otherwise,
827 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
828 /// the expression (used to simplify the caller). The KnownZero/One bits may
829 /// only be accurate for those bits in the DemandedMask.
830 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
831 const APInt &DemandedMask,
832 APInt &KnownZero,
833 APInt &KnownOne,
834 TargetLoweringOpt &TLO,
835 unsigned Depth) const {
836 unsigned BitWidth = DemandedMask.getBitWidth();
837 assert(Op.getValueSizeInBits() == BitWidth &&
838 "Mask size mismatches value type size!");
839 APInt NewMask = DemandedMask;
840 DebugLoc dl = Op.getDebugLoc();
841
842 // Don't know anything.
843 KnownZero = KnownOne = APInt(BitWidth, 0);
844
845 // Other users may use these bits.
846 if (!Op.getNode()->hasOneUse()) {
847 if (Depth != 0) {
848 // If not at the root, Just compute the KnownZero/KnownOne bits to
849 // simplify things downstream.
850 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
851 return false;
852 }
853 // If this is the root being simplified, allow it to have multiple uses,
854 // just set the NewMask to all bits.
855 NewMask = APInt::getAllOnesValue(BitWidth);
856 } else if (DemandedMask == 0) {
857 // Not demanding any bits from Op.
858 if (Op.getOpcode() != ISD::UNDEF)
859 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
860 return false;
861 } else if (Depth == 6) { // Limit search depth.
862 return false;
863 }
864
865 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
866 switch (Op.getOpcode()) {
867 case ISD::Constant:
868 // We know all of the bits for a constant!
869 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
870 KnownZero = ~KnownOne & NewMask;
871 return false; // Don't fall through, will infinitely loop.
872 case ISD::AND:
873 // If the RHS is a constant, check to see if the LHS would be zero without
874 // using the bits from the RHS. Below, we use knowledge about the RHS to
875 // simplify the LHS, here we're using information from the LHS to simplify
876 // the RHS.
877 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
878 APInt LHSZero, LHSOne;
879 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
880 LHSZero, LHSOne, Depth+1);
881 // If the LHS already has zeros where RHSC does, this and is dead.
882 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
883 return TLO.CombineTo(Op, Op.getOperand(0));
884 // If any of the set bits in the RHS are known zero on the LHS, shrink
885 // the constant.
886 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
887 return true;
888 }
889
890 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
891 KnownOne, TLO, Depth+1))
892 return true;
893 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
894 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
895 KnownZero2, KnownOne2, TLO, Depth+1))
896 return true;
897 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
898
899 // If all of the demanded bits are known one on one side, return the other.
900 // These bits cannot contribute to the result of the 'and'.
901 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
902 return TLO.CombineTo(Op, Op.getOperand(0));
903 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
904 return TLO.CombineTo(Op, Op.getOperand(1));
905 // If all of the demanded bits in the inputs are known zeros, return zero.
906 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
907 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
908 // If the RHS is a constant, see if we can simplify it.
909 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
910 return true;
911 // If the operation can be done in a smaller type, do so.
912 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
913 return true;
914
915 // Output known-1 bits are only known if set in both the LHS & RHS.
916 KnownOne &= KnownOne2;
917 // Output known-0 are known to be clear if zero in either the LHS | RHS.
918 KnownZero |= KnownZero2;
919 break;
920 case ISD::OR:
921 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
922 KnownOne, TLO, Depth+1))
923 return true;
924 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
925 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
926 KnownZero2, KnownOne2, TLO, Depth+1))
927 return true;
928 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
929
930 // If all of the demanded bits are known zero on one side, return the other.
931 // These bits cannot contribute to the result of the 'or'.
932 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
933 return TLO.CombineTo(Op, Op.getOperand(0));
934 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
935 return TLO.CombineTo(Op, Op.getOperand(1));
936 // If all of the potentially set bits on one side are known to be set on
937 // the other side, just use the 'other' side.
938 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
939 return TLO.CombineTo(Op, Op.getOperand(0));
940 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
941 return TLO.CombineTo(Op, Op.getOperand(1));
942 // If the RHS is a constant, see if we can simplify it.
943 if (TLO.ShrinkDemandedConstant(Op, NewMask))
944 return true;
945 // If the operation can be done in a smaller type, do so.
946 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
947 return true;
948
949 // Output known-0 bits are only known if clear in both the LHS & RHS.
950 KnownZero &= KnownZero2;
951 // Output known-1 are known to be set if set in either the LHS | RHS.
952 KnownOne |= KnownOne2;
953 break;
954 case ISD::XOR:
955 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
956 KnownOne, TLO, Depth+1))
957 return true;
958 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
959 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
960 KnownOne2, TLO, Depth+1))
961 return true;
962 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
963
964 // If all of the demanded bits are known zero on one side, return the other.
965 // These bits cannot contribute to the result of the 'xor'.
966 if ((KnownZero & NewMask) == NewMask)
967 return TLO.CombineTo(Op, Op.getOperand(0));
968 if ((KnownZero2 & NewMask) == NewMask)
969 return TLO.CombineTo(Op, Op.getOperand(1));
970 // If the operation can be done in a smaller type, do so.
971 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
972 return true;
973
974 // If all of the unknown bits are known to be zero on one side or the other
975 // (but not both) turn this into an *inclusive* or.
976 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
977 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
978 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
979 Op.getOperand(0),
980 Op.getOperand(1)));
981
982 // Output known-0 bits are known if clear or set in both the LHS & RHS.
983 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
984 // Output known-1 are known to be set if set in only one of the LHS, RHS.
985 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
986
987 // If all of the demanded bits on one side are known, and all of the set
988 // bits on that side are also known to be set on the other side, turn this
989 // into an AND, as we know the bits will be cleared.
990 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
991 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
992 if ((KnownOne & KnownOne2) == KnownOne) {
993 MVT VT = Op.getValueType();
994 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
995 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
996 Op.getOperand(0), ANDC));
997 }
998 }
999
1000 // If the RHS is a constant, see if we can simplify it.
1001 // for XOR, we prefer to force bits to 1 if they will make a -1.
1002 // if we can't force bits, try to shrink constant
1003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1004 APInt Expanded = C->getAPIntValue() | (~NewMask);
1005 // if we can expand it to have all bits set, do it
1006 if (Expanded.isAllOnesValue()) {
1007 if (Expanded != C->getAPIntValue()) {
1008 MVT VT = Op.getValueType();
1009 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1010 TLO.DAG.getConstant(Expanded, VT));
1011 return TLO.CombineTo(Op, New);
1012 }
1013 // if it already has all the bits set, nothing to change
1014 // but don't shrink either!
1015 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1016 return true;
1017 }
1018 }
1019
1020 KnownZero = KnownZeroOut;
1021 KnownOne = KnownOneOut;
1022 break;
1023 case ISD::SELECT:
1024 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1025 KnownOne, TLO, Depth+1))
1026 return true;
1027 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1028 KnownOne2, TLO, Depth+1))
1029 return true;
1030 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1031 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1032
1033 // If the operands are constants, see if we can simplify them.
1034 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1035 return true;
1036
1037 // Only known if known in both the LHS and RHS.
1038 KnownOne &= KnownOne2;
1039 KnownZero &= KnownZero2;
1040 break;
1041 case ISD::SELECT_CC:
1042 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1043 KnownOne, TLO, Depth+1))
1044 return true;
1045 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1046 KnownOne2, TLO, Depth+1))
1047 return true;
1048 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1049 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1050
1051 // If the operands are constants, see if we can simplify them.
1052 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1053 return true;
1054
1055 // Only known if known in both the LHS and RHS.
1056 KnownOne &= KnownOne2;
1057 KnownZero &= KnownZero2;
1058 break;
1059 case ISD::SHL:
1060 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1061 unsigned ShAmt = SA->getZExtValue();
1062 SDValue InOp = Op.getOperand(0);
1063
1064 // If the shift count is an invalid immediate, don't do anything.
1065 if (ShAmt >= BitWidth)
1066 break;
1067
1068 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1069 // single shift. We can do this if the bottom bits (which are shifted
1070 // out) are never demanded.
1071 if (InOp.getOpcode() == ISD::SRL &&
1072 isa<ConstantSDNode>(InOp.getOperand(1))) {
1073 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1074 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1075 unsigned Opc = ISD::SHL;
1076 int Diff = ShAmt-C1;
1077 if (Diff < 0) {
1078 Diff = -Diff;
1079 Opc = ISD::SRL;
1080 }
1081
1082 SDValue NewSA =
1083 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1084 MVT VT = Op.getValueType();
1085 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1086 InOp.getOperand(0), NewSA));
1087 }
1088 }
1089
1090 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1091 KnownZero, KnownOne, TLO, Depth+1))
1092 return true;
1093 KnownZero <<= SA->getZExtValue();
1094 KnownOne <<= SA->getZExtValue();
1095 // low bits known zero.
1096 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1097 }
1098 break;
1099 case ISD::SRL:
1100 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1101 MVT VT = Op.getValueType();
1102 unsigned ShAmt = SA->getZExtValue();
1103 unsigned VTSize = VT.getSizeInBits();
1104 SDValue InOp = Op.getOperand(0);
1105
1106 // If the shift count is an invalid immediate, don't do anything.
1107 if (ShAmt >= BitWidth)
1108 break;
1109
1110 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1111 // single shift. We can do this if the top bits (which are shifted out)
1112 // are never demanded.
1113 if (InOp.getOpcode() == ISD::SHL &&
1114 isa<ConstantSDNode>(InOp.getOperand(1))) {
1115 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1116 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1117 unsigned Opc = ISD::SRL;
1118 int Diff = ShAmt-C1;
1119 if (Diff < 0) {
1120 Diff = -Diff;
1121 Opc = ISD::SHL;
1122 }
1123
1124 SDValue NewSA =
1125 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1126 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1127 InOp.getOperand(0), NewSA));
1128 }
1129 }
1130
1131 // Compute the new bits that are at the top now.
1132 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1133 KnownZero, KnownOne, TLO, Depth+1))
1134 return true;
1135 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1136 KnownZero = KnownZero.lshr(ShAmt);
1137 KnownOne = KnownOne.lshr(ShAmt);
1138
1139 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1140 KnownZero |= HighBits; // High bits known zero.
1141 }
1142 break;
1143 case ISD::SRA:
1144 // If this is an arithmetic shift right and only the low-bit is set, we can
1145 // always convert this into a logical shr, even if the shift amount is
1146 // variable. The low bit of the shift cannot be an input sign bit unless
1147 // the shift amount is >= the size of the datatype, which is undefined.
1148 if (DemandedMask == 1)
1149 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1150 Op.getOperand(0), Op.getOperand(1)));
1151
1152 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1153 MVT VT = Op.getValueType();
1154 unsigned ShAmt = SA->getZExtValue();
1155
1156 // If the shift count is an invalid immediate, don't do anything.
1157 if (ShAmt >= BitWidth)
1158 break;
1159
1160 APInt InDemandedMask = (NewMask << ShAmt);
1161
1162 // If any of the demanded bits are produced by the sign extension, we also
1163 // demand the input sign bit.
1164 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1165 if (HighBits.intersects(NewMask))
1166 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
1167
1168 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1169 KnownZero, KnownOne, TLO, Depth+1))
1170 return true;
1171 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1172 KnownZero = KnownZero.lshr(ShAmt);
1173 KnownOne = KnownOne.lshr(ShAmt);
1174
1175 // Handle the sign bit, adjusted to where it is now in the mask.
1176 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1177
1178 // If the input sign bit is known to be zero, or if none of the top bits
1179 // are demanded, turn this into an unsigned shift right.
1180 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1181 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1182 Op.getOperand(0),
1183 Op.getOperand(1)));
1184 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1185 KnownOne |= HighBits;
1186 }
1187 }
1188 break;
1189 case ISD::SIGN_EXTEND_INREG: {
1190 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1191
1192 // Sign extension. Compute the demanded bits in the result that are not
1193 // present in the input.
1194 APInt NewBits = APInt::getHighBitsSet(BitWidth,
1195 BitWidth - EVT.getSizeInBits()) &
1196 NewMask;
1197
1198 // If none of the extended bits are demanded, eliminate the sextinreg.
1199 if (NewBits == 0)
1200 return TLO.CombineTo(Op, Op.getOperand(0));
1201
1202 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1203 InSignBit.zext(BitWidth);
1204 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1205 EVT.getSizeInBits()) &
1206 NewMask;
1207
1208 // Since the sign extended bits are demanded, we know that the sign
1209 // bit is demanded.
1210 InputDemandedBits |= InSignBit;
1211
1212 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1213 KnownZero, KnownOne, TLO, Depth+1))
1214 return true;
1215 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1216
1217 // If the sign bit of the input is known set or clear, then we know the
1218 // top bits of the result.
1219
1220 // If the input sign bit is known zero, convert this into a zero extension.
1221 if (KnownZero.intersects(InSignBit))
1222 return TLO.CombineTo(Op,
1223 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1224
1225 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1226 KnownOne |= NewBits;
1227 KnownZero &= ~NewBits;
1228 } else { // Input sign bit unknown
1229 KnownZero &= ~NewBits;
1230 KnownOne &= ~NewBits;
1231 }
1232 break;
1233 }
1234 case ISD::ZERO_EXTEND: {
1235 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1236 APInt InMask = NewMask;
1237 InMask.trunc(OperandBitWidth);
1238
1239 // If none of the top bits are demanded, convert this into an any_extend.
1240 APInt NewBits =
1241 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1242 if (!NewBits.intersects(NewMask))
1243 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1244 Op.getValueType(),
1245 Op.getOperand(0)));
1246
1247 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1248 KnownZero, KnownOne, TLO, Depth+1))
1249 return true;
1250 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1251 KnownZero.zext(BitWidth);
1252 KnownOne.zext(BitWidth);
1253 KnownZero |= NewBits;
1254 break;
1255 }
1256 case ISD::SIGN_EXTEND: {
1257 MVT InVT = Op.getOperand(0).getValueType();
1258 unsigned InBits = InVT.getSizeInBits();
1259 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1260 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1261 APInt NewBits = ~InMask & NewMask;
1262
1263 // If none of the top bits are demanded, convert this into an any_extend.
1264 if (NewBits == 0)
1265 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1266 Op.getValueType(),
1267 Op.getOperand(0)));
1268
1269 // Since some of the sign extended bits are demanded, we know that the sign
1270 // bit is demanded.
1271 APInt InDemandedBits = InMask & NewMask;
1272 InDemandedBits |= InSignBit;
1273 InDemandedBits.trunc(InBits);
1274
1275 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1276 KnownOne, TLO, Depth+1))
1277 return true;
1278 KnownZero.zext(BitWidth);
1279 KnownOne.zext(BitWidth);
1280
1281 // If the sign bit is known zero, convert this to a zero extend.
1282 if (KnownZero.intersects(InSignBit))
1283 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1284 Op.getValueType(),
1285 Op.getOperand(0)));
1286
1287 // If the sign bit is known one, the top bits match.
1288 if (KnownOne.intersects(InSignBit)) {
1289 KnownOne |= NewBits;
1290 KnownZero &= ~NewBits;
1291 } else { // Otherwise, top bits aren't known.
1292 KnownOne &= ~NewBits;
1293 KnownZero &= ~NewBits;
1294 }
1295 break;
1296 }
1297 case ISD::ANY_EXTEND: {
1298 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1299 APInt InMask = NewMask;
1300 InMask.trunc(OperandBitWidth);
1301 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1302 KnownZero, KnownOne, TLO, Depth+1))
1303 return true;
1304 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1305 KnownZero.zext(BitWidth);
1306 KnownOne.zext(BitWidth);
1307 break;
1308 }
1309 case ISD::TRUNCATE: {
1310 // Simplify the input, using demanded bit information, and compute the known
1311 // zero/one bits live out.
1312 APInt TruncMask = NewMask;
1313 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1314 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1315 KnownZero, KnownOne, TLO, Depth+1))
1316 return true;
1317 KnownZero.trunc(BitWidth);
1318 KnownOne.trunc(BitWidth);
1319
1320 // If the input is only used by this truncate, see if we can shrink it based
1321 // on the known demanded bits.
1322 if (Op.getOperand(0).getNode()->hasOneUse()) {
1323 SDValue In = Op.getOperand(0);
1324 unsigned InBitWidth = In.getValueSizeInBits();
1325 switch (In.getOpcode()) {
1326 default: break;
1327 case ISD::SRL:
1328 // Shrink SRL by a constant if none of the high bits shifted in are
1329 // demanded.
1330 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1331 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1332 InBitWidth - BitWidth);
1333 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1334 HighBits.trunc(BitWidth);
1335
1336 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1337 // None of the shifted in bits are needed. Add a truncate of the
1338 // shift input, then shift it.
1339 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1340 Op.getValueType(),
1341 In.getOperand(0));
1342 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1343 Op.getValueType(),
1344 NewTrunc,
1345 In.getOperand(1)));
1346 }
1347 }
1348 break;
1349 }
1350 }
1351
1352 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1353 break;
1354 }
1355 case ISD::AssertZext: {
1356 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1357 APInt InMask = APInt::getLowBitsSet(BitWidth,
1358 VT.getSizeInBits());
1359 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1360 KnownZero, KnownOne, TLO, Depth+1))
1361 return true;
1362 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1363 KnownZero |= ~InMask & NewMask;
1364 break;
1365 }
1366 case ISD::BIT_CONVERT:
1367 #if 0
1368 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1369 // is demanded, turn this into a FGETSIGN.
1370 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) &&
1371 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1372 !MVT::isVector(Op.getOperand(0).getValueType())) {
1373 // Only do this xform if FGETSIGN is valid or if before legalize.
1374 if (!TLO.AfterLegalize ||
1375 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1376 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1377 // place. We expect the SHL to be eliminated by other optimizations.
1378 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1379 Op.getOperand(0));
1380 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1381 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1382 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1383 Sign, ShAmt));
1384 }
1385 }
1386 #endif
1387 break;
1388 case ISD::ADD:
1389 case ISD::MUL:
1390 case ISD::SUB: {
1391 // Add, Sub, and Mul don't demand any bits in positions beyond that
1392 // of the highest bit demanded of them.
1393 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1394 BitWidth - NewMask.countLeadingZeros());
1395 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1396 KnownOne2, TLO, Depth+1))
1397 return true;
1398 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1399 KnownOne2, TLO, Depth+1))
1400 return true;
1401 // See if the operation should be performed at a smaller bit width.
1402 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1403 return true;
1404 }
1405 // FALL THROUGH
1406 default:
1407 // Just use ComputeMaskedBits to compute output bits.
1408 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1409 break;
1410 }
1411
1412 // If we know the value of all of the demanded bits, return this as a
1413 // constant.
1414 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1415 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1416
1417 return false;
1418 }
1419
1420 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1421 /// in Mask are known to be either zero or one and return them in the
1422 /// KnownZero/KnownOne bitsets.
1423 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1424 const APInt &Mask,
1425 APInt &KnownZero,
1426 APInt &KnownOne,
1427 const SelectionDAG &DAG,
1428 unsigned Depth) const {
1429 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1430 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1431 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1432 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1433 "Should use MaskedValueIsZero if you don't know whether Op"
1434 " is a target node!");
1435 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1436 }
1437
1438 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1439 /// targets that want to expose additional information about sign bits to the
1440 /// DAG Combiner.
1441 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1442 unsigned Depth) const {
1443 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1444 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1445 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1446 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1447 "Should use ComputeNumSignBits if you don't know whether Op"
1448 " is a target node!");
1449 return 1;
1450 }
1451
1452 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1453 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1454 /// determine which bit is set.
1455 ///
1456 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1457 // A left-shift of a constant one will have exactly one bit set, because
1458 // shifting the bit off the end is undefined.
1459 if (Val.getOpcode() == ISD::SHL)
1460 if (ConstantSDNode *C =
1461 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1462 if (C->getAPIntValue() == 1)
1463 return true;
1464
1465 // Similarly, a right-shift of a constant sign-bit will have exactly
1466 // one bit set.
1467 if (Val.getOpcode() == ISD::SRL)
1468 if (ConstantSDNode *C =
1469 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1470 if (C->getAPIntValue().isSignBit())
1471 return true;
1472
1473 // More could be done here, though the above checks are enough
1474 // to handle some common cases.
1475
1476 // Fall back to ComputeMaskedBits to catch other known cases.
1477 MVT OpVT = Val.getValueType();
1478 unsigned BitWidth = OpVT.getSizeInBits();
1479 APInt Mask = APInt::getAllOnesValue(BitWidth);
1480 APInt KnownZero, KnownOne;
1481 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1482 return (KnownZero.countPopulation() == BitWidth - 1) &&
1483 (KnownOne.countPopulation() == 1);
1484 }
1485
1486 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1487 /// and cc. If it is unable to simplify it, return a null SDValue.
1488 SDValue
1489 TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
1490 ISD::CondCode Cond, bool foldBooleans,
1491 DAGCombinerInfo &DCI, DebugLoc dl) const {
1492 SelectionDAG &DAG = DCI.DAG;
1493
1494 // These setcc operations always fold.
1495 switch (Cond) {
1496 default: break;
1497 case ISD::SETFALSE:
1498 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1499 case ISD::SETTRUE:
1500 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1501 }
1502
1503 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1504 const APInt &C1 = N1C->getAPIntValue();
1505 if (isa<ConstantSDNode>(N0.getNode())) {
1506 return DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1507 } else {
1508 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1509 // equality comparison, then we're just comparing whether X itself is
1510 // zero.
1511 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1512 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1513 N0.getOperand(1).getOpcode() == ISD::Constant) {
1514 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1515 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1516 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1517 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1518 // (srl (ctlz x), 5) == 0 -> X != 0
1519 // (srl (ctlz x), 5) != 1 -> X != 0
1520 Cond = ISD::SETNE;
1521 } else {
1522 // (srl (ctlz x), 5) != 0 -> X == 0
1523 // (srl (ctlz x), 5) == 1 -> X == 0
1524 Cond = ISD::SETEQ;
1525 }
1526 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1527 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1528 Zero, Cond);
1529 }
1530 }
1531
1532 // If the LHS is '(and load, const)', the RHS is 0,
1533 // the test is for equality or unsigned, and all 1 bits of the const are
1534 // in the same partial word, see if we can shorten the load.
1535 if (DCI.isBeforeLegalize() &&
1536 N0.getOpcode() == ISD::AND && C1 == 0 &&
1537 N0.getNode()->hasOneUse() &&
1538 isa<LoadSDNode>(N0.getOperand(0)) &&
1539 N0.getOperand(0).getNode()->hasOneUse() &&
1540 isa<ConstantSDNode>(N0.getOperand(1))) {
1541 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1542 uint64_t bestMask = 0;
1543 unsigned bestWidth = 0, bestOffset = 0;
1544 if (!Lod->isVolatile() && Lod->isUnindexed() &&
1545 // FIXME: This uses getZExtValue() below so it only works on i64 and
1546 // below.
1547 N0.getValueType().getSizeInBits() <= 64) {
1548 unsigned origWidth = N0.getValueType().getSizeInBits();
1549 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1550 // 8 bits, but have to be careful...
1551 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1552 origWidth = Lod->getMemoryVT().getSizeInBits();
1553 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1554 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1555 uint64_t newMask = (1ULL << width) - 1;
1556 for (unsigned offset=0; offset<origWidth/width; offset++) {
1557 if ((newMask & Mask) == Mask) {
1558 if (!TD->isLittleEndian())
1559 bestOffset = (origWidth/width - offset - 1) * (width/8);
1560 else
1561 bestOffset = (uint64_t)offset * (width/8);
1562 bestMask = Mask >> (offset * (width/8) * 8);
1563 bestWidth = width;
1564 break;
1565 }
1566 newMask = newMask << width;
1567 }
1568 }
1569 }
1570 if (bestWidth) {
1571 MVT newVT = MVT::getIntegerVT(bestWidth);
1572 if (newVT.isRound()) {
1573 MVT PtrType = Lod->getOperand(1).getValueType();
1574 SDValue Ptr = Lod->getBasePtr();
1575 if (bestOffset != 0)
1576 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1577 DAG.getConstant(bestOffset, PtrType));
1578 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1579 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1580 Lod->getSrcValue(),
1581 Lod->getSrcValueOffset() + bestOffset,
1582 false, NewAlign);
1583 return DAG.getSetCC(dl, VT,
1584 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1585 DAG.getConstant(bestMask, newVT)),
1586 DAG.getConstant(0LL, newVT), Cond);
1587 }
1588 }
1589 }
1590
1591 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1592 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1593 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1594
1595 // If the comparison constant has bits in the upper part, the
1596 // zero-extended value could never match.
1597 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1598 C1.getBitWidth() - InSize))) {
1599 switch (Cond) {
1600 case ISD::SETUGT:
1601 case ISD::SETUGE:
1602 case ISD::SETEQ: return DAG.getConstant(0, VT);
1603 case ISD::SETULT:
1604 case ISD::SETULE:
1605 case ISD::SETNE: return DAG.getConstant(1, VT);
1606 case ISD::SETGT:
1607 case ISD::SETGE:
1608 // True if the sign bit of C1 is set.
1609 return DAG.getConstant(C1.isNegative(), VT);
1610 case ISD::SETLT:
1611 case ISD::SETLE:
1612 // True if the sign bit of C1 isn't set.
1613 return DAG.getConstant(C1.isNonNegative(), VT);
1614 default:
1615 break;
1616 }
1617 }
1618
1619 // Otherwise, we can perform the comparison with the low bits.
1620 switch (Cond) {
1621 case ISD::SETEQ:
1622 case ISD::SETNE:
1623 case ISD::SETUGT:
1624 case ISD::SETUGE:
1625 case ISD::SETULT:
1626 case ISD::SETULE:
1627 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1628 DAG.getConstant(APInt(C1).trunc(InSize),
1629 N0.getOperand(0).getValueType()),
1630 Cond);
1631 default:
1632 break; // todo, be more careful with signed comparisons
1633 }
1634 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1635 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1636 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1637 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1638 MVT ExtDstTy = N0.getValueType();
1639 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1640
1641 // If the extended part has any inconsistent bits, it cannot ever
1642 // compare equal. In other words, they have to be all ones or all
1643 // zeros.
1644 APInt ExtBits =
1645 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1646 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1647 return DAG.getConstant(Cond == ISD::SETNE, VT);
1648
1649 SDValue ZextOp;
1650 MVT Op0Ty = N0.getOperand(0).getValueType();
1651 if (Op0Ty == ExtSrcTy) {
1652 ZextOp = N0.getOperand(0);
1653 } else {
1654 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1655 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1656 DAG.getConstant(Imm, Op0Ty));
1657 }
1658 if (!DCI.isCalledByLegalizer())
1659 DCI.AddToWorklist(ZextOp.getNode());
1660 // Otherwise, make this a use of a zext.
1661 return DAG.getSetCC(dl, VT, ZextOp,
1662 DAG.getConstant(C1 & APInt::getLowBitsSet(
1663 ExtDstTyBits,
1664 ExtSrcTyBits),
1665 ExtDstTy),
1666 Cond);
1667 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1668 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1669
1670 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1671 if (N0.getOpcode() == ISD::SETCC) {
1672 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1673 if (TrueWhenTrue)
1674 return N0;
1675
1676 // Invert the condition.
1677 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1678 CC = ISD::getSetCCInverse(CC,
1679 N0.getOperand(0).getValueType().isInteger());
1680 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1681 }
1682
1683 if ((N0.getOpcode() == ISD::XOR ||
1684 (N0.getOpcode() == ISD::AND &&
1685 N0.getOperand(0).getOpcode() == ISD::XOR &&
1686 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1687 isa<ConstantSDNode>(N0.getOperand(1)) &&
1688 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1689 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1690 // can only do this if the top bits are known zero.
1691 unsigned BitWidth = N0.getValueSizeInBits();
1692 if (DAG.MaskedValueIsZero(N0,
1693 APInt::getHighBitsSet(BitWidth,
1694 BitWidth-1))) {
1695 // Okay, get the un-inverted input value.
1696 SDValue Val;
1697 if (N0.getOpcode() == ISD::XOR)
1698 Val = N0.getOperand(0);
1699 else {
1700 assert(N0.getOpcode() == ISD::AND &&
1701 N0.getOperand(0).getOpcode() == ISD::XOR);
1702 // ((X^1)&1)^1 -> X & 1
1703 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1704 N0.getOperand(0).getOperand(0),
1705 N0.getOperand(1));
1706 }
1707 return DAG.getSetCC(dl, VT, Val, N1,
1708 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1709 }
1710 }
1711 }
1712
1713 APInt MinVal, MaxVal;
1714 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1715 if (ISD::isSignedIntSetCC(Cond)) {
1716 MinVal = APInt::getSignedMinValue(OperandBitSize);
1717 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1718 } else {
1719 MinVal = APInt::getMinValue(OperandBitSize);
1720 MaxVal = APInt::getMaxValue(OperandBitSize);
1721 }
1722
1723 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1724 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1725 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1726 // X >= C0 --> X > (C0-1)
1727 return DAG.getSetCC(dl, VT, N0,
1728 DAG.getConstant(C1-1, N1.getValueType()),
1729 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1730 }
1731
1732 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1733 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1734 // X <= C0 --> X < (C0+1)
1735 return DAG.getSetCC(dl, VT, N0,
1736 DAG.getConstant(C1+1, N1.getValueType()),
1737 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1738 }
1739
1740 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1741 return DAG.getConstant(0, VT); // X < MIN --> false
1742 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1743 return DAG.getConstant(1, VT); // X >= MIN --> true
1744 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1745 return DAG.getConstant(0, VT); // X > MAX --> false
1746 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1747 return DAG.getConstant(1, VT); // X <= MAX --> true
1748
1749 // Canonicalize setgt X, Min --> setne X, Min
1750 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1751 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1752 // Canonicalize setlt X, Max --> setne X, Max
1753 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1754 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1755
1756 // If we have setult X, 1, turn it into seteq X, 0
1757 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1758 return DAG.getSetCC(dl, VT, N0,
1759 DAG.getConstant(MinVal, N0.getValueType()),
1760 ISD::SETEQ);
1761 // If we have setugt X, Max-1, turn it into seteq X, Max
1762 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1763 return DAG.getSetCC(dl, VT, N0,
1764 DAG.getConstant(MaxVal, N0.getValueType()),
1765 ISD::SETEQ);
1766
1767 // If we have "setcc X, C0", check to see if we can shrink the immediate
1768 // by changing cc.
1769
1770 // SETUGT X, SINTMAX -> SETLT X, 0
1771 if (Cond == ISD::SETUGT &&
1772 C1 == APInt::getSignedMaxValue(OperandBitSize))
1773 return DAG.getSetCC(dl, VT, N0,
1774 DAG.getConstant(0, N1.getValueType()),
1775 ISD::SETLT);
1776
1777 // SETULT X, SINTMIN -> SETGT X, -1
1778 if (Cond == ISD::SETULT &&
1779 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1780 SDValue ConstMinusOne =
1781 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1782 N1.getValueType());
1783 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1784 }
1785
1786 // Fold bit comparisons when we can.
1787 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1788 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1789 if (ConstantSDNode *AndRHS =
1790 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1791 MVT ShiftTy = DCI.isBeforeLegalize() ?
1792 getPointerTy() : getShiftAmountTy();
1793 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1794 // Perform the xform if the AND RHS is a single bit.
1795 if (isPowerOf2_64(AndRHS->getZExtValue())) {
1796 return DAG.getNode(ISD::SRL, dl, VT, N0,
1797 DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1798 ShiftTy));
1799 }
1800 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1801 // (X & 8) == 8 --> (X & 8) >> 3
1802 // Perform the xform if C1 is a single bit.
1803 if (C1.isPowerOf2()) {
1804 return DAG.getNode(ISD::SRL, dl, VT, N0,
1805 DAG.getConstant(C1.logBase2(), ShiftTy));
1806 }
1807 }
1808 }
1809 }
1810 } else if (isa<ConstantSDNode>(N0.getNode())) {
1811 // Ensure that the constant occurs on the RHS.
1812 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1813 }
1814
1815 if (isa<ConstantFPSDNode>(N0.getNode())) {
1816 // Constant fold or commute setcc.
1817 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1818 if (O.getNode()) return O;
1819 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1820 // If the RHS of an FP comparison is a constant, simplify it away in
1821 // some cases.
1822 if (CFP->getValueAPF().isNaN()) {
1823 // If an operand is known to be a nan, we can fold it.
1824 switch (ISD::getUnorderedFlavor(Cond)) {
1825 default: assert(0 && "Unknown flavor!");
1826 case 0: // Known false.
1827 return DAG.getConstant(0, VT);
1828 case 1: // Known true.
1829 return DAG.getConstant(1, VT);
1830 case 2: // Undefined.
1831 return DAG.getUNDEF(VT);
1832 }
1833 }
1834
1835 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1836 // constant if knowing that the operand is non-nan is enough. We prefer to
1837 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1838 // materialize 0.0.
1839 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1840 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1841 }
1842
1843 if (N0 == N1) {
1844 // We can always fold X == X for integer setcc's.
1845 if (N0.getValueType().isInteger())
1846 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1847 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1848 if (UOF == 2) // FP operators that are undefined on NaNs.
1849 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1850 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1851 return DAG.getConstant(UOF, VT);
1852 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1853 // if it is not already.
1854 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1855 if (NewCond != Cond)
1856 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1857 }
1858
1859 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1860 N0.getValueType().isInteger()) {
1861 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1862 N0.getOpcode() == ISD::XOR) {
1863 // Simplify (X+Y) == (X+Z) --> Y == Z
1864 if (N0.getOpcode() == N1.getOpcode()) {
1865 if (N0.getOperand(0) == N1.getOperand(0))
1866 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1867 if (N0.getOperand(1) == N1.getOperand(1))
1868 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1869 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1870 // If X op Y == Y op X, try other combinations.
1871 if (N0.getOperand(0) == N1.getOperand(1))
1872 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1873 Cond);
1874 if (N0.getOperand(1) == N1.getOperand(0))
1875 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1876 Cond);
1877 }
1878 }
1879
1880 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1881 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1882 // Turn (X+C1) == C2 --> X == C2-C1
1883 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1884 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1885 DAG.getConstant(RHSC->getAPIntValue()-
1886 LHSR->getAPIntValue(),
1887 N0.getValueType()), Cond);
1888 }
1889
1890 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1891 if (N0.getOpcode() == ISD::XOR)
1892 // If we know that all of the inverted bits are zero, don't bother
1893 // performing the inversion.
1894 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1895 return
1896 DAG.getSetCC(dl, VT, N0.getOperand(0),
1897 DAG.getConstant(LHSR->getAPIntValue() ^
1898 RHSC->getAPIntValue(),
1899 N0.getValueType()),
1900 Cond);
1901 }
1902
1903 // Turn (C1-X) == C2 --> X == C1-C2
1904 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1905 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1906 return
1907 DAG.getSetCC(dl, VT, N0.getOperand(1),
1908 DAG.getConstant(SUBC->getAPIntValue() -
1909 RHSC->getAPIntValue(),
1910 N0.getValueType()),
1911 Cond);
1912 }
1913 }
1914 }
1915
1916 // Simplify (X+Z) == X --> Z == 0
1917 if (N0.getOperand(0) == N1)
1918 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1919 DAG.getConstant(0, N0.getValueType()), Cond);
1920 if (N0.getOperand(1) == N1) {
1921 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1922 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1923 DAG.getConstant(0, N0.getValueType()), Cond);
1924 else if (N0.getNode()->hasOneUse()) {
1925 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1926 // (Z-X) == X --> Z == X<<1
1927 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
1928 N1,
1929 DAG.getConstant(1, getShiftAmountTy()));
1930 if (!DCI.isCalledByLegalizer())
1931 DCI.AddToWorklist(SH.getNode());
1932 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1933 }
1934 }
1935 }
1936
1937 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1938 N1.getOpcode() == ISD::XOR) {
1939 // Simplify X == (X+Z) --> Z == 0
1940 if (N1.getOperand(0) == N0) {
1941 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1942 DAG.getConstant(0, N1.getValueType()), Cond);
1943 } else if (N1.getOperand(1) == N0) {
1944 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1945 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1946 DAG.getConstant(0, N1.getValueType()), Cond);
1947 } else if (N1.getNode()->hasOneUse()) {
1948 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1949 // X == (Z-X) --> X<<1 == Z
1950 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1951 DAG.getConstant(1, getShiftAmountTy()));
1952 if (!DCI.isCalledByLegalizer())
1953 DCI.AddToWorklist(SH.getNode());
1954 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1955 }
1956 }
1957 }
1958
1959 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1960 // Note that where y is variable and is known to have at most
1961 // one bit set (for example, if it is z&1) we cannot do this;
1962 // the expressions are not equivalent when y==0.
1963 if (N0.getOpcode() == ISD::AND)
1964 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1965 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1966 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1967 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1968 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1969 }
1970 }
1971 if (N1.getOpcode() == ISD::AND)
1972 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1973 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1974 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1975 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1976 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1977 }
1978 }
1979 }
1980
1981 // Fold away ALL boolean setcc's.
1982 SDValue Temp;
1983 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1984 switch (Cond) {
1985 default: assert(0 && "Unknown integer setcc!");
1986 case ISD::SETEQ: // X == Y -> ~(X^Y)
1987 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1988 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1989 if (!DCI.isCalledByLegalizer())
1990 DCI.AddToWorklist(Temp.getNode());
1991 break;
1992 case ISD::SETNE: // X != Y --> (X^Y)
1993 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1994 break;
1995 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1996 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1997 Temp = DAG.getNOT(dl, N0, MVT::i1);
1998 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1999 if (!DCI.isCalledByLegalizer())
2000 DCI.AddToWorklist(Temp.getNode());
2001 break;
2002 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2003 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2004 Temp = DAG.getNOT(dl, N1, MVT::i1);
2005 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2006 if (!DCI.isCalledByLegalizer())
2007 DCI.AddToWorklist(Temp.getNode());
2008 break;
2009 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2010 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2011 Temp = DAG.getNOT(dl, N0, MVT::i1);
2012 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2013 if (!DCI.isCalledByLegalizer())
2014 DCI.AddToWorklist(Temp.getNode());
2015 break;
2016 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2017 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2018 Temp = DAG.getNOT(dl, N1, MVT::i1);
2019 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2020 break;
2021 }
2022 if (VT != MVT::i1) {
2023 if (!DCI.isCalledByLegalizer())
2024 DCI.AddToWorklist(N0.getNode());
2025 // FIXME: If running after legalize, we probably can't do this.
2026 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2027 }
2028 return N0;
2029 }
2030
2031 // Could not fold it.
2032 return SDValue();
2033 }
2034
2035 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2036 /// node is a GlobalAddress + offset.
2037 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2038 int64_t &Offset) const {
2039 if (isa<GlobalAddressSDNode>(N)) {
2040 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2041 GA = GASD->getGlobal();
2042 Offset += GASD->getOffset();
2043 return true;
2044 }
2045
2046 if (N->getOpcode() == ISD::ADD) {
2047 SDValue N1 = N->getOperand(0);
2048 SDValue N2 = N->getOperand(1);
2049 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2050 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2051 if (V) {
2052 Offset += V->getSExtValue();
2053 return true;
2054 }
2055 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2056 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2057 if (V) {
2058 Offset += V->getSExtValue();
2059 return true;
2060 }
2061 }
2062 }
2063 return false;
2064 }
2065
2066
2067 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
2068 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
2069 /// location that the 'Base' load is loading from.
2070 bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
2071 unsigned Bytes, int Dist,
2072 const MachineFrameInfo *MFI) const {
2073 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
2074 return false;
2075 MVT VT = LD->getValueType(0);
2076 if (VT.getSizeInBits() / 8 != Bytes)
2077 return false;
2078
2079 SDValue Loc = LD->getOperand(1);
2080 SDValue BaseLoc = Base->getOperand(1);
2081 if (Loc.getOpcode() == ISD::FrameIndex) {
2082 if (BaseLoc.getOpcode() != ISD::FrameIndex)
2083 return false;
2084 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
2085 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
2086 int FS = MFI->getObjectSize(FI);
2087 int BFS = MFI->getObjectSize(BFI);
2088 if (FS != BFS || FS != (int)Bytes) return false;
2089 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
2090 }
2091
2092 GlobalValue *GV1 = NULL;
2093 GlobalValue *GV2 = NULL;
2094 int64_t Offset1 = 0;
2095 int64_t Offset2 = 0;
2096 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
2097 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
2098 if (isGA1 && isGA2 && GV1 == GV2)
2099 return Offset1 == (Offset2 + Dist*Bytes);
2100 return false;
2101 }
2102
2103
2104 SDValue TargetLowering::
2105 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2106 // Default implementation: no optimization.
2107 return SDValue();
2108 }
2109
2110 //===----------------------------------------------------------------------===//
2111 // Inline Assembler Implementation Methods
2112 //===----------------------------------------------------------------------===//
2113
2114
2115 TargetLowering::ConstraintType
2116 TargetLowering::getConstraintType(const std::string &Constraint) const {
2117 // FIXME: lots more standard ones to handle.
2118 if (Constraint.size() == 1) {
2119 switch (Constraint[0]) {
2120 default: break;
2121 case 'r': return C_RegisterClass;
2122 case 'm': // memory
2123 case 'o': // offsetable
2124 case 'V': // not offsetable
2125 return C_Memory;
2126 case 'i': // Simple Integer or Relocatable Constant
2127 case 'n': // Simple Integer
2128 case 's': // Relocatable Constant
2129 case 'X': // Allow ANY value.
2130 case 'I': // Target registers.
2131 case 'J':
2132 case 'K':
2133 case 'L':
2134 case 'M':
2135 case 'N':
2136 case 'O':
2137 case 'P':
2138 return C_Other;
2139 }
2140 }
2141
2142 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2143 Constraint[Constraint.size()-1] == '}')
2144 return C_Register;
2145 return C_Unknown;
2146 }
2147
2148 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2149 /// with another that has more specific requirements based on the type of the
2150 /// corresponding operand.
2151 const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
2152 if (ConstraintVT.isInteger())
2153 return "r";
2154 if (ConstraintVT.isFloatingPoint())
2155 return "f"; // works for many targets
2156 return 0;
2157 }
2158
2159 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2160 /// vector. If it is invalid, don't add anything to Ops.
2161 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2162 char ConstraintLetter,
2163 bool hasMemory,
2164 std::vector<SDValue> &Ops,
2165 SelectionDAG &DAG) const {
2166 switch (ConstraintLetter) {
2167 default: break;
2168 case 'X': // Allows any operand; labels (basic block) use this.
2169 if (Op.getOpcode() == ISD::BasicBlock) {
2170 Ops.push_back(Op);
2171 return;
2172 }
2173 // fall through
2174 case 'i': // Simple Integer or Relocatable Constant
2175 case 'n': // Simple Integer
2176 case 's': { // Relocatable Constant
2177 // These operands are interested in values of the form (GV+C), where C may
2178 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2179 // is possible and fine if either GV or C are missing.
2180 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2181 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2182
2183 // If we have "(add GV, C)", pull out GV/C
2184 if (Op.getOpcode() == ISD::ADD) {
2185 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2186 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2187 if (C == 0 || GA == 0) {
2188 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2189 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2190 }
2191 if (C == 0 || GA == 0)
2192 C = 0, GA = 0;
2193 }
2194
2195 // If we find a valid operand, map to the TargetXXX version so that the
2196 // value itself doesn't get selected.
2197 if (GA) { // Either &GV or &GV+C
2198 if (ConstraintLetter != 'n') {
2199 int64_t Offs = GA->getOffset();
2200 if (C) Offs += C->getZExtValue();
2201 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2202 Op.getValueType(), Offs));
2203 return;
2204 }
2205 }
2206 if (C) { // just C, no GV.
2207 // Simple constants are not allowed for 's'.
2208 if (ConstraintLetter != 's') {
2209 // gcc prints these as sign extended. Sign extend value to 64 bits
2210 // now; without this it would get ZExt'd later in
2211 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2212 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2213 MVT::i64));
2214 return;
2215 }
2216 }
2217 break;
2218 }
2219 }
2220 }
2221
2222 std::vector<unsigned> TargetLowering::
2223 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2224 MVT VT) const {
2225 return std::vector<unsigned>();
2226 }
2227
2228
2229 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2230 getRegForInlineAsmConstraint(const std::string &Constraint,
2231 MVT VT) const {
2232 if (Constraint[0] != '{')
2233 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2234 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2235
2236 // Remove the braces from around the name.
2237 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
2238
2239 // Figure out which register class contains this reg.
2240 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2241 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2242 E = RI->regclass_end(); RCI != E; ++RCI) {
2243 const TargetRegisterClass *RC = *RCI;
2244
2245 // If none of the the value types for this register class are valid, we
2246 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2247 bool isLegal = false;
2248 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2249 I != E; ++I) {
2250 if (isTypeLegal(*I)) {
2251 isLegal = true;
2252 break;
2253 }
2254 }
2255
2256 if (!isLegal) continue;
2257
2258 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2259 I != E; ++I) {
2260 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
2261 return std::make_pair(*I, RC);
2262 }
2263 }
2264
2265 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2266 }
2267
2268 //===----------------------------------------------------------------------===//
2269 // Constraint Selection.
2270
2271 /// isMatchingInputConstraint - Return true of this is an input operand that is
2272 /// a matching constraint like "4".
2273 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2274 assert(!ConstraintCode.empty() && "No known constraint!");
2275 return isdigit(ConstraintCode[0]);
2276 }
2277
2278 /// getMatchedOperand - If this is an input matching constraint, this method
2279 /// returns the output operand it matches.
2280 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2281 assert(!ConstraintCode.empty() && "No known constraint!");
2282 return atoi(ConstraintCode.c_str());
2283 }
2284
2285
2286 /// getConstraintGenerality - Return an integer indicating how general CT
2287 /// is.
2288 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2289 switch (CT) {
2290 default: assert(0 && "Unknown constraint type!");
2291 case TargetLowering::C_Other:
2292 case TargetLowering::C_Unknown:
2293 return 0;
2294 case TargetLowering::C_Register:
2295 return 1;
2296 case TargetLowering::C_RegisterClass:
2297 return 2;
2298 case TargetLowering::C_Memory:
2299 return 3;
2300 }
2301 }
2302
2303 /// ChooseConstraint - If there are multiple different constraints that we
2304 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2305 /// This is somewhat tricky: constraints fall into four classes:
2306 /// Other -> immediates and magic values
2307 /// Register -> one specific register
2308 /// RegisterClass -> a group of regs
2309 /// Memory -> memory
2310 /// Ideally, we would pick the most specific constraint possible: if we have
2311 /// something that fits into a register, we would pick it. The problem here
2312 /// is that if we have something that could either be in a register or in
2313 /// memory that use of the register could cause selection of *other*
2314 /// operands to fail: they might only succeed if we pick memory. Because of
2315 /// this the heuristic we use is:
2316 ///
2317 /// 1) If there is an 'other' constraint, and if the operand is valid for
2318 /// that constraint, use it. This makes us take advantage of 'i'
2319 /// constraints when available.
2320 /// 2) Otherwise, pick the most general constraint present. This prefers
2321 /// 'm' over 'r', for example.
2322 ///
2323 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2324 bool hasMemory, const TargetLowering &TLI,
2325 SDValue Op, SelectionDAG *DAG) {
2326 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2327 unsigned BestIdx = 0;
2328 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2329 int BestGenerality = -1;
2330
2331 // Loop over the options, keeping track of the most general one.
2332 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2333 TargetLowering::ConstraintType CType =
2334 TLI.getConstraintType(OpInfo.Codes[i]);
2335
2336 // If this is an 'other' constraint, see if the operand is valid for it.
2337 // For example, on X86 we might have an 'rI' constraint. If the operand
2338 // is an integer in the range [0..31] we want to use I (saving a load
2339 // of a register), otherwise we must use 'r'.
2340 if (CType == TargetLowering::C_Other && Op.getNode()) {
2341 assert(OpInfo.Codes[i].size() == 1 &&
2342 "Unhandled multi-letter 'other' constraint");
2343 std::vector<SDValue> ResultOps;
2344 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2345 ResultOps, *DAG);
2346 if (!ResultOps.empty()) {
2347 BestType = CType;
2348 BestIdx = i;
2349 break;
2350 }
2351 }
2352
2353 // This constraint letter is more general than the previous one, use it.
2354 int Generality = getConstraintGenerality(CType);
2355 if (Generality > BestGenerality) {
2356 BestType = CType;
2357 BestIdx = i;
2358 BestGenerality = Generality;
2359 }
2360 }
2361
2362 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2363 OpInfo.ConstraintType = BestType;
2364 }
2365
2366 /// ComputeConstraintToUse - Determines the constraint code and constraint
2367 /// type to use for the specific AsmOperandInfo, setting
2368 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2369 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2370 SDValue Op,
2371 bool hasMemory,
2372 SelectionDAG *DAG) const {
2373 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2374
2375 // Single-letter constraints ('r') are very common.
2376 if (OpInfo.Codes.size() == 1) {
2377 OpInfo.ConstraintCode = OpInfo.Codes[0];
2378 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2379 } else {
2380 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2381 }
2382
2383 // 'X' matches anything.
2384 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2385 // Labels and constants are handled elsewhere ('X' is the only thing
2386 // that matches labels).
2387 if (isa<BasicBlock>(OpInfo.CallOperandVal) ||
2388 isa<ConstantInt>(OpInfo.CallOperandVal))
2389 return;
2390
2391 // Otherwise, try to resolve it to something we know about by looking at
2392 // the actual operand type.
2393 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2394 OpInfo.ConstraintCode = Repl;
2395 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2396 }
2397 }
2398 }
2399
2400 //===----------------------------------------------------------------------===//
2401 // Loop Strength Reduction hooks
2402 //===----------------------------------------------------------------------===//
2403
2404 /// isLegalAddressingMode - Return true if the addressing mode represented
2405 /// by AM is legal for this target, for a load/store of the specified type.
2406 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2407 const Type *Ty) const {
2408 // The default implementation of this implements a conservative RISCy, r+r and
2409 // r+i addr mode.
2410
2411 // Allows a sign-extended 16-bit immediate field.
2412 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2413 return false;
2414
2415 // No global is ever allowed as a base.
2416 if (AM.BaseGV)
2417 return false;
2418
2419 // Only support r+r,
2420 switch (AM.Scale) {
2421 case 0: // "r+i" or just "i", depending on HasBaseReg.
2422 break;
2423 case 1:
2424 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2425 return false;
2426 // Otherwise we have r+r or r+i.
2427 break;
2428 case 2:
2429 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2430 return false;
2431 // Allow 2*r as r+r.
2432 break;
2433 }
2434
2435 return true;
2436 }
2437
2438 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2439 /// return a DAG expression to select that will generate the same value by
2440 /// multiplying by a magic number. See:
2441 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2442 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2443 std::vector<SDNode*>* Created) const {
2444 MVT VT = N->getValueType(0);
2445 DebugLoc dl= N->getDebugLoc();
2446
2447 // Check to see if we can do this.
2448 // FIXME: We should be more aggressive here.
2449 if (!isTypeLegal(VT))
2450 return SDValue();
2451
2452 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2453 APInt::ms magics = d.magic();
2454
2455 // Multiply the numerator (operand 0) by the magic value
2456 // FIXME: We should support doing a MUL in a wider type
2457 SDValue Q;
2458 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2459 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2460 DAG.getConstant(magics.m, VT));
2461 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2462 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2463 N->getOperand(0),
2464 DAG.getConstant(magics.m, VT)).getNode(), 1);
2465 else
2466 return SDValue(); // No mulhs or equvialent
2467 // If d > 0 and m < 0, add the numerator
2468 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2469 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2470 if (Created)
2471 Created->push_back(Q.getNode());
2472 }
2473 // If d < 0 and m > 0, subtract the numerator.
2474 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2475 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2476 if (Created)
2477 Created->push_back(Q.getNode());
2478 }
2479 // Shift right algebraic if shift value is nonzero
2480 if (magics.s > 0) {
2481 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2482 DAG.getConstant(magics.s, getShiftAmountTy()));
2483 if (Created)
2484 Created->push_back(Q.getNode());
2485 }
2486 // Extract the sign bit and add it to the quotient
2487 SDValue T =
2488 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2489 getShiftAmountTy()));
2490 if (Created)
2491 Created->push_back(T.getNode());
2492 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2493 }
2494
2495 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2496 /// return a DAG expression to select that will generate the same value by
2497 /// multiplying by a magic number. See:
2498 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2499 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2500 std::vector<SDNode*>* Created) const {
2501 MVT VT = N->getValueType(0);
2502 DebugLoc dl = N->getDebugLoc();
2503
2504 // Check to see if we can do this.
2505 // FIXME: We should be more aggressive here.
2506 if (!isTypeLegal(VT))
2507 return SDValue();
2508
2509 // FIXME: We should use a narrower constant when the upper
2510 // bits are known to be zero.
2511 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2512 APInt::mu magics = N1C->getAPIntValue().magicu();
2513
2514 // Multiply the numerator (operand 0) by the magic value
2515 // FIXME: We should support doing a MUL in a wider type
2516 SDValue Q;
2517 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2518 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2519 DAG.getConstant(magics.m, VT));
2520 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2521 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2522 N->getOperand(0),
2523 DAG.getConstant(magics.m, VT)).getNode(), 1);
2524 else
2525 return SDValue(); // No mulhu or equvialent
2526 if (Created)
2527 Created->push_back(Q.getNode());
2528
2529 if (magics.a == 0) {
2530 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2531 "We shouldn't generate an undefined shift!");
2532 return DAG.getNode(ISD::SRL, dl, VT, Q,
2533 DAG.getConstant(magics.s, getShiftAmountTy()));
2534 } else {
2535 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2536 if (Created)
2537 Created->push_back(NPQ.getNode());
2538 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2539 DAG.getConstant(1, getShiftAmountTy()));
2540 if (Created)
2541 Created->push_back(NPQ.getNode());
2542 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2543 if (Created)
2544 Created->push_back(NPQ.getNode());
2545 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2546 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2547 }
2548 }
2549
2550 /// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET
2551 /// node that don't prevent tail call optimization.
2552 static SDValue IgnoreHarmlessInstructions(SDValue node) {
2553 // Found call return.
2554 if (node.getOpcode() == ISD::CALL) return node;
2555 // Ignore MERGE_VALUES. Will have at least one operand.
2556 if (node.getOpcode() == ISD::MERGE_VALUES)
2557 return IgnoreHarmlessInstructions(node.getOperand(0));
2558 // Ignore ANY_EXTEND node.
2559 if (node.getOpcode() == ISD::ANY_EXTEND)
2560 return IgnoreHarmlessInstructions(node.getOperand(0));
2561 if (node.getOpcode() == ISD::TRUNCATE)
2562 return IgnoreHarmlessInstructions(node.getOperand(0));
2563 // Any other node type.
2564 return node;
2565 }
2566
2567 bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall,
2568 SDValue Ret) {
2569 unsigned NumOps = Ret.getNumOperands();
2570 // ISD::CALL results:(value0, ..., valuen, chain)
2571 // ISD::RET operands:(chain, value0, flag0, ..., valuen, flagn)
2572 // Value return:
2573 // Check that operand of the RET node sources from the CALL node. The RET node
2574 // has at least two operands. Operand 0 holds the chain. Operand 1 holds the
2575 // value.
2576 if (NumOps > 1 &&
2577 IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0))
2578 return true;
2579 // void return: The RET node has the chain result value of the CALL node as
2580 // input.
2581 if (NumOps == 1 &&
2582 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1))
2583 return true;
2584
2585 return false;
2586 }
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