lib/Target/ARM/ARMCodeEmitter.cpp

   1 //===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the pass that transforms the ARM machine instructions into
  11 // relocatable machine code.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "jit"
  16 #include "ARM.h"
  17 #include "ARMAddressingModes.h"
  18 #include "ARMConstantPoolValue.h"
  19 #include "ARMInstrInfo.h"
  20 #include "ARMRelocations.h"
  21 #include "ARMSubtarget.h"
  22 #include "ARMTargetMachine.h"
  23 #include "llvm/Constants.h"
  24 #include "llvm/DerivedTypes.h"
  25 #include "llvm/Function.h"
  26 #include "llvm/PassManager.h"
  27 #include "llvm/CodeGen/MachineCodeEmitter.h"
  28 #include "llvm/CodeGen/MachineConstantPool.h"
  29 #include "llvm/CodeGen/MachineFunctionPass.h"
  30 #include "llvm/CodeGen/MachineInstr.h"
  31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  32 #include "llvm/CodeGen/Passes.h"
  33 #include "llvm/ADT/Statistic.h"
  34 #include "llvm/Support/Compiler.h"
  35 #include "llvm/Support/Debug.h"
  36 #ifndef NDEBUG
  37 #include <iomanip>
  38 #endif
  39 using namespace llvm;
  40
  41 STATISTIC(NumEmitted, "Number of machine instructions emitted");
  42
  43 namespace {
  44   class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
  45     ARMJITInfo                *JTI;
  46     const ARMInstrInfo        *II;
  47     const TargetData          *TD;
  48     TargetMachine             &TM;
  49     MachineCodeEmitter        &MCE;
  50     const std::vector<MachineConstantPoolEntry> *MCPEs;
  51     const std::vector<MachineJumpTableEntry> *MJTEs;
  52     bool IsPIC;
  53
  54   public:
  55     static char ID;
  56     explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
  57       : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
  58       MCE(mce), MCPEs(0), MJTEs(0),
  59       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  60     ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
  61             const ARMInstrInfo &ii, const TargetData &td)
  62       : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
  63       MCE(mce), MCPEs(0), MJTEs(0),
  64       IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
  65
  66     bool runOnMachineFunction(MachineFunction &MF);
  67
  68     virtual const char *getPassName() const {
  69       return "ARM Machine Code Emitter";
  70     }
  71
  72     void emitInstruction(const MachineInstr &MI);
  73
  74   private:
  75
  76     void emitWordLE(unsigned Binary);
  77
  78     void emitDWordLE(uint64_t Binary);
  79
  80     void emitConstPoolInstruction(const MachineInstr &MI);
  81
  82     void emitMOVi2piecesInstruction(const MachineInstr &MI);
  83
  84     void emitLEApcrelJTInstruction(const MachineInstr &MI);
  85
  86     void emitPseudoMoveInstruction(const MachineInstr &MI);
  87
  88     void addPCLabel(unsigned LabelID);
  89
  90     void emitPseudoInstruction(const MachineInstr &MI);
  91
  92     unsigned getMachineSoRegOpValue(const MachineInstr &MI,
  93                                     const TargetInstrDesc &TID,
  94                                     const MachineOperand &MO,
  95                                     unsigned OpIdx);
  96
  97     unsigned getMachineSoImmOpValue(unsigned SoImm);
  98
  99     unsigned getAddrModeSBit(const MachineInstr &MI,
 100                              const TargetInstrDesc &TID) const;
 101
 102     void emitDataProcessingInstruction(const MachineInstr &MI,
 103                                        unsigned ImplicitRd = 0,
 104                                        unsigned ImplicitRn = 0);
 105
 106     void emitLoadStoreInstruction(const MachineInstr &MI,
 107                                   unsigned ImplicitRd = 0,
 108                                   unsigned ImplicitRn = 0);
 109
 110     void emitMiscLoadStoreInstruction(const MachineInstr &MI,
 111                                       unsigned ImplicitRn = 0);
 112
 113     void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
 114
 115     void emitMulFrmInstruction(const MachineInstr &MI);
 116
 117     void emitExtendInstruction(const MachineInstr &MI);
 118
 119     void emitMiscArithInstruction(const MachineInstr &MI);
 120
 121     void emitBranchInstruction(const MachineInstr &MI);
 122
 123     void emitInlineJumpTable(unsigned JTIndex);
 124
 125     void emitMiscBranchInstruction(const MachineInstr &MI);
 126
 127     void emitVFPArithInstruction(const MachineInstr &MI);
 128
 129     void emitVFPConversionInstruction(const MachineInstr &MI);
 130
 131     void emitVFPLoadStoreInstruction(const MachineInstr &MI);
 132
 133     void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
 134
 135     void emitMiscInstruction(const MachineInstr &MI);
 136
 137     /// getBinaryCodeForInstr - This function, generated by the
 138     /// CodeEmitterGenerator using TableGen, produces the binary encoding for
 139     /// machine instructions.
 140     ///
 141     unsigned getBinaryCodeForInstr(const MachineInstr &MI);
 142
 143     /// getMachineOpValue - Return binary encoding of operand. If the machine
 144     /// operand requires relocation, record the relocation and return zero.
 145     unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
 146     unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
 147       return getMachineOpValue(MI, MI.getOperand(OpIdx));
 148     }
 149
 150     /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
 151     ///
 152     unsigned getShiftOp(unsigned Imm) const ;
 153
 154     /// Routines that handle operands which add machine relocations which are
 155     /// fixed up by the relocation stage.
 156     void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
 157                            bool NeedStub, intptr_t ACPV = 0);
 158     void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
 159     void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
 160     void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
 161     void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
 162                                intptr_t JTBase = 0);
 163   };
 164   char ARMCodeEmitter::ID = 0;
 165 }
 166
 167 /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
 168 /// to the specified MCE object.
 169 FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
 170                                              MachineCodeEmitter &MCE) {
 171   return new ARMCodeEmitter(TM, MCE);
 172 }
 173
 174 bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
 175   assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
 176           MF.getTarget().getRelocationModel() != Reloc::Static) &&
 177          "JIT relocation model must be set to static or default!");
 178   II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
 179   TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
 180   JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
 181   MCPEs = &MF.getConstantPool()->getConstants();
 182   MJTEs = &MF.getJumpTableInfo()->getJumpTables();
 183   IsPIC = TM.getRelocationModel() == Reloc::PIC_;
 184   JTI->Initialize(MF, IsPIC);
 185
 186   do {
 187     DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
 188     MCE.startFunction(MF);
 189     for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
 190          MBB != E; ++MBB) {
 191       MCE.StartMachineBasicBlock(MBB);
 192       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
 193            I != E; ++I)
 194         emitInstruction(*I);
 195     }
 196   } while (MCE.finishFunction(MF));
 197
 198   return false;
 199 }
 200
 201 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
 202 ///
 203 unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
 204   switch (ARM_AM::getAM2ShiftOpc(Imm)) {
 205   default: assert(0 && "Unknown shift opc!");
 206   case ARM_AM::asr: return 2;
 207   case ARM_AM::lsl: return 0;
 208   case ARM_AM::lsr: return 1;
 209   case ARM_AM::ror:
 210   case ARM_AM::rrx: return 3;
 211   }
 212   return 0;
 213 }
 214
 215 /// getMachineOpValue - Return binary encoding of operand. If the machine
 216 /// operand requires relocation, record the relocation and return zero.
 217 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
 218                                            const MachineOperand &MO) {
 219   if (MO.isReg())
 220     return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
 221   else if (MO.isImm())
 222     return static_cast<unsigned>(MO.getImm());
 223   else if (MO.isGlobal())
 224     emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
 225   else if (MO.isSymbol())
 226     emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
 227   else if (MO.isCPI()) {
 228     const TargetInstrDesc &TID = MI.getDesc();
 229     // For VFP load, the immediate offset is multiplied by 4.
 230     unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
 231       ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
 232     emitConstPoolAddress(MO.getIndex(), Reloc);
 233   } else if (MO.isJTI())
 234     emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
 235   else if (MO.isMBB())
 236     emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
 237   else {
 238     cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
 239     abort();
 240   }
 241   return 0;
 242 }
 243
 244 /// emitGlobalAddress - Emit the specified address to the code stream.
 245 ///
 246 void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
 247                                        bool NeedStub, intptr_t ACPV) {
 248   MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
 249                                              Reloc, GV, ACPV, NeedStub));
 250 }
 251
 252 /// emitExternalSymbolAddress - Arrange for the address of an external symbol to
 253 /// be emitted to the current location in the function, and allow it to be PC
 254 /// relative.
 255 void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
 256   MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
 257                                                  Reloc, ES));
 258 }
 259
 260 /// emitConstPoolAddress - Arrange for the address of an constant pool
 261 /// to be emitted to the current location in the function, and allow it to be PC
 262 /// relative.
 263 void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
 264   // Tell JIT emitter we'll resolve the address.
 265   MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
 266                                                     Reloc, CPI, 0, true));
 267 }
 268
 269 /// emitJumpTableAddress - Arrange for the address of a jump table to
 270 /// be emitted to the current location in the function, and allow it to be PC
 271 /// relative.
 272 void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
 273   MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
 274                                                     Reloc, JTIndex, 0, true));
 275 }
 276
 277 /// emitMachineBasicBlock - Emit the specified address basic block.
 278 void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
 279                                            unsigned Reloc, intptr_t JTBase) {
 280   MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
 281                                              Reloc, BB, JTBase));
 282 }
 283
 284 void ARMCodeEmitter::emitWordLE(unsigned Binary) {
 285 #ifndef NDEBUG
 286   DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
 287        << Binary << std::dec << "\n";
 288 #endif
 289   MCE.emitWordLE(Binary);
 290 }
 291
 292 void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
 293 #ifndef NDEBUG
 294   DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
 295        << (unsigned)Binary << std::dec << "\n";
 296   DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
 297        << (unsigned)(Binary >> 32) << std::dec << "\n";
 298 #endif
 299   MCE.emitDWordLE(Binary);
 300 }
 301
 302 void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
 303   DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
 304
 305   NumEmitted++;  // Keep track of the # of mi's emitted
 306   switch (MI.getDesc().TSFlags & ARMII::FormMask) {
 307   default: {
 308     assert(0 && "Unhandled instruction encoding format!");
 309     break;
 310   }
 311   case ARMII::Pseudo:
 312     emitPseudoInstruction(MI);
 313     break;
 314   case ARMII::DPFrm:
 315   case ARMII::DPSoRegFrm:
 316     emitDataProcessingInstruction(MI);
 317     break;
 318   case ARMII::LdFrm:
 319   case ARMII::StFrm:
 320     emitLoadStoreInstruction(MI);
 321     break;
 322   case ARMII::LdMiscFrm:
 323   case ARMII::StMiscFrm:
 324     emitMiscLoadStoreInstruction(MI);
 325     break;
 326   case ARMII::LdStMulFrm:
 327     emitLoadStoreMultipleInstruction(MI);
 328     break;
 329   case ARMII::MulFrm:
 330     emitMulFrmInstruction(MI);
 331     break;
 332   case ARMII::ExtFrm:
 333     emitExtendInstruction(MI);
 334     break;
 335   case ARMII::ArithMiscFrm:
 336     emitMiscArithInstruction(MI);
 337     break;
 338   case ARMII::BrFrm:
 339     emitBranchInstruction(MI);
 340     break;
 341   case ARMII::BrMiscFrm:
 342     emitMiscBranchInstruction(MI);
 343     break;
 344   // VFP instructions.
 345   case ARMII::VFPUnaryFrm:
 346   case ARMII::VFPBinaryFrm:
 347     emitVFPArithInstruction(MI);
 348     break;
 349   case ARMII::VFPConv1Frm:
 350   case ARMII::VFPConv2Frm:
 351   case ARMII::VFPConv3Frm:
 352   case ARMII::VFPConv4Frm:
 353   case ARMII::VFPConv5Frm:
 354     emitVFPConversionInstruction(MI);
 355     break;
 356   case ARMII::VFPLdStFrm:
 357     emitVFPLoadStoreInstruction(MI);
 358     break;
 359   case ARMII::VFPLdStMulFrm:
 360     emitVFPLoadStoreMultipleInstruction(MI);
 361     break;
 362   case ARMII::VFPMiscFrm:
 363     emitMiscInstruction(MI);
 364     break;
 365   }
 366 }
 367
 368 void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
 369   unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
 370   unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
 371   const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
 372
 373   // Remember the CONSTPOOL_ENTRY address for later relocation.
 374   JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
 375
 376   // Emit constpool island entry. In most cases, the actual values will be
 377   // resolved and relocated after code emission.
 378   if (MCPE.isMachineConstantPoolEntry()) {
 379     ARMConstantPoolValue *ACPV =
 380       static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
 381
 382     DOUT << "  ** ARM constant pool #" << CPI << " @ "
 383          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
 384
 385     GlobalValue *GV = ACPV->getGV();
 386     if (GV) {
 387       assert(!ACPV->isStub() && "Don't know how to deal this yet!");
 388       if (ACPV->isNonLazyPointer())
 389         MCE.addRelocation(MachineRelocation::getIndirectSymbol(
 390                   MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
 391                   (intptr_t)ACPV, false));
 392       else
 393         emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
 394                           ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
 395      } else  {
 396       assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
 397       emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
 398     }
 399     emitWordLE(0);
 400   } else {
 401     Constant *CV = MCPE.Val.ConstVal;
 402
 403 #ifndef NDEBUG
 404     DOUT << "  ** Constant pool #" << CPI << " @ "
 405          << (void*)MCE.getCurrentPCValue() << " ";
 406     if (const Function *F = dyn_cast<Function>(CV))
 407       DOUT << F->getName();
 408     else
 409       DOUT << *CV;
 410     DOUT << '\n';
 411 #endif
 412
 413     if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
 414       emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
 415       emitWordLE(0);
 416     } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
 417       uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
 418       emitWordLE(Val);
 419     } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
 420       if (CFP->getType() == Type::FloatTy)
 421         emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
 422       else if (CFP->getType() == Type::DoubleTy)
 423         emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
 424       else {
 425         assert(0 && "Unable to handle this constantpool entry!");
 426         abort();
 427       }
 428     } else {
 429       assert(0 && "Unable to handle this constantpool entry!");
 430       abort();
 431     }
 432   }
 433 }
 434
 435 void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
 436   const MachineOperand &MO0 = MI.getOperand(0);
 437   const MachineOperand &MO1 = MI.getOperand(1);
 438   assert(MO1.isImm() && "Not a valid so_imm value!");
 439   unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
 440   unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
 441
 442   // Emit the 'mov' instruction.
 443   unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
 444
 445   // Set the conditional execution predicate.
 446   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 447
 448   // Encode Rd.
 449   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
 450
 451   // Encode so_imm.
 452   // Set bit I(25) to identify this is the immediate form of <shifter_op>
 453   Binary |= 1 << ARMII::I_BitShift;
 454   Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
 455   emitWordLE(Binary);
 456
 457   // Now the 'orr' instruction.
 458   Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
 459
 460   // Set the conditional execution predicate.
 461   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 462
 463   // Encode Rd.
 464   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
 465
 466   // Encode Rn.
 467   Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
 468
 469   // Encode so_imm.
 470   // Set bit I(25) to identify this is the immediate form of <shifter_op>
 471   Binary |= 1 << ARMII::I_BitShift;
 472   Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
 473   emitWordLE(Binary);
 474 }
 475
 476 void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
 477   // It's basically add r, pc, (LJTI - $+8)
 478
 479   const TargetInstrDesc &TID = MI.getDesc();
 480
 481   // Emit the 'add' instruction.
 482   unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
 483
 484   // Set the conditional execution predicate
 485   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 486
 487   // Encode S bit if MI modifies CPSR.
 488   Binary |= getAddrModeSBit(MI, TID);
 489
 490   // Encode Rd.
 491   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
 492
 493   // Encode Rn which is PC.
 494   Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
 495
 496   // Encode the displacement.
 497   // Set bit I(25) to identify this is the immediate form of <shifter_op>.
 498   Binary |= 1 << ARMII::I_BitShift;
 499   emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
 500
 501   emitWordLE(Binary);
 502 }
 503
 504 void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
 505   unsigned Opcode = MI.getDesc().Opcode;
 506
 507   // Part of binary is determined by TableGn.
 508   unsigned Binary = getBinaryCodeForInstr(MI);
 509
 510   // Set the conditional execution predicate
 511   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 512
 513   // Encode S bit if MI modifies CPSR.
 514   if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
 515     Binary |= 1 << ARMII::S_BitShift;
 516
 517   // Encode register def if there is one.
 518   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
 519
 520   // Encode the shift operation.
 521   switch (Opcode) {
 522   default: break;
 523   case ARM::MOVrx:
 524     // rrx
 525     Binary |= 0x6 << 4;
 526     break;
 527   case ARM::MOVsrl_flag:
 528     // lsr #1
 529     Binary |= (0x2 << 4) | (1 << 7);
 530     break;
 531   case ARM::MOVsra_flag:
 532     // asr #1
 533     Binary |= (0x4 << 4) | (1 << 7);
 534     break;
 535   }
 536
 537   // Encode register Rm.
 538   Binary |= getMachineOpValue(MI, 1);
 539
 540   emitWordLE(Binary);
 541 }
 542
 543 void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
 544   DOUT << "  ** LPC" << LabelID << " @ "
 545        << (void*)MCE.getCurrentPCValue() << '\n';
 546   JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
 547 }
 548
 549 void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
 550   unsigned Opcode = MI.getDesc().Opcode;
 551   switch (Opcode) {
 552   default:
 553     abort(); // FIXME:
 554   case TargetInstrInfo::INLINEASM: {
 555     // We allow inline assembler nodes with empty bodies - they can
 556     // implicitly define registers, which is ok for JIT.
 557     if (MI.getOperand(0).getSymbolName()[0]) {
 558       assert(0 && "JIT does not support inline asm!\n");
 559       abort();
 560     }
 561     break;
 562   }
 563   case TargetInstrInfo::DBG_LABEL:
 564   case TargetInstrInfo::EH_LABEL:
 565     MCE.emitLabel(MI.getOperand(0).getImm());
 566     break;
 567   case TargetInstrInfo::IMPLICIT_DEF:
 568   case TargetInstrInfo::DECLARE:
 569   case ARM::DWARF_LOC:
 570     // Do nothing.
 571     break;
 572   case ARM::CONSTPOOL_ENTRY:
 573     emitConstPoolInstruction(MI);
 574     break;
 575   case ARM::PICADD: {
 576     // Remember of the address of the PC label for relocation later.
 577     addPCLabel(MI.getOperand(2).getImm());
 578     // PICADD is just an add instruction that implicitly read pc.
 579     emitDataProcessingInstruction(MI, 0, ARM::PC);
 580     break;
 581   }
 582   case ARM::PICLDR:
 583   case ARM::PICLDRB:
 584   case ARM::PICSTR:
 585   case ARM::PICSTRB: {
 586     // Remember of the address of the PC label for relocation later.
 587     addPCLabel(MI.getOperand(2).getImm());
 588     // These are just load / store instructions that implicitly read pc.
 589     emitLoadStoreInstruction(MI, 0, ARM::PC);
 590     break;
 591   }
 592   case ARM::PICLDRH:
 593   case ARM::PICLDRSH:
 594   case ARM::PICLDRSB:
 595   case ARM::PICSTRH: {
 596     // Remember of the address of the PC label for relocation later.
 597     addPCLabel(MI.getOperand(2).getImm());
 598     // These are just load / store instructions that implicitly read pc.
 599     emitMiscLoadStoreInstruction(MI, ARM::PC);
 600     break;
 601   }
 602   case ARM::MOVi2pieces:
 603     // Two instructions to materialize a constant.
 604     emitMOVi2piecesInstruction(MI);
 605     break;
 606   case ARM::LEApcrelJT:
 607     // Materialize jumptable address.
 608     emitLEApcrelJTInstruction(MI);
 609     break;
 610   case ARM::MOVrx:
 611   case ARM::MOVsrl_flag:
 612   case ARM::MOVsra_flag:
 613     emitPseudoMoveInstruction(MI);
 614     break;
 615   }
 616 }
 617
 618
 619 unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
 620                                                 const TargetInstrDesc &TID,
 621                                                 const MachineOperand &MO,
 622                                                 unsigned OpIdx) {
 623   unsigned Binary = getMachineOpValue(MI, MO);
 624
 625   const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
 626   const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
 627   ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
 628
 629   // Encode the shift opcode.
 630   unsigned SBits = 0;
 631   unsigned Rs = MO1.getReg();
 632   if (Rs) {
 633     // Set shift operand (bit[7:4]).
 634     // LSL - 0001
 635     // LSR - 0011
 636     // ASR - 0101
 637     // ROR - 0111
 638     // RRX - 0110 and bit[11:8] clear.
 639     switch (SOpc) {
 640     default: assert(0 && "Unknown shift opc!");
 641     case ARM_AM::lsl: SBits = 0x1; break;
 642     case ARM_AM::lsr: SBits = 0x3; break;
 643     case ARM_AM::asr: SBits = 0x5; break;
 644     case ARM_AM::ror: SBits = 0x7; break;
 645     case ARM_AM::rrx: SBits = 0x6; break;
 646     }
 647   } else {
 648     // Set shift operand (bit[6:4]).
 649     // LSL - 000
 650     // LSR - 010
 651     // ASR - 100
 652     // ROR - 110
 653     switch (SOpc) {
 654     default: assert(0 && "Unknown shift opc!");
 655     case ARM_AM::lsl: SBits = 0x0; break;
 656     case ARM_AM::lsr: SBits = 0x2; break;
 657     case ARM_AM::asr: SBits = 0x4; break;
 658     case ARM_AM::ror: SBits = 0x6; break;
 659     }
 660   }
 661   Binary |= SBits << 4;
 662   if (SOpc == ARM_AM::rrx)
 663     return Binary;
 664
 665   // Encode the shift operation Rs or shift_imm (except rrx).
 666   if (Rs) {
 667     // Encode Rs bit[11:8].
 668     assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
 669     return Binary |
 670       (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
 671   }
 672
 673   // Encode shift_imm bit[11:7].
 674   return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
 675 }
 676
 677 unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
 678   // Encode rotate_imm.
 679   unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
 680     << ARMII::SoRotImmShift;
 681
 682   // Encode immed_8.
 683   Binary |= ARM_AM::getSOImmValImm(SoImm);
 684   return Binary;
 685 }
 686
 687 unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
 688                                          const TargetInstrDesc &TID) const {
 689   for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
 690     const MachineOperand &MO = MI.getOperand(i-1);
 691     if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
 692       return 1 << ARMII::S_BitShift;
 693   }
 694   return 0;
 695 }
 696
 697 void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
 698                                                    unsigned ImplicitRd,
 699                                                    unsigned ImplicitRn) {
 700   const TargetInstrDesc &TID = MI.getDesc();
 701
 702   // Part of binary is determined by TableGn.
 703   unsigned Binary = getBinaryCodeForInstr(MI);
 704
 705   // Set the conditional execution predicate
 706   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 707
 708   // Encode S bit if MI modifies CPSR.
 709   Binary |= getAddrModeSBit(MI, TID);
 710
 711   // Encode register def if there is one.
 712   unsigned NumDefs = TID.getNumDefs();
 713   unsigned OpIdx = 0;
 714   if (NumDefs)
 715     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
 716   else if (ImplicitRd)
 717     // Special handling for implicit use (e.g. PC).
 718     Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
 719                << ARMII::RegRdShift);
 720
 721   // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
 722   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
 723     ++OpIdx;
 724
 725   // Encode first non-shifter register operand if there is one.
 726   bool isUnary = TID.TSFlags & ARMII::UnaryDP;
 727   if (!isUnary) {
 728     if (ImplicitRn)
 729       // Special handling for implicit use (e.g. PC).
 730       Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
 731                  << ARMII::RegRnShift);
 732     else {
 733       Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
 734       ++OpIdx;
 735     }
 736   }
 737
 738   // Encode shifter operand.
 739   const MachineOperand &MO = MI.getOperand(OpIdx);
 740   if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
 741     // Encode SoReg.
 742     emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
 743     return;
 744   }
 745
 746   if (MO.isReg()) {
 747     // Encode register Rm.
 748     emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
 749     return;
 750   }
 751
 752   // Encode so_imm.
 753   // Set bit I(25) to identify this is the immediate form of <shifter_op>.
 754   Binary |= 1 << ARMII::I_BitShift;
 755   Binary |= getMachineSoImmOpValue(MO.getImm());
 756
 757   emitWordLE(Binary);
 758 }
 759
 760 void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
 761                                               unsigned ImplicitRd,
 762                                               unsigned ImplicitRn) {
 763   const TargetInstrDesc &TID = MI.getDesc();
 764   unsigned Form = TID.TSFlags & ARMII::FormMask;
 765   bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
 766
 767   // Part of binary is determined by TableGn.
 768   unsigned Binary = getBinaryCodeForInstr(MI);
 769
 770   // Set the conditional execution predicate
 771   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 772
 773   unsigned OpIdx = 0;
 774
 775   // Operand 0 of a pre- and post-indexed store is the address base
 776   // writeback. Skip it.
 777   bool Skipped = false;
 778   if (IsPrePost && Form == ARMII::StFrm) {
 779     ++OpIdx;
 780     Skipped = true;
 781   }
 782
 783   // Set first operand
 784   if (ImplicitRd)
 785     // Special handling for implicit use (e.g. PC).
 786     Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
 787                << ARMII::RegRdShift);
 788   else
 789     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
 790
 791   // Set second operand
 792   if (ImplicitRn)
 793     // Special handling for implicit use (e.g. PC).
 794     Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
 795                << ARMII::RegRnShift);
 796   else
 797     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
 798
 799   // If this is a two-address operand, skip it. e.g. LDR_PRE.
 800   if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
 801     ++OpIdx;
 802
 803   const MachineOperand &MO2 = MI.getOperand(OpIdx);
 804   unsigned AM2Opc = (ImplicitRn == ARM::PC)
 805     ? 0 : MI.getOperand(OpIdx+1).getImm();
 806
 807   // Set bit U(23) according to sign of immed value (positive or negative).
 808   Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
 809              ARMII::U_BitShift);
 810   if (!MO2.getReg()) { // is immediate
 811     if (ARM_AM::getAM2Offset(AM2Opc))
 812       // Set the value of offset_12 field
 813       Binary |= ARM_AM::getAM2Offset(AM2Opc);
 814     emitWordLE(Binary);
 815     return;
 816   }
 817
 818   // Set bit I(25), because this is not in immediate enconding.
 819   Binary |= 1 << ARMII::I_BitShift;
 820   assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
 821   // Set bit[3:0] to the corresponding Rm register
 822   Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
 823
 824   // If this instr is in scaled register offset/index instruction, set
 825   // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
 826   if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
 827     Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
 828     Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
 829   }
 830
 831   emitWordLE(Binary);
 832 }
 833
 834 void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
 835                                                   unsigned ImplicitRn) {
 836   const TargetInstrDesc &TID = MI.getDesc();
 837   unsigned Form = TID.TSFlags & ARMII::FormMask;
 838   bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
 839
 840   // Part of binary is determined by TableGn.
 841   unsigned Binary = getBinaryCodeForInstr(MI);
 842
 843   // Set the conditional execution predicate
 844   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 845
 846   unsigned OpIdx = 0;
 847
 848   // Operand 0 of a pre- and post-indexed store is the address base
 849   // writeback. Skip it.
 850   bool Skipped = false;
 851   if (IsPrePost && Form == ARMII::StMiscFrm) {
 852     ++OpIdx;
 853     Skipped = true;
 854   }
 855
 856   // Set first operand
 857   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
 858
 859   // Set second operand
 860   if (ImplicitRn)
 861     // Special handling for implicit use (e.g. PC).
 862     Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
 863                << ARMII::RegRnShift);
 864   else
 865     Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
 866
 867   // If this is a two-address operand, skip it. e.g. LDRH_POST.
 868   if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
 869     ++OpIdx;
 870
 871   const MachineOperand &MO2 = MI.getOperand(OpIdx);
 872   unsigned AM3Opc = (ImplicitRn == ARM::PC)
 873     ? 0 : MI.getOperand(OpIdx+1).getImm();
 874
 875   // Set bit U(23) according to sign of immed value (positive or negative)
 876   Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
 877              ARMII::U_BitShift);
 878
 879   // If this instr is in register offset/index encoding, set bit[3:0]
 880   // to the corresponding Rm register.
 881   if (MO2.getReg()) {
 882     Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
 883     emitWordLE(Binary);
 884     return;
 885   }
 886
 887   // This instr is in immediate offset/index encoding, set bit 22 to 1.
 888   Binary |= 1 << ARMII::AM3_I_BitShift;
 889   if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
 890     // Set operands
 891     Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
 892     Binary |= (ImmOffs & 0xF);                      // immedL
 893   }
 894
 895   emitWordLE(Binary);
 896 }
 897
 898 static unsigned getAddrModeUPBits(unsigned Mode) {
 899   unsigned Binary = 0;
 900
 901   // Set addressing mode by modifying bits U(23) and P(24)
 902   // IA - Increment after  - bit U = 1 and bit P = 0
 903   // IB - Increment before - bit U = 1 and bit P = 1
 904   // DA - Decrement after  - bit U = 0 and bit P = 0
 905   // DB - Decrement before - bit U = 0 and bit P = 1
 906   switch (Mode) {
 907   default: assert(0 && "Unknown addressing sub-mode!");
 908   case ARM_AM::da:                      break;
 909   case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
 910   case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
 911   case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
 912   }
 913
 914   return Binary;
 915 }
 916
 917 void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
 918   // Part of binary is determined by TableGn.
 919   unsigned Binary = getBinaryCodeForInstr(MI);
 920
 921   // Set the conditional execution predicate
 922   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 923
 924   // Set base address operand
 925   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
 926
 927   // Set addressing mode by modifying bits U(23) and P(24)
 928   const MachineOperand &MO = MI.getOperand(1);
 929   Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
 930
 931   // Set bit W(21)
 932   if (ARM_AM::getAM4WBFlag(MO.getImm()))
 933     Binary |= 0x1 << ARMII::W_BitShift;
 934
 935   // Set registers
 936   for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
 937     const MachineOperand &MO = MI.getOperand(i);
 938     if (!MO.isReg() || MO.isImplicit())
 939       break;
 940     unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
 941     assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
 942            RegNum < 16);
 943     Binary |= 0x1 << RegNum;
 944   }
 945
 946   emitWordLE(Binary);
 947 }
 948
 949 void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
 950   const TargetInstrDesc &TID = MI.getDesc();
 951
 952   // Part of binary is determined by TableGn.
 953   unsigned Binary = getBinaryCodeForInstr(MI);
 954
 955   // Set the conditional execution predicate
 956   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 957
 958   // Encode S bit if MI modifies CPSR.
 959   Binary |= getAddrModeSBit(MI, TID);
 960
 961   // 32x32->64bit operations have two destination registers. The number
 962   // of register definitions will tell us if that's what we're dealing with.
 963   unsigned OpIdx = 0;
 964   if (TID.getNumDefs() == 2)
 965     Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
 966
 967   // Encode Rd
 968   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
 969
 970   // Encode Rm
 971   Binary |= getMachineOpValue(MI, OpIdx++);
 972
 973   // Encode Rs
 974   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
 975
 976   // Many multiple instructions (e.g. MLA) have three src operands. Encode
 977   // it as Rn (for multiply, that's in the same offset as RdLo.
 978   if (TID.getNumOperands() > OpIdx &&
 979       !TID.OpInfo[OpIdx].isPredicate() &&
 980       !TID.OpInfo[OpIdx].isOptionalDef())
 981     Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
 982
 983   emitWordLE(Binary);
 984 }
 985
 986 void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
 987   const TargetInstrDesc &TID = MI.getDesc();
 988
 989   // Part of binary is determined by TableGn.
 990   unsigned Binary = getBinaryCodeForInstr(MI);
 991
 992   // Set the conditional execution predicate
 993   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
 994
 995   unsigned OpIdx = 0;
 996
 997   // Encode Rd
 998   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
 999
1000   const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1001   const MachineOperand &MO2 = MI.getOperand(OpIdx);
1002   if (MO2.isReg()) {
1003     // Two register operand form.
1004     // Encode Rn.
1005     Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1006
1007     // Encode Rm.
1008     Binary |= getMachineOpValue(MI, MO2);
1009     ++OpIdx;
1010   } else {
1011     Binary |= getMachineOpValue(MI, MO1);
1012   }
1013
1014   // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1015   if (MI.getOperand(OpIdx).isImm() &&
1016       !TID.OpInfo[OpIdx].isPredicate() &&
1017       !TID.OpInfo[OpIdx].isOptionalDef())
1018     Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1019
1020   emitWordLE(Binary);
1021 }
1022
1023 void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1024   const TargetInstrDesc &TID = MI.getDesc();
1025
1026   // Part of binary is determined by TableGn.
1027   unsigned Binary = getBinaryCodeForInstr(MI);
1028
1029   // Set the conditional execution predicate
1030   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1031
1032   unsigned OpIdx = 0;
1033
1034   // Encode Rd
1035   Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1036
1037   const MachineOperand &MO = MI.getOperand(OpIdx++);
1038   if (OpIdx == TID.getNumOperands() ||
1039       TID.OpInfo[OpIdx].isPredicate() ||
1040       TID.OpInfo[OpIdx].isOptionalDef()) {
1041     // Encode Rm and it's done.
1042     Binary |= getMachineOpValue(MI, MO);
1043     emitWordLE(Binary);
1044     return;
1045   }
1046
1047   // Encode Rn.
1048   Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1049
1050   // Encode Rm.
1051   Binary |= getMachineOpValue(MI, OpIdx++);
1052
1053   // Encode shift_imm.
1054   unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1055   assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1056   Binary |= ShiftAmt << ARMII::ShiftShift;
1057
1058   emitWordLE(Binary);
1059 }
1060
1061 void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1062   const TargetInstrDesc &TID = MI.getDesc();
1063
1064   if (TID.Opcode == ARM::TPsoft)
1065     abort(); // FIXME
1066
1067   // Part of binary is determined by TableGn.
1068   unsigned Binary = getBinaryCodeForInstr(MI);
1069
1070   // Set the conditional execution predicate
1071   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1072
1073   // Set signed_immed_24 field
1074   Binary |= getMachineOpValue(MI, 0);
1075
1076   emitWordLE(Binary);
1077 }
1078
1079 void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1080   // Remember the base address of the inline jump table.
1081   uintptr_t JTBase = MCE.getCurrentPCValue();
1082   JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1083   DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1084
1085   // Now emit the jump table entries.
1086   const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1087   for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1088     if (IsPIC)
1089       // DestBB address - JT base.
1090       emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1091     else
1092       // Absolute DestBB address.
1093       emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1094     emitWordLE(0);
1095   }
1096 }
1097
1098 void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1099   const TargetInstrDesc &TID = MI.getDesc();
1100
1101   // Handle jump tables.
1102   if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1103     // First emit a ldr pc, [] instruction.
1104     emitDataProcessingInstruction(MI, ARM::PC);
1105
1106     // Then emit the inline jump table.
1107     unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
1108       ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1109     emitInlineJumpTable(JTIndex);
1110     return;
1111   } else if (TID.Opcode == ARM::BR_JTm) {
1112     // First emit a ldr pc, [] instruction.
1113     emitLoadStoreInstruction(MI, ARM::PC);
1114
1115     // Then emit the inline jump table.
1116     emitInlineJumpTable(MI.getOperand(3).getIndex());
1117     return;
1118   }
1119
1120   // Part of binary is determined by TableGn.
1121   unsigned Binary = getBinaryCodeForInstr(MI);
1122
1123   // Set the conditional execution predicate
1124   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1125
1126   if (TID.Opcode == ARM::BX_RET)
1127     // The return register is LR.
1128     Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1129   else
1130     // otherwise, set the return register
1131     Binary |= getMachineOpValue(MI, 0);
1132
1133   emitWordLE(Binary);
1134 }
1135
1136 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1137   unsigned RegD = MI.getOperand(OpIdx).getReg();
1138   unsigned Binary = 0;
1139   bool isSPVFP = false;
1140   RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1141   if (!isSPVFP)
1142     Binary |=   RegD               << ARMII::RegRdShift;
1143   else {
1144     Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1145     Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1146   }
1147   return Binary;
1148 }
1149
1150 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1151   unsigned RegN = MI.getOperand(OpIdx).getReg();
1152   unsigned Binary = 0;
1153   bool isSPVFP = false;
1154   RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1155   if (!isSPVFP)
1156     Binary |=   RegN               << ARMII::RegRnShift;
1157   else {
1158     Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1159     Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1160   }
1161   return Binary;
1162 }
1163
1164 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1165   unsigned RegM = MI.getOperand(OpIdx).getReg();
1166   unsigned Binary = 0;
1167   bool isSPVFP = false;
1168   RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1169   if (!isSPVFP)
1170     Binary |=   RegM;
1171   else {
1172     Binary |= ((RegM & 0x1E) >> 1);
1173     Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1174   }
1175   return Binary;
1176 }
1177
1178 void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1179   const TargetInstrDesc &TID = MI.getDesc();
1180
1181   // Part of binary is determined by TableGn.
1182   unsigned Binary = getBinaryCodeForInstr(MI);
1183
1184   // Set the conditional execution predicate
1185   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1186
1187   unsigned OpIdx = 0;
1188   assert((Binary & ARMII::D_BitShift) == 0 &&
1189          (Binary & ARMII::N_BitShift) == 0 &&
1190          (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1191
1192   // Encode Dd / Sd.
1193   Binary |= encodeVFPRd(MI, OpIdx++);
1194
1195   // If this is a two-address operand, skip it, e.g. FMACD.
1196   if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1197     ++OpIdx;
1198
1199   // Encode Dn / Sn.
1200   if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1201     Binary |= encodeVFPRn(MI, OpIdx++);
1202
1203   if (OpIdx == TID.getNumOperands() ||
1204       TID.OpInfo[OpIdx].isPredicate() ||
1205       TID.OpInfo[OpIdx].isOptionalDef()) {
1206     // FCMPEZD etc. has only one operand.
1207     emitWordLE(Binary);
1208     return;
1209   }
1210
1211   // Encode Dm / Sm.
1212   Binary |= encodeVFPRm(MI, OpIdx);
1213
1214   emitWordLE(Binary);
1215 }
1216
1217 void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1218   const TargetInstrDesc &TID = MI.getDesc();
1219   unsigned Form = TID.TSFlags & ARMII::FormMask;
1220
1221   // Part of binary is determined by TableGn.
1222   unsigned Binary = getBinaryCodeForInstr(MI);
1223
1224   // Set the conditional execution predicate
1225   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1226
1227   switch (Form) {
1228   default: break;
1229   case ARMII::VFPConv1Frm:
1230   case ARMII::VFPConv2Frm:
1231   case ARMII::VFPConv3Frm:
1232     // Encode Dd / Sd.
1233     Binary |= encodeVFPRd(MI, 0);
1234     break;
1235   case ARMII::VFPConv4Frm:
1236     // Encode Dn / Sn.
1237     Binary |= encodeVFPRn(MI, 0);
1238     break;
1239   case ARMII::VFPConv5Frm:
1240     // Encode Dm / Sm.
1241     Binary |= encodeVFPRm(MI, 0);
1242     break;
1243   }
1244
1245   switch (Form) {
1246   default: break;
1247   case ARMII::VFPConv1Frm:
1248     // Encode Dm / Sm.
1249     Binary |= encodeVFPRm(MI, 1);
1250     break;
1251   case ARMII::VFPConv2Frm:
1252   case ARMII::VFPConv3Frm:
1253     // Encode Dn / Sn.
1254     Binary |= encodeVFPRn(MI, 1);
1255     break;
1256   case ARMII::VFPConv4Frm:
1257   case ARMII::VFPConv5Frm:
1258     // Encode Dd / Sd.
1259     Binary |= encodeVFPRd(MI, 1);
1260     break;
1261   }
1262
1263   if (Form == ARMII::VFPConv5Frm)
1264     // Encode Dn / Sn.
1265     Binary |= encodeVFPRn(MI, 2);
1266   else if (Form == ARMII::VFPConv3Frm)
1267     // Encode Dm / Sm.
1268     Binary |= encodeVFPRm(MI, 2);
1269
1270   emitWordLE(Binary);
1271 }
1272
1273 void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1274   // Part of binary is determined by TableGn.
1275   unsigned Binary = getBinaryCodeForInstr(MI);
1276
1277   // Set the conditional execution predicate
1278   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1279
1280   unsigned OpIdx = 0;
1281
1282   // Encode Dd / Sd.
1283   Binary |= encodeVFPRd(MI, OpIdx++);
1284
1285   // Encode address base.
1286   const MachineOperand &Base = MI.getOperand(OpIdx++);
1287   Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1288
1289   // If there is a non-zero immediate offset, encode it.
1290   if (Base.isReg()) {
1291     const MachineOperand &Offset = MI.getOperand(OpIdx);
1292     if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1293       if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1294         Binary |= 1 << ARMII::U_BitShift;
1295       Binary |= ImmOffs;
1296       emitWordLE(Binary);
1297       return;
1298     }
1299   }
1300
1301   // If immediate offset is omitted, default to +0.
1302   Binary |= 1 << ARMII::U_BitShift;
1303
1304   emitWordLE(Binary);
1305 }
1306
1307 void
1308 ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1309   // Part of binary is determined by TableGn.
1310   unsigned Binary = getBinaryCodeForInstr(MI);
1311
1312   // Set the conditional execution predicate
1313   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1314
1315   // Set base address operand
1316   Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1317
1318   // Set addressing mode by modifying bits U(23) and P(24)
1319   const MachineOperand &MO = MI.getOperand(1);
1320   Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1321
1322   // Set bit W(21)
1323   if (ARM_AM::getAM5WBFlag(MO.getImm()))
1324     Binary |= 0x1 << ARMII::W_BitShift;
1325
1326   // First register is encoded in Dd.
1327   Binary |= encodeVFPRd(MI, 4);
1328
1329   // Number of registers are encoded in offset field.
1330   unsigned NumRegs = 1;
1331   for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1332     const MachineOperand &MO = MI.getOperand(i);
1333     if (!MO.isReg() || MO.isImplicit())
1334       break;
1335     ++NumRegs;
1336   }
1337   Binary |= NumRegs * 2;
1338
1339   emitWordLE(Binary);
1340 }
1341
1342 void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1343   // Part of binary is determined by TableGn.
1344   unsigned Binary = getBinaryCodeForInstr(MI);
1345
1346   // Set the conditional execution predicate
1347   Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1348
1349   emitWordLE(Binary);
1350 }
1351
1352 #include "ARMGenCodeEmitter.inc"