Update comments.
[llvm/msp430.git] / lib / Target / CellSPU / SPUHazardRecognizers.cpp
blobcaaa71a422fb80ac7b712ce1c96740ed13bfcbd2
1 //===-- SPUHazardRecognizers.cpp - Cell Hazard Recognizer Impls -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements hazard recognizers for scheduling on Cell SPU
11 // processors.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "sched"
17 #include "SPUHazardRecognizers.h"
18 #include "SPU.h"
19 #include "SPUInstrInfo.h"
20 #include "llvm/CodeGen/ScheduleDAG.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
22 #include "llvm/Support/Debug.h"
24 using namespace llvm;
26 //===----------------------------------------------------------------------===//
27 // Cell SPU hazard recognizer
29 // This is the pipeline hazard recognizer for the Cell SPU processor. It does
30 // very little right now.
31 //===----------------------------------------------------------------------===//
33 SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) :
34 TII(tii),
35 EvenOdd(0)
39 /// Return the pipeline hazard type encountered or generated by this
40 /// instruction. Currently returns NoHazard.
41 ///
42 /// \return NoHazard
43 ScheduleHazardRecognizer::HazardType
44 SPUHazardRecognizer::getHazardType(SUnit *SU)
46 // Initial thoughts on how to do this, but this code cannot work unless the
47 // function's prolog and epilog code are also being scheduled so that we can
48 // accurately determine which pipeline is being scheduled.
49 #if 0
50 const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
51 ScheduleHazardRecognizer::HazardType retval = NoHazard;
52 bool mustBeOdd = false;
54 switch (Node->getOpcode()) {
55 case SPU::LQDv16i8:
56 case SPU::LQDv8i16:
57 case SPU::LQDv4i32:
58 case SPU::LQDv4f32:
59 case SPU::LQDv2f64:
60 case SPU::LQDr128:
61 case SPU::LQDr64:
62 case SPU::LQDr32:
63 case SPU::LQDr16:
64 case SPU::LQAv16i8:
65 case SPU::LQAv8i16:
66 case SPU::LQAv4i32:
67 case SPU::LQAv4f32:
68 case SPU::LQAv2f64:
69 case SPU::LQAr128:
70 case SPU::LQAr64:
71 case SPU::LQAr32:
72 case SPU::LQXv4i32:
73 case SPU::LQXr128:
74 case SPU::LQXr64:
75 case SPU::LQXr32:
76 case SPU::LQXr16:
77 case SPU::STQDv16i8:
78 case SPU::STQDv8i16:
79 case SPU::STQDv4i32:
80 case SPU::STQDv4f32:
81 case SPU::STQDv2f64:
82 case SPU::STQDr128:
83 case SPU::STQDr64:
84 case SPU::STQDr32:
85 case SPU::STQDr16:
86 case SPU::STQDr8:
87 case SPU::STQAv16i8:
88 case SPU::STQAv8i16:
89 case SPU::STQAv4i32:
90 case SPU::STQAv4f32:
91 case SPU::STQAv2f64:
92 case SPU::STQAr128:
93 case SPU::STQAr64:
94 case SPU::STQAr32:
95 case SPU::STQAr16:
96 case SPU::STQAr8:
97 case SPU::STQXv16i8:
98 case SPU::STQXv8i16:
99 case SPU::STQXv4i32:
100 case SPU::STQXv4f32:
101 case SPU::STQXv2f64:
102 case SPU::STQXr128:
103 case SPU::STQXr64:
104 case SPU::STQXr32:
105 case SPU::STQXr16:
106 case SPU::STQXr8:
107 case SPU::RET:
108 mustBeOdd = true;
109 break;
110 default:
111 // Assume that this instruction can be on the even pipe
112 break;
115 if (mustBeOdd && !EvenOdd)
116 retval = Hazard;
118 DOUT << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard " << retval << "\n";
119 EvenOdd ^= 1;
120 return retval;
121 #else
122 return NoHazard;
123 #endif
126 void SPUHazardRecognizer::EmitInstruction(SUnit *SU)
130 void SPUHazardRecognizer::AdvanceCycle()
132 DOUT << "SPUHazardRecognizer::AdvanceCycle\n";
135 void SPUHazardRecognizer::EmitNoop()
137 AdvanceCycle();