lib/Target/CellSPU/SPURegisterInfo.cpp

   1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Cell implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "reginfo"
  15 #include "SPU.h"
  16 #include "SPURegisterInfo.h"
  17 #include "SPURegisterNames.h"
  18 #include "SPUInstrBuilder.h"
  19 #include "SPUSubtarget.h"
  20 #include "SPUMachineFunction.h"
  21 #include "SPUFrameInfo.h"
  22 #include "llvm/Constants.h"
  23 #include "llvm/Type.h"
  24 #include "llvm/CodeGen/ValueTypes.h"
  25 #include "llvm/CodeGen/MachineInstrBuilder.h"
  26 #include "llvm/CodeGen/MachineModuleInfo.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/MachineFrameInfo.h"
  29 #include "llvm/CodeGen/MachineLocation.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/CodeGen/ValueTypes.h"
  32 #include "llvm/Target/TargetFrameInfo.h"
  33 #include "llvm/Target/TargetInstrInfo.h"
  34 #include "llvm/Target/TargetMachine.h"
  35 #include "llvm/Target/TargetOptions.h"
  36 #include "llvm/Support/CommandLine.h"
  37 #include "llvm/Support/Debug.h"
  38 #include "llvm/Support/MathExtras.h"
  39 #include "llvm/ADT/BitVector.h"
  40 #include "llvm/ADT/STLExtras.h"
  41 #include <cstdlib>
  42
  43 using namespace llvm;
  44
  45 /// getRegisterNumbering - Given the enum value for some register, e.g.
  46 /// PPC::F14, return the number that it corresponds to (e.g. 14).
  47 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
  48   using namespace SPU;
  49   switch (RegEnum) {
  50   case SPU::R0: return 0;
  51   case SPU::R1: return 1;
  52   case SPU::R2: return 2;
  53   case SPU::R3: return 3;
  54   case SPU::R4: return 4;
  55   case SPU::R5: return 5;
  56   case SPU::R6: return 6;
  57   case SPU::R7: return 7;
  58   case SPU::R8: return 8;
  59   case SPU::R9: return 9;
  60   case SPU::R10: return 10;
  61   case SPU::R11: return 11;
  62   case SPU::R12: return 12;
  63   case SPU::R13: return 13;
  64   case SPU::R14: return 14;
  65   case SPU::R15: return 15;
  66   case SPU::R16: return 16;
  67   case SPU::R17: return 17;
  68   case SPU::R18: return 18;
  69   case SPU::R19: return 19;
  70   case SPU::R20: return 20;
  71   case SPU::R21: return 21;
  72   case SPU::R22: return 22;
  73   case SPU::R23: return 23;
  74   case SPU::R24: return 24;
  75   case SPU::R25: return 25;
  76   case SPU::R26: return 26;
  77   case SPU::R27: return 27;
  78   case SPU::R28: return 28;
  79   case SPU::R29: return 29;
  80   case SPU::R30: return 30;
  81   case SPU::R31: return 31;
  82   case SPU::R32: return 32;
  83   case SPU::R33: return 33;
  84   case SPU::R34: return 34;
  85   case SPU::R35: return 35;
  86   case SPU::R36: return 36;
  87   case SPU::R37: return 37;
  88   case SPU::R38: return 38;
  89   case SPU::R39: return 39;
  90   case SPU::R40: return 40;
  91   case SPU::R41: return 41;
  92   case SPU::R42: return 42;
  93   case SPU::R43: return 43;
  94   case SPU::R44: return 44;
  95   case SPU::R45: return 45;
  96   case SPU::R46: return 46;
  97   case SPU::R47: return 47;
  98   case SPU::R48: return 48;
  99   case SPU::R49: return 49;
 100   case SPU::R50: return 50;
 101   case SPU::R51: return 51;
 102   case SPU::R52: return 52;
 103   case SPU::R53: return 53;
 104   case SPU::R54: return 54;
 105   case SPU::R55: return 55;
 106   case SPU::R56: return 56;
 107   case SPU::R57: return 57;
 108   case SPU::R58: return 58;
 109   case SPU::R59: return 59;
 110   case SPU::R60: return 60;
 111   case SPU::R61: return 61;
 112   case SPU::R62: return 62;
 113   case SPU::R63: return 63;
 114   case SPU::R64: return 64;
 115   case SPU::R65: return 65;
 116   case SPU::R66: return 66;
 117   case SPU::R67: return 67;
 118   case SPU::R68: return 68;
 119   case SPU::R69: return 69;
 120   case SPU::R70: return 70;
 121   case SPU::R71: return 71;
 122   case SPU::R72: return 72;
 123   case SPU::R73: return 73;
 124   case SPU::R74: return 74;
 125   case SPU::R75: return 75;
 126   case SPU::R76: return 76;
 127   case SPU::R77: return 77;
 128   case SPU::R78: return 78;
 129   case SPU::R79: return 79;
 130   case SPU::R80: return 80;
 131   case SPU::R81: return 81;
 132   case SPU::R82: return 82;
 133   case SPU::R83: return 83;
 134   case SPU::R84: return 84;
 135   case SPU::R85: return 85;
 136   case SPU::R86: return 86;
 137   case SPU::R87: return 87;
 138   case SPU::R88: return 88;
 139   case SPU::R89: return 89;
 140   case SPU::R90: return 90;
 141   case SPU::R91: return 91;
 142   case SPU::R92: return 92;
 143   case SPU::R93: return 93;
 144   case SPU::R94: return 94;
 145   case SPU::R95: return 95;
 146   case SPU::R96: return 96;
 147   case SPU::R97: return 97;
 148   case SPU::R98: return 98;
 149   case SPU::R99: return 99;
 150   case SPU::R100: return 100;
 151   case SPU::R101: return 101;
 152   case SPU::R102: return 102;
 153   case SPU::R103: return 103;
 154   case SPU::R104: return 104;
 155   case SPU::R105: return 105;
 156   case SPU::R106: return 106;
 157   case SPU::R107: return 107;
 158   case SPU::R108: return 108;
 159   case SPU::R109: return 109;
 160   case SPU::R110: return 110;
 161   case SPU::R111: return 111;
 162   case SPU::R112: return 112;
 163   case SPU::R113: return 113;
 164   case SPU::R114: return 114;
 165   case SPU::R115: return 115;
 166   case SPU::R116: return 116;
 167   case SPU::R117: return 117;
 168   case SPU::R118: return 118;
 169   case SPU::R119: return 119;
 170   case SPU::R120: return 120;
 171   case SPU::R121: return 121;
 172   case SPU::R122: return 122;
 173   case SPU::R123: return 123;
 174   case SPU::R124: return 124;
 175   case SPU::R125: return 125;
 176   case SPU::R126: return 126;
 177   case SPU::R127: return 127;
 178   default:
 179     cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
 180     abort();
 181   }
 182 }
 183
 184 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
 185                                  const TargetInstrInfo &tii) :
 186   SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
 187   Subtarget(subtarget),
 188   TII(tii)
 189 {
 190 }
 191
 192 // SPU's 128-bit registers used for argument passing:
 193 static const unsigned SPU_ArgRegs[] = {
 194   SPU::R3,  SPU::R4,  SPU::R5,  SPU::R6,  SPU::R7,  SPU::R8,  SPU::R9,
 195   SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
 196   SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
 197   SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
 198   SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
 199   SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
 200   SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
 201   SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
 202   SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
 203   SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
 204   SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
 205 };
 206
 207 const unsigned *
 208 SPURegisterInfo::getArgRegs()
 209 {
 210   return SPU_ArgRegs;
 211 }
 212
 213 unsigned
 214 SPURegisterInfo::getNumArgRegs()
 215 {
 216   return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
 217 }
 218
 219 /// getPointerRegClass - Return the register class to use to hold pointers.
 220 /// This is used for addressing modes.
 221 const TargetRegisterClass * SPURegisterInfo::getPointerRegClass() const
 222 {
 223   return &SPU::R32CRegClass;
 224 }
 225
 226 const unsigned *
 227 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
 228 {
 229   // Cell ABI calling convention
 230   static const unsigned SPU_CalleeSaveRegs[] = {
 231     SPU::R80, SPU::R81, SPU::R82, SPU::R83,
 232     SPU::R84, SPU::R85, SPU::R86, SPU::R87,
 233     SPU::R88, SPU::R89, SPU::R90, SPU::R91,
 234     SPU::R92, SPU::R93, SPU::R94, SPU::R95,
 235     SPU::R96, SPU::R97, SPU::R98, SPU::R99,
 236     SPU::R100, SPU::R101, SPU::R102, SPU::R103,
 237     SPU::R104, SPU::R105, SPU::R106, SPU::R107,
 238     SPU::R108, SPU::R109, SPU::R110, SPU::R111,
 239     SPU::R112, SPU::R113, SPU::R114, SPU::R115,
 240     SPU::R116, SPU::R117, SPU::R118, SPU::R119,
 241     SPU::R120, SPU::R121, SPU::R122, SPU::R123,
 242     SPU::R124, SPU::R125, SPU::R126, SPU::R127,
 243     SPU::R2,    /* environment pointer */
 244     SPU::R1,    /* stack pointer */
 245     SPU::R0,    /* link register */
 246     0 /* end */
 247   };
 248
 249   return SPU_CalleeSaveRegs;
 250 }
 251
 252 const TargetRegisterClass* const*
 253 SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
 254 {
 255   // Cell ABI Calling Convention
 256   static const TargetRegisterClass * const SPU_CalleeSaveRegClasses[] = {
 257     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 258     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 259     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 260     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 261     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 262     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 263     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 264     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 265     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 266     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 267     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 268     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 269     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 270     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 271     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 272     &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
 273     &SPU::GPRCRegClass, /* environment pointer */
 274     &SPU::GPRCRegClass, /* stack pointer */
 275     &SPU::GPRCRegClass, /* link register */
 276     0 /* end */
 277   };
 278
 279   return SPU_CalleeSaveRegClasses;
 280 }
 281
 282 /*!
 283  R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
 284  generally unused) are the Cell's reserved registers
 285  */
 286 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 287   BitVector Reserved(getNumRegs());
 288   Reserved.set(SPU::R0);                // LR
 289   Reserved.set(SPU::R1);                // SP
 290   Reserved.set(SPU::R2);                // environment pointer
 291   return Reserved;
 292 }
 293
 294 //===----------------------------------------------------------------------===//
 295 // Stack Frame Processing methods
 296 //===----------------------------------------------------------------------===//
 297
 298 // needsFP - Return true if the specified function should have a dedicated frame
 299 // pointer register.  This is true if the function has variable sized allocas or
 300 // if frame pointer elimination is disabled.
 301 //
 302 static bool needsFP(const MachineFunction &MF) {
 303   const MachineFrameInfo *MFI = MF.getFrameInfo();
 304   return NoFramePointerElim || MFI->hasVarSizedObjects();
 305 }
 306
 307 //--------------------------------------------------------------------------
 308 // hasFP - Return true if the specified function actually has a dedicated frame
 309 // pointer register.  This is true if the function needs a frame pointer and has
 310 // a non-zero stack size.
 311 bool
 312 SPURegisterInfo::hasFP(const MachineFunction &MF) const {
 313   const MachineFrameInfo *MFI = MF.getFrameInfo();
 314   return MFI->getStackSize() && needsFP(MF);
 315 }
 316
 317 //--------------------------------------------------------------------------
 318 void
 319 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
 320                                                MachineBasicBlock &MBB,
 321                                                MachineBasicBlock::iterator I)
 322   const
 323 {
 324   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
 325   MBB.erase(I);
 326 }
 327
 328 void
 329 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
 330                                      RegScavenger *RS) const
 331 {
 332   unsigned i = 0;
 333   MachineInstr &MI = *II;
 334   MachineBasicBlock &MBB = *MI.getParent();
 335   MachineFunction &MF = *MBB.getParent();
 336   MachineFrameInfo *MFI = MF.getFrameInfo();
 337
 338   while (!MI.getOperand(i).isFI()) {
 339     ++i;
 340     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 341   }
 342
 343   MachineOperand &SPOp = MI.getOperand(i);
 344   int FrameIndex = SPOp.getIndex();
 345
 346   // Now add the frame object offset to the offset from r1.
 347   int Offset = MFI->getObjectOffset(FrameIndex);
 348
 349   // Most instructions, except for generated FrameIndex additions using AIr32
 350   // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the
 351   // immediate in operand 2.
 352   unsigned OpNo = 1;
 353   if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
 354     OpNo = 2;
 355
 356   MachineOperand &MO = MI.getOperand(OpNo);
 357
 358   // Offset is biased by $lr's slot at the bottom.
 359   Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
 360   assert((Offset & 0xf) == 0
 361          && "16-byte alignment violated in eliminateFrameIndex");
 362
 363   // Replace the FrameIndex with base register with $sp (aka $r1)
 364   SPOp.ChangeToRegister(SPU::R1, false);
 365   if (Offset > SPUFrameInfo::maxFrameOffset()
 366       || Offset < SPUFrameInfo::minFrameOffset()) {
 367     cerr << "Large stack adjustment ("
 368          << Offset
 369          << ") in SPURegisterInfo::eliminateFrameIndex.";
 370   } else {
 371     MO.ChangeToImmediate(Offset);
 372   }
 373 }
 374
 375 /// determineFrameLayout - Determine the size of the frame and maximum call
 376 /// frame size.
 377 void
 378 SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
 379 {
 380   MachineFrameInfo *MFI = MF.getFrameInfo();
 381
 382   // Get the number of bytes to allocate from the FrameInfo
 383   unsigned FrameSize = MFI->getStackSize();
 384
 385   // Get the alignments provided by the target, and the maximum alignment
 386   // (if any) of the fixed frame objects.
 387   unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
 388   unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
 389   assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
 390   unsigned AlignMask = Align - 1;
 391
 392   // Get the maximum call frame size of all the calls.
 393   unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
 394
 395   // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
 396   // that allocations will be aligned.
 397   if (MFI->hasVarSizedObjects())
 398     maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
 399
 400   // Update maximum call frame size.
 401   MFI->setMaxCallFrameSize(maxCallFrameSize);
 402
 403   // Include call frame size in total.
 404   FrameSize += maxCallFrameSize;
 405
 406   // Make sure the frame is aligned.
 407   FrameSize = (FrameSize + AlignMask) & ~AlignMask;
 408
 409   // Update frame info.
 410   MFI->setStackSize(FrameSize);
 411 }
 412
 413 void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 414                                                            RegScavenger *RS)
 415   const {
 416   // Mark LR and SP unused, since the prolog spills them to stack and
 417   // we don't want anyone else to spill them for us.
 418   //
 419   // Also, unless R2 is really used someday, don't spill it automatically.
 420   MF.getRegInfo().setPhysRegUnused(SPU::R0);
 421   MF.getRegInfo().setPhysRegUnused(SPU::R1);
 422   MF.getRegInfo().setPhysRegUnused(SPU::R2);
 423 }
 424
 425 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
 426 {
 427   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
 428   MachineBasicBlock::iterator MBBI = MBB.begin();
 429   MachineFrameInfo *MFI = MF.getFrameInfo();
 430   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 431   DebugLoc dl = (MBBI != MBB.end() ?
 432                  MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
 433
 434   // Prepare for debug frame info.
 435   bool hasDebugInfo = MMI && MMI->hasDebugInfo();
 436   unsigned FrameLabelId = 0;
 437
 438   // Move MBBI back to the beginning of the function.
 439   MBBI = MBB.begin();
 440
 441   // Work out frame sizes.
 442   determineFrameLayout(MF);
 443   int FrameSize = MFI->getStackSize();
 444
 445   assert((FrameSize & 0xf) == 0
 446          && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
 447
 448   if (FrameSize > 0 || MFI->hasCalls()) {
 449     FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
 450     if (hasDebugInfo) {
 451       // Mark effective beginning of when frame pointer becomes valid.
 452       FrameLabelId = MMI->NextLabelID();
 453       BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId);
 454     }
 455
 456     // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
 457     // for the ABI
 458     BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
 459       .addReg(SPU::R1);
 460     if (isS10Constant(FrameSize)) {
 461       // Spill $sp to adjusted $sp
 462       BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
 463         .addReg(SPU::R1);
 464       // Adjust $sp by required amout
 465       BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
 466         .addImm(FrameSize);
 467     } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
 468       // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
 469       // $r2 to adjust $sp:
 470       BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
 471         .addImm(-16)
 472         .addReg(SPU::R1);
 473       BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
 474         .addImm(FrameSize);
 475       BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1)
 476         .addReg(SPU::R2)
 477         .addReg(SPU::R1);
 478       BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
 479         .addReg(SPU::R1)
 480         .addReg(SPU::R2);
 481       BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
 482         .addReg(SPU::R2)
 483         .addImm(16);
 484       BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
 485         .addReg(SPU::R2)
 486         .addReg(SPU::R1);
 487     } else {
 488       cerr << "Unhandled frame size: " << FrameSize << "\n";
 489       abort();
 490     }
 491
 492     if (hasDebugInfo) {
 493       std::vector<MachineMove> &Moves = MMI->getFrameMoves();
 494
 495       // Show update of SP.
 496       MachineLocation SPDst(MachineLocation::VirtualFP);
 497       MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
 498       Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
 499
 500       // Add callee saved registers to move list.
 501       const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 502       for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
 503         int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
 504         unsigned Reg = CSI[I].getReg();
 505         if (Reg == SPU::R0) continue;
 506         MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
 507         MachineLocation CSSrc(Reg);
 508         Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
 509       }
 510
 511       // Mark effective beginning of when frame pointer is ready.
 512       unsigned ReadyLabelId = MMI->NextLabelID();
 513       BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId);
 514
 515       MachineLocation FPDst(SPU::R1);
 516       MachineLocation FPSrc(MachineLocation::VirtualFP);
 517       Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
 518     }
 519   } else {
 520     // This is a leaf function -- insert a branch hint iff there are
 521     // sufficient number instructions in the basic block. Note that
 522     // this is just a best guess based on the basic block's size.
 523     if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
 524       MachineBasicBlock::iterator MBBI = prior(MBB.end());
 525       dl = MBBI->getDebugLoc();
 526
 527       // Insert terminator label
 528       unsigned BranchLabelId = MMI->NextLabelID();
 529       BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId);
 530     }
 531   }
 532 }
 533
 534 void
 535 SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
 536 {
 537   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 538   const MachineFrameInfo *MFI = MF.getFrameInfo();
 539   int FrameSize = MFI->getStackSize();
 540   int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
 541   DebugLoc dl = MBBI->getDebugLoc();
 542
 543   assert(MBBI->getOpcode() == SPU::RET &&
 544          "Can only insert epilog into returning blocks");
 545   assert((FrameSize & 0xf) == 0
 546          && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
 547   if (FrameSize > 0 || MFI->hasCalls()) {
 548     FrameSize = FrameSize + SPUFrameInfo::minStackSize();
 549     if (isS10Constant(FrameSize + LinkSlotOffset)) {
 550       // Reload $lr, adjust $sp by required amount
 551       // Note: We do this to slightly improve dual issue -- not by much, but it
 552       // is an opportunity for dual issue.
 553       BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
 554         .addImm(FrameSize + LinkSlotOffset)
 555         .addReg(SPU::R1);
 556       BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1)
 557         .addReg(SPU::R1)
 558         .addImm(FrameSize);
 559     } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
 560       // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
 561       // $r2 to adjust $sp:
 562       BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
 563         .addImm(16)
 564         .addReg(SPU::R1);
 565       BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
 566         .addImm(FrameSize);
 567       BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
 568         .addReg(SPU::R1)
 569         .addReg(SPU::R2);
 570       BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
 571         .addImm(16)
 572         .addReg(SPU::R2);
 573       BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
 574         addReg(SPU::R2)
 575         .addImm(16);
 576       BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
 577         .addReg(SPU::R2)
 578         .addReg(SPU::R1);
 579     } else {
 580       cerr << "Unhandled frame size: " << FrameSize << "\n";
 581       abort();
 582     }
 583    }
 584 }
 585
 586 unsigned
 587 SPURegisterInfo::getRARegister() const
 588 {
 589   return SPU::R0;
 590 }
 591
 592 unsigned
 593 SPURegisterInfo::getFrameRegister(MachineFunction &MF) const
 594 {
 595   return SPU::R1;
 596 }
 597
 598 void
 599 SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
 600 {
 601   // Initial state of the frame pointer is R1.
 602   MachineLocation Dst(MachineLocation::VirtualFP);
 603   MachineLocation Src(SPU::R1, 0);
 604   Moves.push_back(MachineMove(0, Dst, Src));
 605 }
 606
 607
 608 int
 609 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 610   // FIXME: Most probably dwarf numbers differs for Linux and Darwin
 611   return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
 612 }
 613
 614 #include "SPUGenRegisterInfo.inc"