lib/Target/Mips/MipsISelLowering.h

   1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Mips uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef MipsISELLOWERING_H
  16 #define MipsISELLOWERING_H
  17
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "Mips.h"
  21 #include "MipsSubtarget.h"
  22
  23 namespace llvm {
  24   namespace MipsISD {
  25     enum NodeType {
  26       // Start the numbering from where ISD NodeType finishes.
  27       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  28
  29       // Jump and link (call)
  30       JmpLink,
  31
  32       // Get the Higher 16 bits from a 32-bit immediate
  33       // No relation with Mips Hi register
  34       Hi,
  35
  36       // Get the Lower 16 bits from a 32-bit immediate
  37       // No relation with Mips Lo register
  38       Lo,
  39
  40       // Handle gp_rel (small data/bss sections) relocation.
  41       GPRel,
  42
  43       // Conditional Move
  44       CMov,
  45
  46       // Select CC Pseudo Instruction
  47       SelectCC,
  48
  49       // Floating Point Select CC Pseudo Instruction
  50       FPSelectCC,
  51
  52       // Floating Point Branch Conditional
  53       FPBrcond,
  54
  55       // Floating Point Compare
  56       FPCmp,
  57
  58       // Return
  59       Ret
  60     };
  61   }
  62
  63   //===--------------------------------------------------------------------===//
  64   // TargetLowering Implementation
  65   //===--------------------------------------------------------------------===//
  66   class MipsTargetLowering : public TargetLowering
  67   {
  68     // FrameIndex for return slot.
  69     int ReturnAddrIndex;
  70   public:
  71
  72     explicit MipsTargetLowering(MipsTargetMachine &TM);
  73
  74     /// LowerOperation - Provide custom lowering hooks for some operations.
  75     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
  76
  77     /// getTargetNodeName - This method returns the name of a target specific
  78     //  DAG node.
  79     virtual const char *getTargetNodeName(unsigned Opcode) const;
  80
  81     /// getSetCCResultType - get the ISD::SETCC result ValueType
  82     MVT getSetCCResultType(MVT VT) const;
  83
  84   private:
  85     // Subtarget Info
  86     const MipsSubtarget *Subtarget;
  87
  88     // Lower Operand helpers
  89     SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
  90                             unsigned CallingConv, SelectionDAG &DAG);
  91     bool IsGlobalInSmallSection(GlobalValue *GV);
  92     bool IsInSmallSection(unsigned Size);
  93
  94     // Lower Operand specifics
  95     SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG);
  96     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG);
  97     SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
  98     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
  99     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
 100     SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
 101     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
 102     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
 103     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
 104     SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
 105     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG);
 106     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
 107
 108     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
 109                                                    MachineBasicBlock *MBB) const;
 110
 111     // Inline asm support
 112     ConstraintType getConstraintType(const std::string &Constraint) const;
 113
 114     std::pair<unsigned, const TargetRegisterClass*>
 115               getRegForInlineAsmConstraint(const std::string &Constraint,
 116               MVT VT) const;
 117
 118     std::vector<unsigned>
 119     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 120               MVT VT) const;
 121
 122     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
 123   };
 124 }
 125
 126 #endif // MipsISELLOWERING_H