lib/Target/Mips/MipsRegisterInfo.cpp

   1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "mips-reg-info"
  15
  16 #include "Mips.h"
  17 #include "MipsSubtarget.h"
  18 #include "MipsRegisterInfo.h"
  19 #include "MipsMachineFunction.h"
  20 #include "llvm/Constants.h"
  21 #include "llvm/Type.h"
  22 #include "llvm/Function.h"
  23 #include "llvm/CodeGen/ValueTypes.h"
  24 #include "llvm/CodeGen/MachineInstrBuilder.h"
  25 #include "llvm/CodeGen/MachineFunction.h"
  26 #include "llvm/CodeGen/MachineFrameInfo.h"
  27 #include "llvm/CodeGen/MachineLocation.h"
  28 #include "llvm/Target/TargetFrameInfo.h"
  29 #include "llvm/Target/TargetMachine.h"
  30 #include "llvm/Target/TargetOptions.h"
  31 #include "llvm/Target/TargetInstrInfo.h"
  32 #include "llvm/Support/CommandLine.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/ADT/BitVector.h"
  35 #include "llvm/ADT/STLExtras.h"
  36
  37 using namespace llvm;
  38
  39 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
  40                                    const TargetInstrInfo &tii)
  41   : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
  42     Subtarget(ST), TII(tii) {}
  43
  44 /// getRegisterNumbering - Given the enum value for some register, e.g.
  45 /// Mips::RA, return the number that it corresponds to (e.g. 31).
  46 unsigned MipsRegisterInfo::
  47 getRegisterNumbering(unsigned RegEnum)
  48 {
  49   switch (RegEnum) {
  50     case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
  51     case Mips::AT   : case Mips::F1 : return 1;
  52     case Mips::V0   : case Mips::F2 : case Mips::D1 : return 2;
  53     case Mips::V1   : case Mips::F3 : return 3;
  54     case Mips::A0   : case Mips::F4 : case Mips::D2 : return 4;
  55     case Mips::A1   : case Mips::F5 : return 5;
  56     case Mips::A2   : case Mips::F6 : case Mips::D3 : return 6;
  57     case Mips::A3   : case Mips::F7 : return 7;
  58     case Mips::T0   : case Mips::F8 : case Mips::D4 : return 8;
  59     case Mips::T1   : case Mips::F9 : return 9;
  60     case Mips::T2   : case Mips::F10: case Mips::D5: return 10;
  61     case Mips::T3   : case Mips::F11: return 11;
  62     case Mips::T4   : case Mips::F12: case Mips::D6: return 12;
  63     case Mips::T5   : case Mips::F13: return 13;
  64     case Mips::T6   : case Mips::F14: case Mips::D7: return 14;
  65     case Mips::T7   : case Mips::F15: return 15;
  66     case Mips::T8   : case Mips::F16: case Mips::D8: return 16;
  67     case Mips::T9   : case Mips::F17: return 17;
  68     case Mips::S0   : case Mips::F18: case Mips::D9: return 18;
  69     case Mips::S1   : case Mips::F19: return 19;
  70     case Mips::S2   : case Mips::F20: case Mips::D10: return 20;
  71     case Mips::S3   : case Mips::F21: return 21;
  72     case Mips::S4   : case Mips::F22: case Mips::D11: return 22;
  73     case Mips::S5   : case Mips::F23: return 23;
  74     case Mips::S6   : case Mips::F24: case Mips::D12: return 24;
  75     case Mips::S7   : case Mips::F25: return 25;
  76     case Mips::K0   : case Mips::F26: case Mips::D13: return 26;
  77     case Mips::K1   : case Mips::F27: return 27;
  78     case Mips::GP   : case Mips::F28: case Mips::D14: return 28;
  79     case Mips::SP   : case Mips::F29: return 29;
  80     case Mips::FP   : case Mips::F30: case Mips::D15: return 30;
  81     case Mips::RA   : case Mips::F31: return 31;
  82     default: assert(0 && "Unknown register number!");
  83   }
  84   return 0; // Not reached
  85 }
  86
  87 unsigned MipsRegisterInfo::getPICCallReg(void) { return Mips::T9; }
  88
  89 //===----------------------------------------------------------------------===//
  90 // Callee Saved Registers methods
  91 //===----------------------------------------------------------------------===//
  92
  93 /// Mips Callee Saved Registers
  94 const unsigned* MipsRegisterInfo::
  95 getCalleeSavedRegs(const MachineFunction *MF) const
  96 {
  97   // Mips callee-save register range is $16-$23, $f20-$f30
  98   static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
  99     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
 100     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
 101     Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
 102     Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
 103   };
 104
 105   static const unsigned BitMode32CalleeSavedRegs[] = {
 106     Mips::S0, Mips::S1, Mips::S2, Mips::S3,
 107     Mips::S4, Mips::S5, Mips::S6, Mips::S7,
 108     Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
 109     Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,0
 110   };
 111
 112   if (Subtarget.isSingleFloat())
 113     return SingleFloatOnlyCalleeSavedRegs;
 114   else
 115     return BitMode32CalleeSavedRegs;
 116 }
 117
 118 /// Mips Callee Saved Register Classes
 119 const TargetRegisterClass* const*
 120 MipsRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
 121 {
 122   static const TargetRegisterClass * const SingleFloatOnlyCalleeSavedRC[] = {
 123     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 124     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 125     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 126     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 127     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 128     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 129     &Mips::FGR32RegClass, &Mips::FGR32RegClass, 0
 130   };
 131
 132   static const TargetRegisterClass * const BitMode32CalleeSavedRC[] = {
 133     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 134     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 135     &Mips::CPURegsRegClass, &Mips::CPURegsRegClass,
 136     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 137     &Mips::FGR32RegClass, &Mips::FGR32RegClass, &Mips::FGR32RegClass,
 138     &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass,
 139     &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, &Mips::AFGR64RegClass, 0
 140   };
 141
 142   if (Subtarget.isSingleFloat())
 143     return SingleFloatOnlyCalleeSavedRC;
 144   else
 145     return BitMode32CalleeSavedRC;
 146 }
 147
 148 BitVector MipsRegisterInfo::
 149 getReservedRegs(const MachineFunction &MF) const
 150 {
 151   BitVector Reserved(getNumRegs());
 152   Reserved.set(Mips::ZERO);
 153   Reserved.set(Mips::AT);
 154   Reserved.set(Mips::K0);
 155   Reserved.set(Mips::K1);
 156   Reserved.set(Mips::GP);
 157   Reserved.set(Mips::SP);
 158   Reserved.set(Mips::FP);
 159   Reserved.set(Mips::RA);
 160
 161   // SRV4 requires that odd register can't be used.
 162   if (!Subtarget.isSingleFloat())
 163     for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
 164       Reserved.set(FReg);
 165
 166   return Reserved;
 167 }
 168
 169 //===----------------------------------------------------------------------===//
 170 //
 171 // Stack Frame Processing methods
 172 // +----------------------------+
 173 //
 174 // The stack is allocated decrementing the stack pointer on
 175 // the first instruction of a function prologue. Once decremented,
 176 // all stack referencesare are done thought a positive offset
 177 // from the stack/frame pointer, so the stack is considering
 178 // to grow up! Otherwise terrible hacks would have to be made
 179 // to get this stack ABI compliant :)
 180 //
 181 //  The stack frame required by the ABI (after call):
 182 //  Offset
 183 //
 184 //  0                 ----------
 185 //  4                 Args to pass
 186 //  .                 saved $GP  (used in PIC)
 187 //  .                 Alloca allocations
 188 //  .                 Local Area
 189 //  .                 CPU "Callee Saved" Registers
 190 //  .                 saved FP
 191 //  .                 saved RA
 192 //  .                 FPU "Callee Saved" Registers
 193 //  StackSize         -----------
 194 //
 195 // Offset - offset from sp after stack allocation on function prologue
 196 //
 197 // The sp is the stack pointer subtracted/added from the stack size
 198 // at the Prologue/Epilogue
 199 //
 200 // References to the previous stack (to obtain arguments) are done
 201 // with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
 202 //
 203 // Examples:
 204 // - reference to the actual stack frame
 205 //   for any local area var there is smt like : FI >= 0, StackOffset: 4
 206 //     sw REGX, 4(SP)
 207 //
 208 // - reference to previous stack frame
 209 //   suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
 210 //   The emitted instruction will be something like:
 211 //     lw REGX, 16+StackSize(SP)
 212 //
 213 // Since the total stack size is unknown on LowerFORMAL_ARGUMENTS, all
 214 // stack references (ObjectOffset) created to reference the function
 215 // arguments, are negative numbers. This way, on eliminateFrameIndex it's
 216 // possible to detect those references and the offsets are adjusted to
 217 // their real location.
 218 //
 219 //===----------------------------------------------------------------------===//
 220
 221 void MipsRegisterInfo::adjustMipsStackFrame(MachineFunction &MF) const
 222 {
 223   MachineFrameInfo *MFI = MF.getFrameInfo();
 224   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 225   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 226   unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
 227
 228   // Min and Max CSI FrameIndex.
 229   int MinCSFI = -1, MaxCSFI = -1;
 230
 231   // See the description at MipsMachineFunction.h
 232   int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
 233
 234   // Replace the dummy '0' SPOffset by the negative offsets, as explained on
 235   // LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid
 236   // the approach done by calculateFrameObjectOffsets to the stack frame.
 237   MipsFI->adjustLoadArgsFI(MFI);
 238   MipsFI->adjustStoreVarArgsFI(MFI);
 239
 240   // It happens that the default stack frame allocation order does not directly
 241   // map to the convention used for mips. So we must fix it. We move the callee
 242   // save register slots after the local variables area, as described in the
 243   // stack frame above.
 244   unsigned CalleeSavedAreaSize = 0;
 245   if (!CSI.empty()) {
 246     MinCSFI = CSI[0].getFrameIdx();
 247     MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
 248   }
 249   for (unsigned i = 0, e = CSI.size(); i != e; ++i)
 250     CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
 251
 252   // Adjust local variables. They should come on the stack right
 253   // after the arguments.
 254   int LastOffsetFI = -1;
 255   for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
 256     if (i >= MinCSFI && i <= MaxCSFI)
 257       continue;
 258     if (MFI->isDeadObjectIndex(i))
 259       continue;
 260     unsigned Offset = MFI->getObjectOffset(i) - CalleeSavedAreaSize;
 261     if (LastOffsetFI == -1)
 262       LastOffsetFI = i;
 263     if (Offset > MFI->getObjectOffset(LastOffsetFI))
 264       LastOffsetFI = i;
 265     MFI->setObjectOffset(i, Offset);
 266   }
 267
 268   // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
 269   // be saved in this CPU Area there is the need. This whole Area must
 270   // be aligned to the default Stack Alignment requirements.
 271   unsigned StackOffset = 0;
 272   unsigned RegSize = Subtarget.isGP32bit() ? 4 : 8;
 273
 274   if (LastOffsetFI >= 0)
 275     StackOffset = MFI->getObjectOffset(LastOffsetFI)+
 276                   MFI->getObjectSize(LastOffsetFI);
 277   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
 278
 279   for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
 280     if (CSI[i].getRegClass() != Mips::CPURegsRegisterClass)
 281       break;
 282     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
 283     TopCPUSavedRegOff = StackOffset;
 284     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
 285   }
 286
 287   if (hasFP(MF)) {
 288     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
 289                          StackOffset);
 290     MipsFI->setFPStackOffset(StackOffset);
 291     TopCPUSavedRegOff = StackOffset;
 292     StackOffset += RegSize;
 293   }
 294
 295   if (MFI->hasCalls()) {
 296     MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize),
 297                          StackOffset);
 298     MipsFI->setRAStackOffset(StackOffset);
 299     TopCPUSavedRegOff = StackOffset;
 300     StackOffset += RegSize;
 301   }
 302   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
 303
 304   // Adjust FPU Callee Saved Registers Area. This Area must be
 305   // aligned to the default Stack Alignment requirements.
 306   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
 307     if (CSI[i].getRegClass() == Mips::CPURegsRegisterClass)
 308       continue;
 309     MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
 310     TopFPUSavedRegOff = StackOffset;
 311     StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
 312   }
 313   StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
 314
 315   // Update frame info
 316   MFI->setStackSize(StackOffset);
 317
 318   // Recalculate the final tops offset. The final values must be '0'
 319   // if there isn't a callee saved register for CPU or FPU, otherwise
 320   // a negative offset is needed.
 321   if (TopCPUSavedRegOff >= 0)
 322     MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
 323
 324   if (TopFPUSavedRegOff >= 0)
 325     MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
 326 }
 327
 328 // hasFP - Return true if the specified function should have a dedicated frame
 329 // pointer register.  This is true if the function has variable sized allocas or
 330 // if frame pointer elimination is disabled.
 331 bool MipsRegisterInfo::
 332 hasFP(const MachineFunction &MF) const {
 333   const MachineFrameInfo *MFI = MF.getFrameInfo();
 334   return NoFramePointerElim || MFI->hasVarSizedObjects();
 335 }
 336
 337 // This function eliminate ADJCALLSTACKDOWN,
 338 // ADJCALLSTACKUP pseudo instructions
 339 void MipsRegisterInfo::
 340 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 341                               MachineBasicBlock::iterator I) const {
 342   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
 343   MBB.erase(I);
 344 }
 345
 346 // FrameIndex represent objects inside a abstract stack.
 347 // We must replace FrameIndex with an stack/frame pointer
 348 // direct reference.
 349 void MipsRegisterInfo::
 350 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
 351                     RegScavenger *RS) const
 352 {
 353   MachineInstr &MI = *II;
 354   MachineFunction &MF = *MI.getParent()->getParent();
 355
 356   unsigned i = 0;
 357   while (!MI.getOperand(i).isFI()) {
 358     ++i;
 359     assert(i < MI.getNumOperands() &&
 360            "Instr doesn't have FrameIndex operand!");
 361   }
 362
 363   #ifndef NDEBUG
 364   DOUT << "\nFunction : " << MF.getFunction()->getName() << "\n";
 365   DOUT << "<--------->\n";
 366   MI.print(DOUT);
 367   #endif
 368
 369   int FrameIndex = MI.getOperand(i).getIndex();
 370   int stackSize  = MF.getFrameInfo()->getStackSize();
 371   int spOffset   = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 372
 373   #ifndef NDEBUG
 374   DOUT << "FrameIndex : " << FrameIndex << "\n";
 375   DOUT << "spOffset   : " << spOffset << "\n";
 376   DOUT << "stackSize  : " << stackSize << "\n";
 377   #endif
 378
 379   // as explained on LowerFORMAL_ARGUMENTS, detect negative offsets
 380   // and adjust SPOffsets considering the final stack size.
 381   int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
 382   Offset    += MI.getOperand(i-1).getImm();
 383
 384   #ifndef NDEBUG
 385   DOUT << "Offset     : " << Offset << "\n";
 386   DOUT << "<--------->\n";
 387   #endif
 388
 389   MI.getOperand(i-1).ChangeToImmediate(Offset);
 390   MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
 391 }
 392
 393 void MipsRegisterInfo::
 394 emitPrologue(MachineFunction &MF) const
 395 {
 396   MachineBasicBlock &MBB   = MF.front();
 397   MachineFrameInfo *MFI    = MF.getFrameInfo();
 398   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 399   MachineBasicBlock::iterator MBBI = MBB.begin();
 400   DebugLoc dl = (MBBI != MBB.end() ?
 401                  MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
 402   bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
 403
 404   // Get the right frame order for Mips.
 405   adjustMipsStackFrame(MF);
 406
 407   // Get the number of bytes to allocate from the FrameInfo.
 408   unsigned StackSize = MFI->getStackSize();
 409
 410   // No need to allocate space on the stack.
 411   if (StackSize == 0 && !MFI->hasCalls()) return;
 412
 413   int FPOffset = MipsFI->getFPStackOffset();
 414   int RAOffset = MipsFI->getRAStackOffset();
 415
 416   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
 417
 418   // TODO: check need from GP here.
 419   if (isPIC && Subtarget.isABI_O32())
 420     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)).addReg(getPICCallReg());
 421   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
 422
 423   // Adjust stack : addi sp, sp, (-imm)
 424   BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
 425       .addReg(Mips::SP).addImm(-StackSize);
 426
 427   // Save the return address only if the function isnt a leaf one.
 428   // sw  $ra, stack_loc($sp)
 429   if (MFI->hasCalls()) {
 430     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
 431         .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
 432   }
 433
 434   // if framepointer enabled, save it and set it
 435   // to point to the stack pointer
 436   if (hasFP(MF)) {
 437     // sw  $fp,stack_loc($sp)
 438     BuildMI(MBB, MBBI, dl, TII.get(Mips::SW))
 439       .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
 440
 441     // move $fp, $sp
 442     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP)
 443       .addReg(Mips::SP).addReg(Mips::ZERO);
 444   }
 445
 446   // PIC speficic function prologue
 447   if ((isPIC) && (MFI->hasCalls())) {
 448     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
 449       .addImm(MipsFI->getGPStackOffset());
 450   }
 451 }
 452
 453 void MipsRegisterInfo::
 454 emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
 455 {
 456   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 457   MachineFrameInfo *MFI            = MF.getFrameInfo();
 458   MipsFunctionInfo *MipsFI         = MF.getInfo<MipsFunctionInfo>();
 459   DebugLoc dl = MBBI->getDebugLoc();
 460
 461   // Get the number of bytes from FrameInfo
 462   int NumBytes = (int) MFI->getStackSize();
 463
 464   // Get the FI's where RA and FP are saved.
 465   int FPOffset = MipsFI->getFPStackOffset();
 466   int RAOffset = MipsFI->getRAStackOffset();
 467
 468   // if framepointer enabled, restore it and restore the
 469   // stack pointer
 470   if (hasFP(MF)) {
 471     // move $sp, $fp
 472     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP)
 473       .addReg(Mips::FP).addReg(Mips::ZERO);
 474
 475     // lw  $fp,stack_loc($sp)
 476     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
 477       .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP);
 478   }
 479
 480   // Restore the return address only if the function isnt a leaf one.
 481   // lw  $ra, stack_loc($sp)
 482   if (MFI->hasCalls()) {
 483     BuildMI(MBB, MBBI, dl, TII.get(Mips::LW))
 484       .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP);
 485   }
 486
 487   // adjust stack  : insert addi sp, sp, (imm)
 488   if (NumBytes) {
 489     BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
 490       .addReg(Mips::SP).addImm(NumBytes);
 491   }
 492 }
 493
 494
 495 void MipsRegisterInfo::
 496 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
 497   // Set the SPOffset on the FI where GP must be saved/loaded.
 498   MachineFrameInfo *MFI = MF.getFrameInfo();
 499   bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_);
 500   if (MFI->hasCalls() && isPIC) {
 501     MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
 502     MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
 503   }
 504 }
 505
 506 unsigned MipsRegisterInfo::
 507 getRARegister() const {
 508   return Mips::RA;
 509 }
 510
 511 unsigned MipsRegisterInfo::
 512 getFrameRegister(MachineFunction &MF) const {
 513   return hasFP(MF) ? Mips::FP : Mips::SP;
 514 }
 515
 516 unsigned MipsRegisterInfo::
 517 getEHExceptionRegister() const {
 518   assert(0 && "What is the exception register");
 519   return 0;
 520 }
 521
 522 unsigned MipsRegisterInfo::
 523 getEHHandlerRegister() const {
 524   assert(0 && "What is the exception handler register");
 525   return 0;
 526 }
 527
 528 int MipsRegisterInfo::
 529 getDwarfRegNum(unsigned RegNum, bool isEH) const {
 530   assert(0 && "What is the dwarf register number");
 531   return -1;
 532 }
 533
 534 #include "MipsGenRegisterInfo.inc"
 535