lib/Target/Sparc/SparcRegisterInfo.cpp

   1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Sparc.h"
  15 #include "SparcRegisterInfo.h"
  16 #include "SparcSubtarget.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineLocation.h"
  21 #include "llvm/Target/TargetInstrInfo.h"
  22 #include "llvm/Type.h"
  23 #include "llvm/ADT/BitVector.h"
  24 #include "llvm/ADT/STLExtras.h"
  25 using namespace llvm;
  26
  27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
  28                                      const TargetInstrInfo &tii)
  29   : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
  30     Subtarget(st), TII(tii) {
  31 }
  32
  33 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
  34                                                                          const {
  35   static const unsigned CalleeSavedRegs[] = { 0 };
  36   return CalleeSavedRegs;
  37 }
  38
  39 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  40   BitVector Reserved(getNumRegs());
  41   Reserved.set(SP::G2);
  42   Reserved.set(SP::G3);
  43   Reserved.set(SP::G4);
  44   Reserved.set(SP::O6);
  45   Reserved.set(SP::I6);
  46   Reserved.set(SP::I7);
  47   Reserved.set(SP::G0);
  48   Reserved.set(SP::G5);
  49   Reserved.set(SP::G6);
  50   Reserved.set(SP::G7);
  51   return Reserved;
  52 }
  53
  54
  55 const TargetRegisterClass* const*
  56 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
  57   static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
  58   return CalleeSavedRegClasses;
  59 }
  60
  61 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
  62   return false;
  63 }
  64
  65 void SparcRegisterInfo::
  66 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
  67                               MachineBasicBlock::iterator I) const {
  68   MachineInstr &MI = *I;
  69   DebugLoc dl = MI.getDebugLoc();
  70   int Size = MI.getOperand(0).getImm();
  71   if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
  72     Size = -Size;
  73   if (Size)
  74     BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
  75   MBB.erase(I);
  76 }
  77
  78 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
  79                                             int SPAdj, RegScavenger *RS) const {
  80   assert(SPAdj == 0 && "Unexpected");
  81
  82   unsigned i = 0;
  83   MachineInstr &MI = *II;
  84   DebugLoc dl = MI.getDebugLoc();
  85   while (!MI.getOperand(i).isFI()) {
  86     ++i;
  87     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
  88   }
  89
  90   int FrameIndex = MI.getOperand(i).getIndex();
  91
  92   // Addressable stack objects are accessed using neg. offsets from %fp
  93   MachineFunction &MF = *MI.getParent()->getParent();
  94   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
  95                MI.getOperand(i+1).getImm();
  96
  97   // Replace frame index with a frame pointer reference.
  98   if (Offset >= -4096 && Offset <= 4095) {
  99     // If the offset is small enough to fit in the immediate field, directly
 100     // encode it.
 101     MI.getOperand(i).ChangeToRegister(SP::I6, false);
 102     MI.getOperand(i+1).ChangeToImmediate(Offset);
 103   } else {
 104     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
 105     // scavenge a register here instead of reserving G1 all of the time.
 106     unsigned OffHi = (unsigned)Offset >> 10U;
 107     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
 108     // Emit G1 = G1 + I6
 109     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
 110       .addReg(SP::I6);
 111     // Insert: G1+%lo(offset) into the user.
 112     MI.getOperand(i).ChangeToRegister(SP::G1, false);
 113     MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
 114   }
 115 }
 116
 117 void SparcRegisterInfo::
 118 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
 119
 120 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
 121   MachineBasicBlock &MBB = MF.front();
 122   MachineFrameInfo *MFI = MF.getFrameInfo();
 123   MachineBasicBlock::iterator MBBI = MBB.begin();
 124   DebugLoc dl = (MBBI != MBB.end() ?
 125                  MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
 126
 127   // Get the number of bytes to allocate from the FrameInfo
 128   int NumBytes = (int) MFI->getStackSize();
 129
 130   // Emit the correct save instruction based on the number of bytes in
 131   // the frame. Minimum stack frame size according to V8 ABI is:
 132   //   16 words for register window spill
 133   //    1 word for address of returned aggregate-value
 134   // +  6 words for passing parameters on the stack
 135   // ----------
 136   //   23 words * 4 bytes per word = 92 bytes
 137   NumBytes += 92;
 138
 139   // Round up to next doubleword boundary -- a double-word boundary
 140   // is required by the ABI.
 141   NumBytes = (NumBytes + 7) & ~7;
 142   NumBytes = -NumBytes;
 143
 144   if (NumBytes >= -4096) {
 145     BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
 146       .addReg(SP::O6).addImm(NumBytes);
 147   } else {
 148     // Emit this the hard way.  This clobbers G1 which we always know is
 149     // available here.
 150     unsigned OffHi = (unsigned)NumBytes >> 10U;
 151     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
 152     // Emit G1 = G1 + I6
 153     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
 154       .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
 155     BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
 156       .addReg(SP::O6).addReg(SP::G1);
 157   }
 158 }
 159
 160 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
 161                                      MachineBasicBlock &MBB) const {
 162   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 163   DebugLoc dl = MBBI->getDebugLoc();
 164   assert(MBBI->getOpcode() == SP::RETL &&
 165          "Can only put epilog before 'retl' instruction!");
 166   BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
 167     .addReg(SP::G0);
 168 }
 169
 170 unsigned SparcRegisterInfo::getRARegister() const {
 171   assert(0 && "What is the return address register");
 172   return 0;
 173 }
 174
 175 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
 176   assert(0 && "What is the frame register");
 177   return SP::G1;
 178 }
 179
 180 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
 181   assert(0 && "What is the exception register");
 182   return 0;
 183 }
 184
 185 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
 186   assert(0 && "What is the exception handler register");
 187   return 0;
 188 }
 189
 190 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
 191   assert(0 && "What is the dwarf register number");
 192   return -1;
 193 }
 194
 195 #include "SparcGenRegisterInfo.inc"
 196