lib/Target/TargetRegisterInfo.cpp

   1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the TargetRegisterInfo interface.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/Target/TargetRegisterInfo.h"
  16 #include "llvm/Target/TargetFrameInfo.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/ADT/BitVector.h"
  20
  21 using namespace llvm;
  22
  23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
  24                              regclass_iterator RCB, regclass_iterator RCE,
  25                              int CFSO, int CFDO,
  26                              const unsigned* subregs, const unsigned subregsize,
  27                          const unsigned* superregs, const unsigned superregsize,
  28                          const unsigned* aliases, const unsigned aliasessize)
  29   : SubregHash(subregs), SubregHashSize(subregsize),
  30     SuperregHash(superregs), SuperregHashSize(superregsize),
  31     AliasesHash(aliases), AliasesHashSize(aliasessize),
  32     Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
  33   assert(NumRegs < FirstVirtualRegister &&
  34          "Target has too many physical registers!");
  35
  36   CallFrameSetupOpcode   = CFSO;
  37   CallFrameDestroyOpcode = CFDO;
  38 }
  39
  40 TargetRegisterInfo::~TargetRegisterInfo() {}
  41
  42 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
  43 /// register of the given type. If type is MVT::Other, then just return any
  44 /// register class the register belongs to.
  45 const TargetRegisterClass *
  46 TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const {
  47   assert(isPhysicalRegister(reg) && "reg must be a physical register");
  48
  49   // Pick the most super register class of the right type that contains
  50   // this physreg.
  51   const TargetRegisterClass* BestRC = 0;
  52   for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
  53     const TargetRegisterClass* RC = *I;
  54     if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
  55         (!BestRC || BestRC->hasSuperClass(RC)))
  56       BestRC = RC;
  57   }
  58
  59   assert(BestRC && "Couldn't find the register class");
  60   return BestRC;
  61 }
  62
  63 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
  64 /// registers for the specific register class.
  65 static void getAllocatableSetForRC(MachineFunction &MF,
  66                                    const TargetRegisterClass *RC, BitVector &R){
  67   for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
  68          E = RC->allocation_order_end(MF); I != E; ++I)
  69     R.set(*I);
  70 }
  71
  72 BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF,
  73                                           const TargetRegisterClass *RC) const {
  74   BitVector Allocatable(NumRegs);
  75   if (RC) {
  76     getAllocatableSetForRC(MF, RC, Allocatable);
  77     return Allocatable;
  78   }
  79
  80   for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
  81          E = regclass_end(); I != E; ++I)
  82     getAllocatableSetForRC(MF, *I, Allocatable);
  83   return Allocatable;
  84 }
  85
  86 /// getFrameIndexOffset - Returns the displacement from the frame register to
  87 /// the stack frame of the specified index. This is the default implementation
  88 /// which is likely incorrect for the target.
  89 int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
  90   const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
  91   MachineFrameInfo *MFI = MF.getFrameInfo();
  92   return MFI->getObjectOffset(FI) + MFI->getStackSize() -
  93     TFI.getOffsetOfLocalArea() + MFI->getOffsetAdjustment();
  94 }
  95
  96 /// getInitialFrameState - Returns a list of machine moves that are assumed
  97 /// on entry to a function.
  98 void
  99 TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
 100   // Default is to do nothing.
 101 }
 102
 103 const TargetRegisterClass *
 104 llvm::getCommonSubClass(const TargetRegisterClass *A,
 105                         const TargetRegisterClass *B) {
 106   // First take care of the trivial cases
 107   if (A == B)
 108     return A;
 109   if (!A || !B)
 110     return 0;
 111
 112   // If B is a subclass of A, it will be handled in the loop below
 113   if (B->hasSubClass(A))
 114     return A;
 115
 116   const TargetRegisterClass *Best = 0;
 117   for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
 118        const TargetRegisterClass *X = *I; ++I) {
 119     if (X == B)
 120       return B;                 // B is a subclass of A
 121
 122     // X must be a common subclass of A and B
 123     if (!B->hasSubClass(X))
 124       continue;
 125
 126     // A superclass is definitely better.
 127     if (!Best || Best->hasSuperClass(X)) {
 128       Best = X;
 129       continue;
 130     }
 131
 132     // A subclass is definitely worse
 133     if (Best->hasSubClass(X))
 134       continue;
 135
 136     // Best and *I have no super/sub class relation - pick the larger class, or
 137     // the smaller spill size.
 138     int nb = std::distance(Best->begin(), Best->end());
 139     int ni = std::distance(X->begin(), X->end());
 140     if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))
 141       Best = X;
 142   }
 143   return Best;
 144 }