lib/Target/X86/X86RegisterInfo.cpp

   1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the X86 implementation of the TargetRegisterInfo class.
  11 // This file is responsible for the frame pointer elimination optimization
  12 // on X86.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "X86.h"
  17 #include "X86RegisterInfo.h"
  18 #include "X86InstrBuilder.h"
  19 #include "X86MachineFunctionInfo.h"
  20 #include "X86Subtarget.h"
  21 #include "X86TargetMachine.h"
  22 #include "llvm/Constants.h"
  23 #include "llvm/Function.h"
  24 #include "llvm/Type.h"
  25 #include "llvm/CodeGen/ValueTypes.h"
  26 #include "llvm/CodeGen/MachineInstrBuilder.h"
  27 #include "llvm/CodeGen/MachineFunction.h"
  28 #include "llvm/CodeGen/MachineFunctionPass.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/CodeGen/MachineLocation.h"
  31 #include "llvm/CodeGen/MachineModuleInfo.h"
  32 #include "llvm/CodeGen/MachineRegisterInfo.h"
  33 #include "llvm/Target/TargetAsmInfo.h"
  34 #include "llvm/Target/TargetFrameInfo.h"
  35 #include "llvm/Target/TargetInstrInfo.h"
  36 #include "llvm/Target/TargetMachine.h"
  37 #include "llvm/Target/TargetOptions.h"
  38 #include "llvm/ADT/BitVector.h"
  39 #include "llvm/ADT/STLExtras.h"
  40 #include "llvm/Support/Compiler.h"
  41 using namespace llvm;
  42
  43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
  44                                  const TargetInstrInfo &tii)
  45   : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
  46                          X86::ADJCALLSTACKDOWN64 :
  47                          X86::ADJCALLSTACKDOWN32,
  48                        tm.getSubtarget<X86Subtarget>().is64Bit() ?
  49                          X86::ADJCALLSTACKUP64 :
  50                          X86::ADJCALLSTACKUP32),
  51     TM(tm), TII(tii) {
  52   // Cache some information.
  53   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
  54   Is64Bit = Subtarget->is64Bit();
  55   IsWin64 = Subtarget->isTargetWin64();
  56   StackAlign = TM.getFrameInfo()->getStackAlignment();
  57   if (Is64Bit) {
  58     SlotSize = 8;
  59     StackPtr = X86::RSP;
  60     FramePtr = X86::RBP;
  61   } else {
  62     SlotSize = 4;
  63     StackPtr = X86::ESP;
  64     FramePtr = X86::EBP;
  65   }
  66 }
  67
  68 // getDwarfRegNum - This function maps LLVM register identifiers to the
  69 // Dwarf specific numbering, used in debug info and exception tables.
  70
  71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
  72   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
  73   unsigned Flavour = DWARFFlavour::X86_64;
  74   if (!Subtarget->is64Bit()) {
  75     if (Subtarget->isTargetDarwin()) {
  76       if (isEH)
  77         Flavour = DWARFFlavour::X86_32_DarwinEH;
  78       else
  79         Flavour = DWARFFlavour::X86_32_Generic;
  80     } else if (Subtarget->isTargetCygMing()) {
  81       // Unsupported by now, just quick fallback
  82       Flavour = DWARFFlavour::X86_32_Generic;
  83     } else {
  84       Flavour = DWARFFlavour::X86_32_Generic;
  85     }
  86   }
  87
  88   return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
  89 }
  90
  91 // getX86RegNum - This function maps LLVM register identifiers to their X86
  92 // specific numbering, which is used in various places encoding instructions.
  93 //
  94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
  95   switch(RegNo) {
  96   case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
  97   case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
  98   case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
  99   case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
 100   case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
 101     return N86::ESP;
 102   case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
 103     return N86::EBP;
 104   case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
 105     return N86::ESI;
 106   case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
 107     return N86::EDI;
 108
 109   case X86::R8:  case X86::R8D:  case X86::R8W:  case X86::R8B:
 110     return N86::EAX;
 111   case X86::R9:  case X86::R9D:  case X86::R9W:  case X86::R9B:
 112     return N86::ECX;
 113   case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
 114     return N86::EDX;
 115   case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
 116     return N86::EBX;
 117   case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
 118     return N86::ESP;
 119   case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
 120     return N86::EBP;
 121   case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
 122     return N86::ESI;
 123   case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
 124     return N86::EDI;
 125
 126   case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
 127   case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
 128     return RegNo-X86::ST0;
 129
 130   case X86::XMM0: case X86::XMM8: case X86::MM0:
 131     return 0;
 132   case X86::XMM1: case X86::XMM9: case X86::MM1:
 133     return 1;
 134   case X86::XMM2: case X86::XMM10: case X86::MM2:
 135     return 2;
 136   case X86::XMM3: case X86::XMM11: case X86::MM3:
 137     return 3;
 138   case X86::XMM4: case X86::XMM12: case X86::MM4:
 139     return 4;
 140   case X86::XMM5: case X86::XMM13: case X86::MM5:
 141     return 5;
 142   case X86::XMM6: case X86::XMM14: case X86::MM6:
 143     return 6;
 144   case X86::XMM7: case X86::XMM15: case X86::MM7:
 145     return 7;
 146
 147   default:
 148     assert(isVirtualRegister(RegNo) && "Unknown physical register!");
 149     assert(0 && "Register allocator hasn't allocated reg correctly yet!");
 150     return 0;
 151   }
 152 }
 153
 154 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
 155   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
 156   if (Subtarget->is64Bit())
 157     return &X86::GR64RegClass;
 158   else
 159     return &X86::GR32RegClass;
 160 }
 161
 162 const TargetRegisterClass *
 163 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
 164   if (RC == &X86::CCRRegClass) {
 165     if (Is64Bit)
 166       return &X86::GR64RegClass;
 167     else
 168       return &X86::GR32RegClass;
 169   }
 170   return NULL;
 171 }
 172
 173 const unsigned *
 174 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
 175   bool callsEHReturn = false;
 176
 177   if (MF) {
 178     const MachineFrameInfo *MFI = MF->getFrameInfo();
 179     const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 180     callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
 181   }
 182
 183   static const unsigned CalleeSavedRegs32Bit[] = {
 184     X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
 185   };
 186
 187   static const unsigned CalleeSavedRegs32EHRet[] = {
 188     X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,  0
 189   };
 190
 191   static const unsigned CalleeSavedRegs64Bit[] = {
 192     X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
 193   };
 194
 195   static const unsigned CalleeSavedRegs64EHRet[] = {
 196     X86::RAX, X86::RDX, X86::RBX, X86::R12,
 197     X86::R13, X86::R14, X86::R15, X86::RBP, 0
 198   };
 199
 200   static const unsigned CalleeSavedRegsWin64[] = {
 201     X86::RBX,   X86::RBP,   X86::RDI,   X86::RSI,
 202     X86::R12,   X86::R13,   X86::R14,   X86::R15,
 203     X86::XMM6,  X86::XMM7,  X86::XMM8,  X86::XMM9,
 204     X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
 205     X86::XMM14, X86::XMM15, 0
 206   };
 207
 208   if (Is64Bit) {
 209     if (IsWin64)
 210       return CalleeSavedRegsWin64;
 211     else
 212       return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
 213   } else {
 214     return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
 215   }
 216 }
 217
 218 const TargetRegisterClass* const*
 219 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
 220   bool callsEHReturn = false;
 221
 222   if (MF) {
 223     const MachineFrameInfo *MFI = MF->getFrameInfo();
 224     const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 225     callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
 226   }
 227
 228   static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
 229     &X86::GR32RegClass, &X86::GR32RegClass,
 230     &X86::GR32RegClass, &X86::GR32RegClass,  0
 231   };
 232   static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
 233     &X86::GR32RegClass, &X86::GR32RegClass,
 234     &X86::GR32RegClass, &X86::GR32RegClass,
 235     &X86::GR32RegClass, &X86::GR32RegClass,  0
 236   };
 237   static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
 238     &X86::GR64RegClass, &X86::GR64RegClass,
 239     &X86::GR64RegClass, &X86::GR64RegClass,
 240     &X86::GR64RegClass, &X86::GR64RegClass, 0
 241   };
 242   static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
 243     &X86::GR64RegClass, &X86::GR64RegClass,
 244     &X86::GR64RegClass, &X86::GR64RegClass,
 245     &X86::GR64RegClass, &X86::GR64RegClass,
 246     &X86::GR64RegClass, &X86::GR64RegClass, 0
 247   };
 248   static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
 249     &X86::GR64RegClass,  &X86::GR64RegClass,
 250     &X86::GR64RegClass,  &X86::GR64RegClass,
 251     &X86::GR64RegClass,  &X86::GR64RegClass,
 252     &X86::GR64RegClass,  &X86::GR64RegClass,
 253     &X86::VR128RegClass, &X86::VR128RegClass,
 254     &X86::VR128RegClass, &X86::VR128RegClass,
 255     &X86::VR128RegClass, &X86::VR128RegClass,
 256     &X86::VR128RegClass, &X86::VR128RegClass,
 257     &X86::VR128RegClass, &X86::VR128RegClass, 0
 258   };
 259
 260   if (Is64Bit) {
 261     if (IsWin64)
 262       return CalleeSavedRegClassesWin64;
 263     else
 264       return (callsEHReturn ?
 265               CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
 266   } else {
 267     return (callsEHReturn ?
 268             CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
 269   }
 270 }
 271
 272 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 273   BitVector Reserved(getNumRegs());
 274   // Set the stack-pointer register and its aliases as reserved.
 275   Reserved.set(X86::RSP);
 276   Reserved.set(X86::ESP);
 277   Reserved.set(X86::SP);
 278   Reserved.set(X86::SPL);
 279   // Set the frame-pointer register and its aliases as reserved if needed.
 280   if (hasFP(MF)) {
 281     Reserved.set(X86::RBP);
 282     Reserved.set(X86::EBP);
 283     Reserved.set(X86::BP);
 284     Reserved.set(X86::BPL);
 285   }
 286   // Mark the x87 stack registers as reserved, since they don't
 287   // behave normally with respect to liveness. We don't fully
 288   // model the effects of x87 stack pushes and pops after
 289   // stackification.
 290   Reserved.set(X86::ST0);
 291   Reserved.set(X86::ST1);
 292   Reserved.set(X86::ST2);
 293   Reserved.set(X86::ST3);
 294   Reserved.set(X86::ST4);
 295   Reserved.set(X86::ST5);
 296   Reserved.set(X86::ST6);
 297   Reserved.set(X86::ST7);
 298   return Reserved;
 299 }
 300
 301 //===----------------------------------------------------------------------===//
 302 // Stack Frame Processing methods
 303 //===----------------------------------------------------------------------===//
 304
 305 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
 306   unsigned MaxAlign = 0;
 307   for (int i = FFI->getObjectIndexBegin(),
 308          e = FFI->getObjectIndexEnd(); i != e; ++i) {
 309     if (FFI->isDeadObjectIndex(i))
 310       continue;
 311     unsigned Align = FFI->getObjectAlignment(i);
 312     MaxAlign = std::max(MaxAlign, Align);
 313   }
 314
 315   return MaxAlign;
 316 }
 317
 318 // hasFP - Return true if the specified function should have a dedicated frame
 319 // pointer register.  This is true if the function has variable sized allocas or
 320 // if frame pointer elimination is disabled.
 321 //
 322 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
 323   const MachineFrameInfo *MFI = MF.getFrameInfo();
 324   const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 325
 326   return (NoFramePointerElim ||
 327           needsStackRealignment(MF) ||
 328           MFI->hasVarSizedObjects() ||
 329           MFI->isFrameAddressTaken() ||
 330           MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
 331           (MMI && MMI->callsUnwindInit()));
 332 }
 333
 334 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
 335   const MachineFrameInfo *MFI = MF.getFrameInfo();;
 336
 337   // FIXME: Currently we don't support stack realignment for functions with
 338   // variable-sized allocas
 339   return (RealignStack &&
 340           (MFI->getMaxAlignment() > StackAlign &&
 341            !MFI->hasVarSizedObjects()));
 342 }
 343
 344 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
 345   return !MF.getFrameInfo()->hasVarSizedObjects();
 346 }
 347
 348 int
 349 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
 350   int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
 351   uint64_t StackSize = MF.getFrameInfo()->getStackSize();
 352
 353   if (needsStackRealignment(MF)) {
 354     if (FI < 0)
 355       // Skip the saved EBP
 356       Offset += SlotSize;
 357     else {
 358       unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
 359       assert( (-(Offset + StackSize)) % Align == 0);
 360       Align = 0;
 361       return Offset + StackSize;
 362     }
 363
 364     // FIXME: Support tail calls
 365   } else {
 366     if (!hasFP(MF))
 367       return Offset + StackSize;
 368
 369     // Skip the saved EBP
 370     Offset += SlotSize;
 371
 372     // Skip the RETADDR move area
 373     X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 374     int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
 375     if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
 376   }
 377
 378   return Offset;
 379 }
 380
 381 void X86RegisterInfo::
 382 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
 383                               MachineBasicBlock::iterator I) const {
 384   if (!hasReservedCallFrame(MF)) {
 385     // If the stack pointer can be changed after prologue, turn the
 386     // adjcallstackup instruction into a 'sub ESP, <amt>' and the
 387     // adjcallstackdown instruction into 'add ESP, <amt>'
 388     // TODO: consider using push / pop instead of sub + store / add
 389     MachineInstr *Old = I;
 390     uint64_t Amount = Old->getOperand(0).getImm();
 391     if (Amount != 0) {
 392       // We need to keep the stack aligned properly.  To do this, we round the
 393       // amount of space needed for the outgoing arguments up to the next
 394       // alignment boundary.
 395       Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
 396
 397       MachineInstr *New = 0;
 398       if (Old->getOpcode() == getCallFrameSetupOpcode()) {
 399         New = BuildMI(MF, Old->getDebugLoc(),
 400                       TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
 401                       StackPtr).addReg(StackPtr).addImm(Amount);
 402       } else {
 403         assert(Old->getOpcode() == getCallFrameDestroyOpcode());
 404         // factor out the amount the callee already popped.
 405         uint64_t CalleeAmt = Old->getOperand(1).getImm();
 406         Amount -= CalleeAmt;
 407         if (Amount) {
 408           unsigned Opc = (Amount < 128) ?
 409             (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
 410             (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
 411           New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
 412             .addReg(StackPtr).addImm(Amount);
 413         }
 414       }
 415
 416       if (New) {
 417         // The EFLAGS implicit def is dead.
 418         New->getOperand(3).setIsDead();
 419
 420         // Replace the pseudo instruction with a new instruction...
 421         MBB.insert(I, New);
 422       }
 423     }
 424   } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
 425     // If we are performing frame pointer elimination and if the callee pops
 426     // something off the stack pointer, add it back.  We do this until we have
 427     // more advanced stack pointer tracking ability.
 428     if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
 429       unsigned Opc = (CalleeAmt < 128) ?
 430         (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
 431         (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
 432       MachineInstr *Old = I;
 433       MachineInstr *New =
 434         BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
 435                 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
 436       // The EFLAGS implicit def is dead.
 437       New->getOperand(3).setIsDead();
 438
 439       MBB.insert(I, New);
 440     }
 441   }
 442
 443   MBB.erase(I);
 444 }
 445
 446 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 447                                           int SPAdj, RegScavenger *RS) const{
 448   assert(SPAdj == 0 && "Unexpected");
 449
 450   unsigned i = 0;
 451   MachineInstr &MI = *II;
 452   MachineFunction &MF = *MI.getParent()->getParent();
 453   while (!MI.getOperand(i).isFI()) {
 454     ++i;
 455     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
 456   }
 457
 458   int FrameIndex = MI.getOperand(i).getIndex();
 459
 460   unsigned BasePtr;
 461   if (needsStackRealignment(MF))
 462     BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
 463   else
 464     BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
 465
 466   // This must be part of a four operand memory reference.  Replace the
 467   // FrameIndex with base register with EBP.  Add an offset to the offset.
 468   MI.getOperand(i).ChangeToRegister(BasePtr, false);
 469
 470   // Now add the frame object offset to the offset from EBP.
 471   if (MI.getOperand(i+3).isImm()) {
 472     // Offset is a 32-bit integer.
 473     int Offset = getFrameIndexOffset(MF, FrameIndex) +
 474       (int)(MI.getOperand(i+3).getImm());
 475
 476      MI.getOperand(i+3).ChangeToImmediate(Offset);
 477   } else {
 478     // Offset is symbolic. This is extremely rare.
 479     uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
 480                       (uint64_t)MI.getOperand(i+3).getOffset();
 481     MI.getOperand(i+3).setOffset(Offset);
 482   }
 483 }
 484
 485 void
 486 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
 487                                                       RegScavenger *RS) const {
 488   MachineFrameInfo *FFI = MF.getFrameInfo();
 489
 490   // Calculate and set max stack object alignment early, so we can decide
 491   // whether we will need stack realignment (and thus FP).
 492   unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
 493                                calculateMaxStackAlignment(FFI));
 494
 495   FFI->setMaxAlignment(MaxAlign);
 496 }
 497
 498 void
 499 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
 500   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 501   int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
 502   if (TailCallReturnAddrDelta < 0) {
 503     // create RETURNADDR area
 504     //   arg
 505     //   arg
 506     //   RETADDR
 507     //   { ...
 508     //     RETADDR area
 509     //     ...
 510     //   }
 511     //   [EBP]
 512     MF.getFrameInfo()->
 513       CreateFixedObject(-TailCallReturnAddrDelta,
 514                         (-1*SlotSize)+TailCallReturnAddrDelta);
 515   }
 516   if (hasFP(MF)) {
 517     assert((TailCallReturnAddrDelta <= 0) &&
 518            "The Delta should always be zero or negative");
 519     // Create a frame entry for the EBP register that must be saved.
 520     int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
 521                                                         (int)SlotSize * -2+
 522                                                        TailCallReturnAddrDelta);
 523     assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
 524            "Slot for EBP register must be last in order to be found!");
 525     FrameIdx = 0;
 526   }
 527 }
 528
 529 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
 530 /// stack pointer by a constant value.
 531 static
 532 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
 533                   unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
 534                   const TargetInstrInfo &TII) {
 535   bool isSub = NumBytes < 0;
 536   uint64_t Offset = isSub ? -NumBytes : NumBytes;
 537   unsigned Opc = isSub
 538     ? ((Offset < 128) ?
 539        (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
 540        (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
 541     : ((Offset < 128) ?
 542        (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
 543        (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
 544   uint64_t Chunk = (1LL << 31) - 1;
 545   DebugLoc DL = MBBI->getDebugLoc();
 546
 547   while (Offset) {
 548     uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
 549     MachineInstr *MI =
 550       BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
 551          .addReg(StackPtr).addImm(ThisVal);
 552     // The EFLAGS implicit def is dead.
 553     MI->getOperand(3).setIsDead();
 554     Offset -= ThisVal;
 555   }
 556 }
 557
 558 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
 559 static
 560 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
 561                       unsigned StackPtr, uint64_t *NumBytes = NULL) {
 562   if (MBBI == MBB.begin()) return;
 563
 564   MachineBasicBlock::iterator PI = prior(MBBI);
 565   unsigned Opc = PI->getOpcode();
 566   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
 567        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
 568       PI->getOperand(0).getReg() == StackPtr) {
 569     if (NumBytes)
 570       *NumBytes += PI->getOperand(2).getImm();
 571     MBB.erase(PI);
 572   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
 573               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
 574              PI->getOperand(0).getReg() == StackPtr) {
 575     if (NumBytes)
 576       *NumBytes -= PI->getOperand(2).getImm();
 577     MBB.erase(PI);
 578   }
 579 }
 580
 581 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
 582 static
 583 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
 584                         MachineBasicBlock::iterator &MBBI,
 585                         unsigned StackPtr, uint64_t *NumBytes = NULL) {
 586   return;
 587
 588   if (MBBI == MBB.end()) return;
 589
 590   MachineBasicBlock::iterator NI = next(MBBI);
 591   if (NI == MBB.end()) return;
 592
 593   unsigned Opc = NI->getOpcode();
 594   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
 595        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
 596       NI->getOperand(0).getReg() == StackPtr) {
 597     if (NumBytes)
 598       *NumBytes -= NI->getOperand(2).getImm();
 599     MBB.erase(NI);
 600     MBBI = NI;
 601   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
 602               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
 603              NI->getOperand(0).getReg() == StackPtr) {
 604     if (NumBytes)
 605       *NumBytes += NI->getOperand(2).getImm();
 606     MBB.erase(NI);
 607     MBBI = NI;
 608   }
 609 }
 610
 611 /// mergeSPUpdates - Checks the instruction before/after the passed
 612 /// instruction. If it is an ADD/SUB instruction it is deleted
 613 /// argument and the stack adjustment is returned as a positive value for ADD
 614 /// and a negative for SUB.
 615 static int mergeSPUpdates(MachineBasicBlock &MBB,
 616                            MachineBasicBlock::iterator &MBBI,
 617                            unsigned StackPtr,
 618                            bool doMergeWithPrevious) {
 619
 620   if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
 621       (!doMergeWithPrevious && MBBI == MBB.end()))
 622     return 0;
 623
 624   int Offset = 0;
 625
 626   MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
 627   MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
 628   unsigned Opc = PI->getOpcode();
 629   if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
 630        Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
 631       PI->getOperand(0).getReg() == StackPtr){
 632     Offset += PI->getOperand(2).getImm();
 633     MBB.erase(PI);
 634     if (!doMergeWithPrevious) MBBI = NI;
 635   } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
 636               Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
 637              PI->getOperand(0).getReg() == StackPtr) {
 638     Offset -= PI->getOperand(2).getImm();
 639     MBB.erase(PI);
 640     if (!doMergeWithPrevious) MBBI = NI;
 641   }
 642
 643   return Offset;
 644 }
 645
 646 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
 647                                      unsigned FrameLabelId,
 648                                      unsigned ReadyLabelId) const {
 649   MachineFrameInfo *MFI = MF.getFrameInfo();
 650   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 651   if (!MMI)
 652     return;
 653
 654   uint64_t StackSize = MFI->getStackSize();
 655   std::vector<MachineMove> &Moves = MMI->getFrameMoves();
 656   const TargetData *TD = MF.getTarget().getTargetData();
 657
 658   // Calculate amount of bytes used for return address storing
 659   int stackGrowth =
 660     (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
 661      TargetFrameInfo::StackGrowsUp ?
 662      TD->getPointerSize() : -TD->getPointerSize());
 663
 664   if (StackSize) {
 665     // Show update of SP.
 666     if (hasFP(MF)) {
 667       // Adjust SP
 668       MachineLocation SPDst(MachineLocation::VirtualFP);
 669       MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
 670       Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
 671     } else {
 672       MachineLocation SPDst(MachineLocation::VirtualFP);
 673       MachineLocation SPSrc(MachineLocation::VirtualFP,
 674                             -StackSize+stackGrowth);
 675       Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
 676     }
 677   } else {
 678     //FIXME: Verify & implement for FP
 679     MachineLocation SPDst(StackPtr);
 680     MachineLocation SPSrc(StackPtr, stackGrowth);
 681     Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
 682   }
 683
 684   // Add callee saved registers to move list.
 685   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
 686
 687   // FIXME: This is dirty hack. The code itself is pretty mess right now.
 688   // It should be rewritten from scratch and generalized sometimes.
 689
 690   // Determine maximum offset (minumum due to stack growth)
 691   int64_t MaxOffset = 0;
 692   for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
 693     MaxOffset = std::min(MaxOffset,
 694                          MFI->getObjectOffset(CSI[I].getFrameIdx()));
 695
 696   // Calculate offsets
 697   int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
 698   for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
 699     int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
 700     unsigned Reg = CSI[I].getReg();
 701     Offset = (MaxOffset-Offset+saveAreaOffset);
 702     MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
 703     MachineLocation CSSrc(Reg);
 704     Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
 705   }
 706
 707   if (hasFP(MF)) {
 708     // Save FP
 709     MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
 710     MachineLocation FPSrc(FramePtr);
 711     Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
 712   }
 713
 714   MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
 715   MachineLocation FPSrc(MachineLocation::VirtualFP);
 716   Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
 717 }
 718
 719
 720 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
 721   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
 722   MachineFrameInfo *MFI = MF.getFrameInfo();
 723   const Function* Fn = MF.getFunction();
 724   const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
 725   MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
 726   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 727   MachineBasicBlock::iterator MBBI = MBB.begin();
 728   bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
 729                           !Fn->doesNotThrow() ||
 730                           UnwindTablesMandatory;
 731   DebugLoc DL = DebugLoc::getUnknownLoc();
 732   // Prepare for frame info.
 733   unsigned FrameLabelId = 0;
 734
 735   // Get the number of bytes to allocate from the FrameInfo.
 736   uint64_t StackSize = MFI->getStackSize();
 737   // Get desired stack alignment
 738   uint64_t MaxAlign  = MFI->getMaxAlignment();
 739
 740   // Add RETADDR move area to callee saved frame size.
 741   int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
 742   if (TailCallReturnAddrDelta < 0)
 743     X86FI->setCalleeSavedFrameSize(
 744           X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
 745
 746   // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
 747   // function, and use up to 128 bytes of stack space, don't have a frame
 748   // pointer, calls, or dynamic alloca then we do not need to adjust the
 749   // stack pointer (we fit in the Red Zone).
 750   if (Is64Bit && !DisableRedZone &&
 751       !needsStackRealignment(MF) &&
 752       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
 753       !MFI->hasCalls()) {                          // No calls.
 754     uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
 755     if (hasFP(MF)) MinSize += SlotSize;
 756     StackSize = std::max(MinSize,
 757                          StackSize > 128 ? StackSize - 128 : 0);
 758     MFI->setStackSize(StackSize);
 759   }
 760
 761   // Insert stack pointer adjustment for later moving of return addr.  Only
 762   // applies to tail call optimized functions where the callee argument stack
 763   // size is bigger than the callers.
 764   if (TailCallReturnAddrDelta < 0) {
 765     MachineInstr *MI =
 766       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
 767               StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
 768     // The EFLAGS implicit def is dead.
 769     MI->getOperand(3).setIsDead();
 770   }
 771
 772   uint64_t NumBytes = 0;
 773   if (hasFP(MF)) {
 774     // Calculate required stack adjustment
 775     uint64_t FrameSize = StackSize - SlotSize;
 776     if (needsStackRealignment(MF))
 777       FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
 778
 779     NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
 780
 781     // Get the offset of the stack slot for the EBP register... which is
 782     // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
 783     // Update the frame offset adjustment.
 784     MFI->setOffsetAdjustment(-NumBytes);
 785
 786     // Save EBP into the appropriate stack slot...
 787     BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
 788       .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
 789
 790     if (needsFrameMoves) {
 791       // Mark effective beginning of when frame pointer becomes valid.
 792       FrameLabelId = MMI->NextLabelID();
 793       BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
 794     }
 795
 796     // Update EBP with the new base value...
 797     BuildMI(MBB, MBBI, DL,
 798             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
 799         .addReg(StackPtr);
 800
 801     // Mark the FramePtr as live-in in every block except the entry.
 802     for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
 803          I != E; ++I)
 804       I->addLiveIn(FramePtr);
 805
 806     // Realign stack
 807     if (needsStackRealignment(MF)) {
 808       MachineInstr *MI =
 809         BuildMI(MBB, MBBI, DL,
 810                 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
 811                 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
 812       // The EFLAGS implicit def is dead.
 813       MI->getOperand(3).setIsDead();
 814     }
 815   } else
 816     NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
 817
 818   unsigned ReadyLabelId = 0;
 819   if (needsFrameMoves) {
 820     // Mark effective beginning of when frame pointer is ready.
 821     ReadyLabelId = MMI->NextLabelID();
 822     BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
 823   }
 824
 825   // Skip the callee-saved push instructions.
 826   while (MBBI != MBB.end() &&
 827          (MBBI->getOpcode() == X86::PUSH32r ||
 828           MBBI->getOpcode() == X86::PUSH64r))
 829     ++MBBI;
 830
 831   if (NumBytes) {   // adjust stack pointer: ESP -= numbytes
 832     if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
 833       // Check, whether EAX is livein for this function
 834       bool isEAXAlive = false;
 835       for (MachineRegisterInfo::livein_iterator
 836            II = MF.getRegInfo().livein_begin(),
 837            EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
 838         unsigned Reg = II->first;
 839         isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
 840                       Reg == X86::AH || Reg == X86::AL);
 841       }
 842
 843       // Function prologue calls _alloca to probe the stack when allocating
 844       // more than 4k bytes in one go. Touching the stack at 4K increments is
 845       // necessary to ensure that the guard pages used by the OS virtual memory
 846       // manager are allocated in correct sequence.
 847       if (!isEAXAlive) {
 848         BuildMI(MBB, MBBI,DL, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
 849         BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
 850           .addExternalSymbol("_alloca");
 851       } else {
 852         // Save EAX
 853         BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
 854           .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
 855         // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
 856         // allocated bytes for EAX.
 857         BuildMI(MBB, MBBI, DL,
 858                 TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
 859         BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
 860           .addExternalSymbol("_alloca");
 861         // Restore EAX
 862         MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
 863                                                 X86::EAX),
 864                                         StackPtr, false, NumBytes-4);
 865         MBB.insert(MBBI, MI);
 866       }
 867     } else {
 868       // If there is an SUB32ri of ESP immediately before this instruction,
 869       // merge the two. This can be the case when tail call elimination is
 870       // enabled and the callee has more arguments then the caller.
 871       NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
 872       // If there is an ADD32ri or SUB32ri of ESP immediately after this
 873       // instruction, merge the two instructions.
 874       mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
 875
 876       if (NumBytes)
 877         emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
 878     }
 879   }
 880
 881   if (needsFrameMoves)
 882     emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
 883 }
 884
 885 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
 886                                    MachineBasicBlock &MBB) const {
 887   const MachineFrameInfo *MFI = MF.getFrameInfo();
 888   X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
 889   MachineBasicBlock::iterator MBBI = prior(MBB.end());
 890   unsigned RetOpcode = MBBI->getOpcode();
 891   DebugLoc DL = MBBI->getDebugLoc();
 892
 893   switch (RetOpcode) {
 894   case X86::RET:
 895   case X86::RETI:
 896   case X86::TCRETURNdi:
 897   case X86::TCRETURNri:
 898   case X86::TCRETURNri64:
 899   case X86::TCRETURNdi64:
 900   case X86::EH_RETURN:
 901   case X86::EH_RETURN64:
 902   case X86::TAILJMPd:
 903   case X86::TAILJMPr:
 904   case X86::TAILJMPm: break;  // These are ok
 905   default:
 906     assert(0 && "Can only insert epilog into returning blocks");
 907   }
 908
 909   // Get the number of bytes to allocate from the FrameInfo
 910   uint64_t StackSize = MFI->getStackSize();
 911   uint64_t MaxAlign  = MFI->getMaxAlignment();
 912   unsigned CSSize = X86FI->getCalleeSavedFrameSize();
 913   uint64_t NumBytes = 0;
 914
 915   if (hasFP(MF)) {
 916     // Calculate required stack adjustment
 917     uint64_t FrameSize = StackSize - SlotSize;
 918     if (needsStackRealignment(MF))
 919       FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
 920
 921     NumBytes = FrameSize - CSSize;
 922
 923     // pop EBP.
 924     BuildMI(MBB, MBBI, DL,
 925             TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
 926   } else {
 927     NumBytes = StackSize - CSSize;
 928   }
 929
 930   // Skip the callee-saved pop instructions.
 931   MachineBasicBlock::iterator LastCSPop = MBBI;
 932   while (MBBI != MBB.begin()) {
 933     MachineBasicBlock::iterator PI = prior(MBBI);
 934     unsigned Opc = PI->getOpcode();
 935     if (Opc != X86::POP32r && Opc != X86::POP64r &&
 936         !PI->getDesc().isTerminator())
 937       break;
 938     --MBBI;
 939   }
 940
 941   // If there is an ADD32ri or SUB32ri of ESP immediately before this
 942   // instruction, merge the two instructions.
 943   if (NumBytes || MFI->hasVarSizedObjects())
 944     mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
 945
 946   // If dynamic alloca is used, then reset esp to point to the last callee-saved
 947   // slot before popping them off! Same applies for the case, when stack was
 948   // realigned
 949   if (needsStackRealignment(MF)) {
 950     // We cannot use LEA here, because stack pointer was realigned. We need to
 951     // deallocate local frame back
 952     if (CSSize) {
 953       emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
 954       MBBI = prior(LastCSPop);
 955     }
 956
 957     BuildMI(MBB, MBBI, DL,
 958             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
 959             StackPtr).addReg(FramePtr);
 960   } else if (MFI->hasVarSizedObjects()) {
 961     if (CSSize) {
 962       unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
 963       MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
 964                                       FramePtr, false, -CSSize);
 965       MBB.insert(MBBI, MI);
 966     } else
 967       BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
 968               StackPtr).addReg(FramePtr);
 969
 970   } else {
 971     // adjust stack pointer back: ESP += numbytes
 972     if (NumBytes)
 973       emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
 974   }
 975
 976   // We're returning from function via eh_return.
 977   if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
 978     MBBI = prior(MBB.end());
 979     MachineOperand &DestAddr  = MBBI->getOperand(0);
 980     assert(DestAddr.isReg() && "Offset should be in register!");
 981     BuildMI(MBB, MBBI, DL,
 982             TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
 983             StackPtr).addReg(DestAddr.getReg());
 984   // Tail call return: adjust the stack pointer and jump to callee
 985   } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
 986              RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
 987     MBBI = prior(MBB.end());
 988     MachineOperand &JumpTarget = MBBI->getOperand(0);
 989     MachineOperand &StackAdjust = MBBI->getOperand(1);
 990     assert(StackAdjust.isImm() && "Expecting immediate value.");
 991
 992     // Adjust stack pointer.
 993     int StackAdj = StackAdjust.getImm();
 994     int MaxTCDelta = X86FI->getTCReturnAddrDelta();
 995     int Offset = 0;
 996     assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
 997     // Incoporate the retaddr area.
 998     Offset = StackAdj-MaxTCDelta;
 999     assert(Offset >= 0 && "Offset should never be negative");
1000     if (Offset) {
1001       // Check for possible merge with preceeding ADD instruction.
1002       Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1003       emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1004     }
1005     // Jump to label or value in register.
1006     if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1007       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1008         addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1009     else if (RetOpcode== X86::TCRETURNri64) {
1010       BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1011     } else
1012        BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1013     // Delete the pseudo instruction TCRETURN.
1014     MBB.erase(MBBI);
1015   } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1016              (X86FI->getTCReturnAddrDelta() < 0)) {
1017     // Add the return addr area delta back since we are not tail calling.
1018     int delta = -1*X86FI->getTCReturnAddrDelta();
1019     MBBI = prior(MBB.end());
1020     // Check for possible merge with preceeding ADD instruction.
1021     delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1022     emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1023   }
1024 }
1025
1026 unsigned X86RegisterInfo::getRARegister() const {
1027   if (Is64Bit)
1028     return X86::RIP;  // Should have dwarf #16
1029   else
1030     return X86::EIP;  // Should have dwarf #8
1031 }
1032
1033 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1034   return hasFP(MF) ? FramePtr : StackPtr;
1035 }
1036
1037 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1038                                                                          const {
1039   // Calculate amount of bytes used for return address storing
1040   int stackGrowth = (Is64Bit ? -8 : -4);
1041
1042   // Initial state of the frame pointer is esp+4.
1043   MachineLocation Dst(MachineLocation::VirtualFP);
1044   MachineLocation Src(StackPtr, stackGrowth);
1045   Moves.push_back(MachineMove(0, Dst, Src));
1046
1047   // Add return address to move list
1048   MachineLocation CSDst(StackPtr, stackGrowth);
1049   MachineLocation CSSrc(getRARegister());
1050   Moves.push_back(MachineMove(0, CSDst, CSSrc));
1051 }
1052
1053 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1054   assert(0 && "What is the exception register");
1055   return 0;
1056 }
1057
1058 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1059   assert(0 && "What is the exception handler register");
1060   return 0;
1061 }
1062
1063 namespace llvm {
1064 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1065   switch (VT.getSimpleVT()) {
1066   default: return Reg;
1067   case MVT::i8:
1068     if (High) {
1069       switch (Reg) {
1070       default: return 0;
1071       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1072         return X86::AH;
1073       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1074         return X86::DH;
1075       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1076         return X86::CH;
1077       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1078         return X86::BH;
1079       }
1080     } else {
1081       switch (Reg) {
1082       default: return 0;
1083       case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1084         return X86::AL;
1085       case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1086         return X86::DL;
1087       case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1088         return X86::CL;
1089       case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1090         return X86::BL;
1091       case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1092         return X86::SIL;
1093       case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1094         return X86::DIL;
1095       case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1096         return X86::BPL;
1097       case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1098         return X86::SPL;
1099       case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1100         return X86::R8B;
1101       case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1102         return X86::R9B;
1103       case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1104         return X86::R10B;
1105       case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1106         return X86::R11B;
1107       case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1108         return X86::R12B;
1109       case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1110         return X86::R13B;
1111       case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1112         return X86::R14B;
1113       case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1114         return X86::R15B;
1115       }
1116     }
1117   case MVT::i16:
1118     switch (Reg) {
1119     default: return Reg;
1120     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1121       return X86::AX;
1122     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1123       return X86::DX;
1124     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1125       return X86::CX;
1126     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1127       return X86::BX;
1128     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1129       return X86::SI;
1130     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1131       return X86::DI;
1132     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1133       return X86::BP;
1134     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1135       return X86::SP;
1136     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1137       return X86::R8W;
1138     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1139       return X86::R9W;
1140     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1141       return X86::R10W;
1142     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1143       return X86::R11W;
1144     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1145       return X86::R12W;
1146     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1147       return X86::R13W;
1148     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1149       return X86::R14W;
1150     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1151       return X86::R15W;
1152     }
1153   case MVT::i32:
1154     switch (Reg) {
1155     default: return Reg;
1156     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1157       return X86::EAX;
1158     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1159       return X86::EDX;
1160     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1161       return X86::ECX;
1162     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1163       return X86::EBX;
1164     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1165       return X86::ESI;
1166     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1167       return X86::EDI;
1168     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1169       return X86::EBP;
1170     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1171       return X86::ESP;
1172     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1173       return X86::R8D;
1174     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1175       return X86::R9D;
1176     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1177       return X86::R10D;
1178     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1179       return X86::R11D;
1180     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1181       return X86::R12D;
1182     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1183       return X86::R13D;
1184     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1185       return X86::R14D;
1186     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1187       return X86::R15D;
1188     }
1189   case MVT::i64:
1190     switch (Reg) {
1191     default: return Reg;
1192     case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1193       return X86::RAX;
1194     case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1195       return X86::RDX;
1196     case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1197       return X86::RCX;
1198     case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1199       return X86::RBX;
1200     case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1201       return X86::RSI;
1202     case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1203       return X86::RDI;
1204     case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1205       return X86::RBP;
1206     case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1207       return X86::RSP;
1208     case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1209       return X86::R8;
1210     case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1211       return X86::R9;
1212     case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1213       return X86::R10;
1214     case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1215       return X86::R11;
1216     case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1217       return X86::R12;
1218     case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1219       return X86::R13;
1220     case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1221       return X86::R14;
1222     case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1223       return X86::R15;
1224     }
1225   }
1226
1227   return Reg;
1228 }
1229 }
1230
1231 #include "X86GenRegisterInfo.inc"
1232
1233 namespace {
1234   struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1235     static char ID;
1236     MSAC() : MachineFunctionPass(&ID) {}
1237
1238     virtual bool runOnMachineFunction(MachineFunction &MF) {
1239       MachineFrameInfo *FFI = MF.getFrameInfo();
1240       MachineRegisterInfo &RI = MF.getRegInfo();
1241
1242       // Calculate max stack alignment of all already allocated stack objects.
1243       unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1244
1245       // Be over-conservative: scan over all vreg defs and find, whether vector
1246       // registers are used. If yes - there is probability, that vector register
1247       // will be spilled and thus stack needs to be aligned properly.
1248       for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1249            RegNum < RI.getLastVirtReg(); ++RegNum)
1250         MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1251
1252       FFI->setMaxAlignment(MaxAlign);
1253
1254       return false;
1255     }
1256
1257     virtual const char *getPassName() const {
1258       return "X86 Maximal Stack Alignment Calculator";
1259     }
1260   };
1261
1262   char MSAC::ID = 0;
1263 }
1264
1265 FunctionPass*
1266 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }