lib/Target/IA64/IA64ISelDAGToDAG.cpp

   1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for IA64,
  11 // converting a legalized dag to an IA64 dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #define DEBUG_TYPE "ia64-codegen"
  16 #include "IA64.h"
  17 #include "IA64TargetMachine.h"
  18 #include "IA64ISelLowering.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/SelectionDAG.h"
  22 #include "llvm/CodeGen/SelectionDAGISel.h"
  23 #include "llvm/Target/TargetOptions.h"
  24 #include "llvm/Constants.h"
  25 #include "llvm/GlobalValue.h"
  26 #include "llvm/Intrinsics.h"
  27 #include "llvm/Support/Compiler.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/Support/MathExtras.h"
  30 using namespace llvm;
  31
  32 namespace {
  33   //===--------------------------------------------------------------------===//
  34   /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
  35   /// instructions for SelectionDAG operations.
  36   ///
  37   class IA64DAGToDAGISel : public SelectionDAGISel {
  38     unsigned GlobalBaseReg;
  39   public:
  40     explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
  41       : SelectionDAGISel(TM) {}
  42
  43     virtual bool runOnFunction(Function &Fn) {
  44       // Make sure we re-emit a set of the global base reg if necessary
  45       GlobalBaseReg = 0;
  46       return SelectionDAGISel::runOnFunction(Fn);
  47     }
  48
  49     /// getI64Imm - Return a target constant with the specified value, of type
  50     /// i64.
  51     inline SDValue getI64Imm(uint64_t Imm) {
  52       return CurDAG->getTargetConstant(Imm, MVT::i64);
  53     }
  54
  55     /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
  56     /// base register.  Return the virtual register that holds this value.
  57     // SDValue getGlobalBaseReg(); TODO: hmm
  58
  59     // Select - Convert the specified operand from a target-independent to a
  60     // target-specific node if it hasn't already been changed.
  61     SDNode *Select(SDValue N);
  62
  63     SDNode *SelectIntImmediateExpr(SDValue LHS, SDValue RHS,
  64                                    unsigned OCHi, unsigned OCLo,
  65                                    bool IsArithmetic = false,
  66                                    bool Negate = false);
  67     SDNode *SelectBitfieldInsert(SDNode *N);
  68
  69     /// SelectCC - Select a comparison of the specified values with the
  70     /// specified condition code, returning the CR# of the expression.
  71     SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
  72
  73     /// SelectAddr - Given the specified address, return the two operands for a
  74     /// load/store instruction, and return true if it should be an indexed [r+r]
  75     /// operation.
  76     bool SelectAddr(SDValue Addr, SDValue &Op1, SDValue &Op2);
  77
  78     /// InstructionSelect - This callback is invoked by
  79     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
  80     virtual void InstructionSelect();
  81
  82     virtual const char *getPassName() const {
  83       return "IA64 (Itanium) DAG->DAG Instruction Selector";
  84     }
  85
  86 // Include the pieces autogenerated from the target description.
  87 #include "IA64GenDAGISel.inc"
  88
  89 private:
  90     SDNode *SelectDIV(SDValue Op);
  91   };
  92 }
  93
  94 /// InstructionSelect - This callback is invoked by
  95 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
  96 void IA64DAGToDAGISel::InstructionSelect() {
  97   DEBUG(BB->dump());
  98
  99   // Select target instructions for the DAG.
 100   SelectRoot(*CurDAG);
 101   CurDAG->RemoveDeadNodes();
 102 }
 103
 104 SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
 105   SDNode *N = Op.getNode();
 106   SDValue Chain = N->getOperand(0);
 107   SDValue Tmp1 = N->getOperand(0);
 108   SDValue Tmp2 = N->getOperand(1);
 109   DebugLoc dl = N->getDebugLoc();
 110
 111   bool isFP=false;
 112
 113   if(Tmp1.getValueType().isFloatingPoint())
 114     isFP=true;
 115
 116   bool isModulus=false; // is it a division or a modulus?
 117   bool isSigned=false;
 118
 119   switch(N->getOpcode()) {
 120     case ISD::FDIV:
 121     case ISD::SDIV:  isModulus=false; isSigned=true;  break;
 122     case ISD::UDIV:  isModulus=false; isSigned=false; break;
 123     case ISD::FREM:
 124     case ISD::SREM:  isModulus=true;  isSigned=true;  break;
 125     case ISD::UREM:  isModulus=true;  isSigned=false; break;
 126   }
 127
 128   // TODO: check for integer divides by powers of 2 (or other simple patterns?)
 129
 130     SDValue TmpPR, TmpPR2;
 131     SDValue TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
 132     SDValue TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
 133     SDNode *Result;
 134
 135     // we'll need copies of F0 and F1
 136     SDValue F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
 137     SDValue F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
 138
 139     // OK, emit some code:
 140
 141     if(!isFP) {
 142       // first, load the inputs into FP regs.
 143       TmpF1 =
 144         SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp1), 0);
 145       Chain = TmpF1.getValue(1);
 146       TmpF2 =
 147         SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp2), 0);
 148       Chain = TmpF2.getValue(1);
 149
 150       // next, convert the inputs to FP
 151       if(isSigned) {
 152         TmpF3 =
 153           SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF1), 0);
 154         Chain = TmpF3.getValue(1);
 155         TmpF4 =
 156           SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF2), 0);
 157         Chain = TmpF4.getValue(1);
 158       } else { // is unsigned
 159         TmpF3 =
 160           SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF1),
 161                   0);
 162         Chain = TmpF3.getValue(1);
 163         TmpF4 =
 164           SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF2),
 165                   0);
 166         Chain = TmpF4.getValue(1);
 167       }
 168
 169     } else { // this is an FP divide/remainder, so we 'leak' some temp
 170              // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
 171       TmpF3=Tmp1;
 172       TmpF4=Tmp2;
 173     }
 174
 175     // we start by computing an approximate reciprocal (good to 9 bits?)
 176     // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
 177     if(isFP)
 178       TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, dl, MVT::f64,
 179                                             MVT::i1, TmpF3, TmpF4), 0);
 180     else
 181       TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, dl, MVT::f64,
 182                                             MVT::i1, TmpF3, TmpF4), 0);
 183
 184     TmpPR = TmpF5.getValue(1);
 185     Chain = TmpF5.getValue(2);
 186
 187     SDValue minusB;
 188     if(isModulus) { // for remainders, it'll be handy to have
 189                              // copies of -input_b
 190       minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, dl, MVT::i64,
 191                   CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
 192       Chain = minusB.getValue(1);
 193     }
 194
 195     SDValue TmpE0, TmpY1, TmpE1, TmpY2;
 196
 197     SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
 198     TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
 199                                             OpsE0, 4), 0);
 200     Chain = TmpE0.getValue(1);
 201     SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
 202     TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
 203                                             OpsY1, 4), 0);
 204     Chain = TmpY1.getValue(1);
 205     SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
 206     TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
 207                                             OpsE1, 4), 0);
 208     Chain = TmpE1.getValue(1);
 209     SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
 210     TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
 211                                             OpsY2, 4), 0);
 212     Chain = TmpY2.getValue(1);
 213
 214     if(isFP) { // if this is an FP divide, we finish up here and exit early
 215       if(isModulus)
 216         assert(0 && "Sorry, try another FORTRAN compiler.");
 217
 218       SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
 219
 220       SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
 221       TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
 222                                               OpsE2, 4), 0);
 223       Chain = TmpE2.getValue(1);
 224       SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
 225       TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
 226                                               OpsY3, 4), 0);
 227       Chain = TmpY3.getValue(1);
 228       SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
 229       TmpQ0 =
 230         SDValue(CurDAG->getTargetNode(IA64::CFMADS1, dl,  // double prec!
 231                                       MVT::f64, OpsQ0, 4), 0);
 232       Chain = TmpQ0.getValue(1);
 233       SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
 234       TmpR0 =
 235         SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, dl, // double prec!
 236                                       MVT::f64, OpsR0, 4), 0);
 237       Chain = TmpR0.getValue(1);
 238
 239 // we want Result to have the same target register as the frcpa, so
 240 // we two-address hack it. See the comment "for this to work..." on
 241 // page 48 of Intel application note #245415
 242       SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
 243       Result = CurDAG->getTargetNode(IA64::TCFMADS0, dl, // d.p. s0 rndg!
 244                                      MVT::f64, Ops, 5);
 245       Chain = SDValue(Result, 1);
 246       return Result; // XXX: early exit!
 247     } else { // this is *not* an FP divide, so there's a bit left to do:
 248
 249       SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
 250
 251       SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
 252       TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64,
 253                                               OpsQ2, 4), 0);
 254       Chain = TmpQ2.getValue(1);
 255       SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
 256       TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64,
 257                                               OpsR2, 4), 0);
 258       Chain = TmpR2.getValue(1);
 259
 260 // we want TmpQ3 to have the same target register as the frcpa? maybe we
 261 // should two-address hack it. See the comment "for this to work..." on page
 262 // 48 of Intel application note #245415
 263       SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
 264       TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, dl, MVT::f64,
 265                                          OpsQ3, 5), 0);
 266       Chain = TmpQ3.getValue(1);
 267
 268       // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
 269       // the FPSWA won't be able to help out in the case of large/tiny
 270       // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
 271
 272       if(isSigned)
 273         TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, dl,
 274                                                MVT::f64, TmpQ3), 0);
 275       else
 276         TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, dl,
 277                                                MVT::f64, TmpQ3), 0);
 278
 279       Chain = TmpQ.getValue(1);
 280
 281       if(isModulus) {
 282         SDValue FPminusB =
 283           SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, minusB),
 284                   0);
 285         Chain = FPminusB.getValue(1);
 286         SDValue Remainder =
 287           SDValue(CurDAG->getTargetNode(IA64::XMAL, dl, MVT::f64,
 288                                           TmpQ, FPminusB, TmpF1), 0);
 289         Chain = Remainder.getValue(1);
 290         Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, Remainder);
 291         Chain = SDValue(Result, 1);
 292       } else { // just an integer divide
 293         Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, TmpQ);
 294         Chain = SDValue(Result, 1);
 295       }
 296
 297       return Result;
 298     } // wasn't an FP divide
 299 }
 300
 301 // Select - Convert the specified operand from a target-independent to a
 302 // target-specific node if it hasn't already been changed.
 303 SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
 304   SDNode *N = Op.getNode();
 305   if (N->isMachineOpcode())
 306     return NULL;   // Already selected.
 307   DebugLoc dl = Op.getDebugLoc();
 308
 309   switch (N->getOpcode()) {
 310   default: break;
 311
 312   case IA64ISD::BRCALL: { // XXX: this is also a hack!
 313     SDValue Chain = N->getOperand(0);
 314     SDValue InFlag;  // Null incoming flag value.
 315
 316     if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
 317       InFlag = N->getOperand(2);
 318     }
 319
 320     unsigned CallOpcode;
 321     SDValue CallOperand;
 322
 323     // if we can call directly, do so
 324     if (GlobalAddressSDNode *GASD =
 325       dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
 326       CallOpcode = IA64::BRCALL_IPREL_GA;
 327       CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
 328     } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
 329       // FIXME: we currently NEED this case for correctness, to avoid
 330       // "non-pic code with imm reloc.n against dynamic symbol" errors
 331     CallOpcode = IA64::BRCALL_IPREL_ES;
 332     CallOperand = N->getOperand(1);
 333   } else {
 334     // otherwise we need to load the function descriptor,
 335     // load the branch target (function)'s entry point and GP,
 336     // branch (call) then restore the GP
 337     SDValue FnDescriptor = N->getOperand(1);
 338
 339     // load the branch target's entry point [mem] and
 340     // GP value [mem+8]
 341     SDValue targetEntryPoint=
 342       SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other,
 343                                       FnDescriptor, CurDAG->getEntryNode()), 0);
 344     Chain = targetEntryPoint.getValue(1);
 345     SDValue targetGPAddr=
 346       SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64,
 347                                       FnDescriptor,
 348                                       CurDAG->getConstant(8, MVT::i64)), 0);
 349     Chain = targetGPAddr.getValue(1);
 350     SDValue targetGP =
 351       SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other,
 352                                       targetGPAddr, CurDAG->getEntryNode()), 0);
 353     Chain = targetGP.getValue(1);
 354
 355     Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag);
 356     InFlag = Chain.getValue(1);
 357     Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6,
 358                                  targetEntryPoint, InFlag); // FLAG these?
 359     InFlag = Chain.getValue(1);
 360
 361     CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
 362     CallOpcode = IA64::BRCALL_INDIRECT;
 363   }
 364
 365    // Finally, once everything is setup, emit the call itself
 366    if (InFlag.getNode())
 367      Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
 368                                            MVT::Flag, CallOperand, InFlag), 0);
 369    else // there might be no arguments
 370      Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
 371                                            MVT::Flag, CallOperand, Chain), 0);
 372    InFlag = Chain.getValue(1);
 373
 374    std::vector<SDValue> CallResults;
 375
 376    CallResults.push_back(Chain);
 377    CallResults.push_back(InFlag);
 378
 379    for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
 380      ReplaceUses(Op.getValue(i), CallResults[i]);
 381    return NULL;
 382   }
 383
 384   case IA64ISD::GETFD: {
 385     SDValue Input = N->getOperand(0);
 386     return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input);
 387   }
 388
 389   case ISD::FDIV:
 390   case ISD::SDIV:
 391   case ISD::UDIV:
 392   case ISD::SREM:
 393   case ISD::UREM:
 394     return SelectDIV(Op);
 395
 396   case ISD::TargetConstantFP: {
 397     SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so..
 398
 399     SDValue V;
 400     ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
 401     if (N2->getValueAPF().isPosZero()) {
 402       V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64);
 403     } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
 404                                   APFloat(+1.0f) : APFloat(+1.0))) {
 405       V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
 406     } else
 407       assert(0 && "Unexpected FP constant!");
 408
 409     ReplaceUses(SDValue(N, 0), V);
 410     return 0;
 411   }
 412
 413   case ISD::FrameIndex: { // TODO: reduce creepyness
 414     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 415     if (N->hasOneUse())
 416       return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
 417                                   CurDAG->getTargetFrameIndex(FI, MVT::i64));
 418     else
 419       return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64,
 420                                    CurDAG->getTargetFrameIndex(FI, MVT::i64));
 421   }
 422
 423   case ISD::ConstantPool: { // TODO: nuke the constant pool
 424     // (ia64 doesn't need one)
 425     ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
 426     Constant *C = CP->getConstVal();
 427     SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
 428                                                   CP->getAlignment());
 429     return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ?
 430                                  CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
 431   }
 432
 433   case ISD::GlobalAddress: {
 434     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
 435     SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
 436     SDValue Tmp =
 437       SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64,
 438                                       CurDAG->getRegister(IA64::r1,
 439                                                           MVT::i64), GA), 0);
 440     return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp,
 441                                  CurDAG->getEntryNode());
 442   }
 443
 444 /* XXX
 445    case ISD::ExternalSymbol: {
 446      SDValue EA = CurDAG->getTargetExternalSymbol(
 447        cast<ExternalSymbolSDNode>(N)->getSymbol(),
 448        MVT::i64);
 449      SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64,
 450                                            CurDAG->getRegister(IA64::r1,
 451                                                                MVT::i64),
 452                                            EA);
 453      return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp);
 454    }
 455 */
 456
 457   case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
 458     LoadSDNode *LD = cast<LoadSDNode>(N);
 459     SDValue Chain = LD->getChain();
 460     SDValue Address = LD->getBasePtr();
 461
 462     MVT TypeBeingLoaded = LD->getMemoryVT();
 463     unsigned Opc;
 464     switch (TypeBeingLoaded.getSimpleVT()) {
 465     default:
 466 #ifndef NDEBUG
 467       N->dump(CurDAG);
 468 #endif
 469       assert(0 && "Cannot load this type!");
 470     case MVT::i1: { // this is a bool
 471       Opc = IA64::LD1; // first we load a byte, then compare for != 0
 472       if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
 473         return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
 474                                     SDValue(CurDAG->getTargetNode(Opc, dl,
 475                                                                   MVT::i64,
 476                                                                   Address), 0),
 477                                     CurDAG->getRegister(IA64::r0, MVT::i64),
 478                                     Chain);
 479       }
 480       /* otherwise, we want to load a bool into something bigger: LD1
 481          will do that for us, so we just fall through */
 482     }
 483     case MVT::i8:  Opc = IA64::LD1; break;
 484     case MVT::i16: Opc = IA64::LD2; break;
 485     case MVT::i32: Opc = IA64::LD4; break;
 486     case MVT::i64: Opc = IA64::LD8; break;
 487
 488     case MVT::f32: Opc = IA64::LDF4; break;
 489     case MVT::f64: Opc = IA64::LDF8; break;
 490     }
 491
 492     // TODO: comment this
 493     return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
 494                                 Address, Chain);
 495   }
 496
 497   case ISD::STORE: {
 498     StoreSDNode *ST = cast<StoreSDNode>(N);
 499     SDValue Address = ST->getBasePtr();
 500     SDValue Chain = ST->getChain();
 501
 502     unsigned Opc;
 503     if (ISD::isNON_TRUNCStore(N)) {
 504       switch (N->getOperand(1).getValueType().getSimpleVT()) {
 505       default: assert(0 && "unknown type in store");
 506       case MVT::i1: { // this is a bool
 507         Opc = IA64::ST1; // we store either 0 or 1 as a byte
 508         // first load zero!
 509         SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64);
 510         Chain = Initial.getValue(1);
 511         // then load 1 into the same reg iff the predicate to store is 1
 512         SDValue Tmp = ST->getValue();
 513         Tmp =
 514           SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial,
 515                                           CurDAG->getTargetConstant(1,
 516                                                                     MVT::i64),
 517                                           Tmp), 0);
 518         return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
 519       }
 520       case MVT::i64: Opc = IA64::ST8;  break;
 521       case MVT::f64: Opc = IA64::STF8; break;
 522       }
 523     } else { // Truncating store
 524       switch(ST->getMemoryVT().getSimpleVT()) {
 525       default: assert(0 && "unknown type in truncstore");
 526       case MVT::i8:  Opc = IA64::ST1;  break;
 527       case MVT::i16: Opc = IA64::ST2;  break;
 528       case MVT::i32: Opc = IA64::ST4;  break;
 529       case MVT::f32: Opc = IA64::STF4; break;
 530       }
 531     }
 532
 533     SDValue N1 = N->getOperand(1);
 534     SDValue N2 = N->getOperand(2);
 535     return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
 536   }
 537
 538   case ISD::BRCOND: {
 539     SDValue Chain = N->getOperand(0);
 540     SDValue CC = N->getOperand(1);
 541     MachineBasicBlock *Dest =
 542       cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
 543     //FIXME - we do NOT need long branches all the time
 544     return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
 545                                 CurDAG->getBasicBlock(Dest), Chain);
 546   }
 547
 548   case ISD::CALLSEQ_START:
 549   case ISD::CALLSEQ_END: {
 550     int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
 551     unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
 552       IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
 553     SDValue N0 = N->getOperand(0);
 554     return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
 555   }
 556
 557   case ISD::BR:
 558     // FIXME: we don't need long branches all the time!
 559     SDValue N0 = N->getOperand(0);
 560     return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
 561                                 N->getOperand(1), N0);
 562   }
 563
 564   return SelectCode(Op);
 565 }
 566
 567
 568 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
 569 /// into an IA64-specific DAG, ready for instruction scheduling.
 570 ///
 571 FunctionPass
 572 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
 573   return new IA64DAGToDAGISel(TM);
 574 }
 575