1 //===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64InstrInfo.h"
16 #include "IA64InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "IA64GenInstrInfo.inc"
22 IA64InstrInfo::IA64InstrInfo()
23 : TargetInstrInfoImpl(IA64Insts
, sizeof(IA64Insts
)/sizeof(IA64Insts
[0])),
28 bool IA64InstrInfo::isMoveInstr(const MachineInstr
& MI
,
31 unsigned& SrcSR
, unsigned& DstSR
) const {
32 SrcSR
= DstSR
= 0; // No sub-registers.
34 unsigned oc
= MI
.getOpcode();
35 if (oc
== IA64::MOV
|| oc
== IA64::FMOV
) {
36 // TODO: this doesn't detect predicate moves
37 assert(MI
.getNumOperands() >= 2 &&
38 /* MI.getOperand(0).isReg() &&
39 MI.getOperand(1).isReg() && */
40 "invalid register-register move instruction");
41 if (MI
.getOperand(0).isReg() &&
42 MI
.getOperand(1).isReg()) {
43 // if both operands of the MOV/FMOV are registers, then
44 // yes, this is a move instruction
45 sourceReg
= MI
.getOperand(1).getReg();
46 destReg
= MI
.getOperand(0).getReg();
50 return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
55 IA64InstrInfo::InsertBranch(MachineBasicBlock
&MBB
,MachineBasicBlock
*TBB
,
56 MachineBasicBlock
*FBB
,
57 const SmallVectorImpl
<MachineOperand
> &Cond
)const {
58 // FIXME this should probably have a DebugLoc argument
59 DebugLoc dl
= DebugLoc::getUnknownLoc();
60 // Can only insert uncond branches so far.
61 assert(Cond
.empty() && !FBB
&& TBB
&& "Can only handle uncond branches!");
62 BuildMI(&MBB
, dl
, get(IA64::BRL_NOTCALL
)).addMBB(TBB
);
66 bool IA64InstrInfo::copyRegToReg(MachineBasicBlock
&MBB
,
67 MachineBasicBlock::iterator MI
,
68 unsigned DestReg
, unsigned SrcReg
,
69 const TargetRegisterClass
*DestRC
,
70 const TargetRegisterClass
*SrcRC
) const {
71 if (DestRC
!= SrcRC
) {
76 DebugLoc DL
= DebugLoc::getUnknownLoc();
77 if (MI
!= MBB
.end()) DL
= MI
->getDebugLoc();
79 if(DestRC
== IA64::PRRegisterClass
) // if a bool, we use pseudocode
80 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
81 BuildMI(MBB
, MI
, DL
, get(IA64::PCMPEQUNC
), DestReg
)
82 .addReg(IA64::r0
).addReg(IA64::r0
).addReg(SrcReg
);
83 else // otherwise, MOV works (for both gen. regs and FP regs)
84 BuildMI(MBB
, MI
, DL
, get(IA64::MOV
), DestReg
).addReg(SrcReg
);
89 void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock
&MBB
,
90 MachineBasicBlock::iterator MI
,
91 unsigned SrcReg
, bool isKill
,
93 const TargetRegisterClass
*RC
) const{
94 DebugLoc DL
= DebugLoc::getUnknownLoc();
95 if (MI
!= MBB
.end()) DL
= MI
->getDebugLoc();
97 if (RC
== IA64::FPRegisterClass
) {
98 BuildMI(MBB
, MI
, DL
, get(IA64::STF_SPILL
)).addFrameIndex(FrameIdx
)
99 .addReg(SrcReg
, false, false, isKill
);
100 } else if (RC
== IA64::GRRegisterClass
) {
101 BuildMI(MBB
, MI
, DL
, get(IA64::ST8
)).addFrameIndex(FrameIdx
)
102 .addReg(SrcReg
, false, false, isKill
);
103 } else if (RC
== IA64::PRRegisterClass
) {
104 /* we use IA64::r2 as a temporary register for doing this hackery. */
106 BuildMI(MBB
, MI
, DL
, get(IA64::MOV
), IA64::r2
).addReg(IA64::r0
);
107 // then conditionally add 1:
108 BuildMI(MBB
, MI
, DL
, get(IA64::CADDIMM22
), IA64::r2
).addReg(IA64::r2
)
109 .addImm(1).addReg(SrcReg
, false, false, isKill
);
110 // and then store it to the stack
111 BuildMI(MBB
, MI
, DL
, get(IA64::ST8
))
112 .addFrameIndex(FrameIdx
)
115 "sorry, I don't know how to store this sort of reg in the stack\n");
118 void IA64InstrInfo::storeRegToAddr(MachineFunction
&MF
, unsigned SrcReg
,
120 SmallVectorImpl
<MachineOperand
> &Addr
,
121 const TargetRegisterClass
*RC
,
122 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const {
124 if (RC
== IA64::FPRegisterClass
) {
126 } else if (RC
== IA64::GRRegisterClass
) {
128 } else if (RC
== IA64::PRRegisterClass
) {
132 "sorry, I don't know how to store this sort of reg\n");
135 DebugLoc DL
= DebugLoc::getUnknownLoc();
136 MachineInstrBuilder MIB
= BuildMI(MF
, DL
, get(Opc
));
137 for (unsigned i
= 0, e
= Addr
.size(); i
!= e
; ++i
)
138 MIB
.addOperand(Addr
[i
]);
139 MIB
.addReg(SrcReg
, false, false, isKill
);
140 NewMIs
.push_back(MIB
);
145 void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock
&MBB
,
146 MachineBasicBlock::iterator MI
,
147 unsigned DestReg
, int FrameIdx
,
148 const TargetRegisterClass
*RC
)const{
149 DebugLoc DL
= DebugLoc::getUnknownLoc();
150 if (MI
!= MBB
.end()) DL
= MI
->getDebugLoc();
152 if (RC
== IA64::FPRegisterClass
) {
153 BuildMI(MBB
, MI
, DL
, get(IA64::LDF_FILL
), DestReg
).addFrameIndex(FrameIdx
);
154 } else if (RC
== IA64::GRRegisterClass
) {
155 BuildMI(MBB
, MI
, DL
, get(IA64::LD8
), DestReg
).addFrameIndex(FrameIdx
);
156 } else if (RC
== IA64::PRRegisterClass
) {
157 // first we load a byte from the stack into r2, our 'predicate hackery'
159 BuildMI(MBB
, MI
, DL
, get(IA64::LD8
), IA64::r2
).addFrameIndex(FrameIdx
);
160 // then we compare it to zero. If it _is_ zero, compare-not-equal to
161 // r0 gives us 0, which is what we want, so that's nice.
162 BuildMI(MBB
, MI
, DL
, get(IA64::CMPNE
), DestReg
)
167 "sorry, I don't know how to load this sort of reg from the stack\n");
171 void IA64InstrInfo::loadRegFromAddr(MachineFunction
&MF
, unsigned DestReg
,
172 SmallVectorImpl
<MachineOperand
> &Addr
,
173 const TargetRegisterClass
*RC
,
174 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const {
176 if (RC
== IA64::FPRegisterClass
) {
178 } else if (RC
== IA64::GRRegisterClass
) {
180 } else if (RC
== IA64::PRRegisterClass
) {
184 "sorry, I don't know how to load this sort of reg\n");
187 DebugLoc DL
= DebugLoc::getUnknownLoc();
188 MachineInstrBuilder MIB
= BuildMI(MF
, DL
, get(Opc
), DestReg
);
189 for (unsigned i
= 0, e
= Addr
.size(); i
!= e
; ++i
)
190 MIB
.addOperand(Addr
[i
]);
191 NewMIs
.push_back(MIB
);