5 * Keep the address of the constant pool in a register instead of forming its
6 address all of the time.
7 * We can fold small constant offsets into the %hi/%lo references to constant
8 pool addresses as well.
9 * When in V9 mode, register allocate %icc[0-3].
10 * Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
11 * Emit the 'Branch on Integer Register with Prediction' instructions. It's
12 not clear how to write a pattern for this though:
14 float %t1(int %a, int* %p) {
16 br bool %C, label %T, label %F
18 store int 123, int* %p
39 1) should be replaced with a brz in V9 mode.
41 * Same as above, but emit conditional move on register zero (p192) in V9
44 int %t1(int %a, int %b) {
46 %D = select bool %C, int %a, int %b
50 * Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
51 with the Y register, if they are faster.
53 * Codegen bswap(load)/store(bswap) -> load/store ASI
55 * Implement frame pointer elimination, e.g. eliminate save/restore for