Basic support for mem=>reg moves
[llvm/msp430.git] / lib / Target / Alpha / AlphaISelLowering.h
blobfdd817c76488fc9aa1832f3cd48884bb94d732d4
1 //===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Alpha uses to lower LLVM code into a
11 // selection DAG.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
16 #define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
18 #include "llvm/ADT/VectorExtras.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "Alpha.h"
23 namespace llvm {
25 namespace AlphaISD {
26 enum NodeType {
27 // Start the numbering where the builting ops and target ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 //These corrospond to the identical Instruction
30 CVTQT_, CVTQS_, CVTTQ_,
32 /// GPRelHi/GPRelLo - These represent the high and low 16-bit
33 /// parts of a global address respectively.
34 GPRelHi, GPRelLo,
36 /// RetLit - Literal Relocation of a Global
37 RelLit,
39 /// GlobalRetAddr - used to restore the return address
40 GlobalRetAddr,
42 /// CALL - Normal call.
43 CALL,
45 /// DIVCALL - used for special library calls for div and rem
46 DivCall,
48 /// return flag operand
49 RET_FLAG,
51 /// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
52 /// corresponds to the COND_BRANCH pseudo instruction.
53 /// *PRC is the input register to compare to zero,
54 /// OPC is the branch opcode to use (e.g. Alpha::BEQ),
55 /// DESTBB is the destination block to branch to, and INFLAG is
56 /// an optional input flag argument.
57 COND_BRANCH_I, COND_BRANCH_F
62 class AlphaTargetLowering : public TargetLowering {
63 int VarArgsOffset; // What is the offset to the first vaarg
64 int VarArgsBase; // What is the base FrameIndex
65 bool useITOF;
66 public:
67 explicit AlphaTargetLowering(TargetMachine &TM);
69 /// getSetCCResultType - Get the SETCC result ValueType
70 virtual MVT getSetCCResultType(MVT VT) const;
72 /// LowerOperation - Provide custom lowering hooks for some operations.
73 ///
74 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
76 /// ReplaceNodeResults - Replace the results of node with an illegal result
77 /// type with new values built out of custom code.
78 ///
79 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
80 SelectionDAG &DAG);
82 // Friendly names for dumps
83 const char *getTargetNodeName(unsigned Opcode) const;
85 /// LowerCallTo - This hook lowers an abstract call to a function into an
86 /// actual call.
87 virtual std::pair<SDValue, SDValue>
88 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
89 bool isVarArg, bool isInreg, unsigned CC, bool isTailCall,
90 SDValue Callee, ArgListTy &Args, SelectionDAG &DAG,
91 DebugLoc dl);
93 ConstraintType getConstraintType(const std::string &Constraint) const;
95 std::vector<unsigned>
96 getRegClassForInlineAsmConstraint(const std::string &Constraint,
97 MVT VT) const;
99 bool hasITOF() { return useITOF; }
101 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
102 MachineBasicBlock *BB) const;
104 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
106 private:
107 // Helpers for custom lowering.
108 void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
109 SelectionDAG &DAG);
114 #endif // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H