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Move helper functions for optimizing division by constant into the APInt
[llvm/msp430.git] / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob6974dde6f67473d898abd2cb4089a2dadff5136f
1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/Target/TargetAsmInfo.h"
15 #include "llvm/Target/TargetLowering.h"
16 #include "llvm/Target/TargetSubtarget.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 #include "llvm/GlobalVariable.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/STLExtras.h"
26 #include "llvm/Support/MathExtras.h"
27 using namespace llvm;
28
29 namespace llvm {
30 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
31 bool isLocal = GV->hasLocalLinkage();
32 bool isDeclaration = GV->isDeclaration();
33 // FIXME: what should we do for protected and internal visibility?
34 // For variables, is internal different from hidden?
35 bool isHidden = GV->hasHiddenVisibility();
36
37 if (reloc == Reloc::PIC_) {
38 if (isLocal || isHidden)
39 return TLSModel::LocalDynamic;
40 else
41 return TLSModel::GeneralDynamic;
42 } else {
43 if (!isDeclaration || isHidden)
44 return TLSModel::LocalExec;
45 else
46 return TLSModel::InitialExec;
47 }
48 }
49 }
50
51 /// InitLibcallNames - Set default libcall names.
52 ///
53 static void InitLibcallNames(const char **Names) {
54 Names[RTLIB::SHL_I16] = "__ashli16";
55 Names[RTLIB::SHL_I32] = "__ashlsi3";
56 Names[RTLIB::SHL_I64] = "__ashldi3";
57 Names[RTLIB::SHL_I128] = "__ashlti3";
58 Names[RTLIB::SRL_I16] = "__lshri16";
59 Names[RTLIB::SRL_I32] = "__lshrsi3";
60 Names[RTLIB::SRL_I64] = "__lshrdi3";
61 Names[RTLIB::SRL_I128] = "__lshrti3";
62 Names[RTLIB::SRA_I16] = "__ashri16";
63 Names[RTLIB::SRA_I32] = "__ashrsi3";
64 Names[RTLIB::SRA_I64] = "__ashrdi3";
65 Names[RTLIB::SRA_I128] = "__ashrti3";
66 Names[RTLIB::MUL_I16] = "__muli16";
67 Names[RTLIB::MUL_I32] = "__mulsi3";
68 Names[RTLIB::MUL_I64] = "__muldi3";
69 Names[RTLIB::MUL_I128] = "__multi3";
70 Names[RTLIB::SDIV_I32] = "__divsi3";
71 Names[RTLIB::SDIV_I64] = "__divdi3";
72 Names[RTLIB::SDIV_I128] = "__divti3";
73 Names[RTLIB::UDIV_I32] = "__udivsi3";
74 Names[RTLIB::UDIV_I64] = "__udivdi3";
75 Names[RTLIB::UDIV_I128] = "__udivti3";
76 Names[RTLIB::SREM_I32] = "__modsi3";
77 Names[RTLIB::SREM_I64] = "__moddi3";
78 Names[RTLIB::SREM_I128] = "__modti3";
79 Names[RTLIB::UREM_I32] = "__umodsi3";
80 Names[RTLIB::UREM_I64] = "__umoddi3";
81 Names[RTLIB::UREM_I128] = "__umodti3";
82 Names[RTLIB::NEG_I32] = "__negsi2";
83 Names[RTLIB::NEG_I64] = "__negdi2";
84 Names[RTLIB::ADD_F32] = "__addsf3";
85 Names[RTLIB::ADD_F64] = "__adddf3";
86 Names[RTLIB::ADD_F80] = "__addxf3";
87 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
88 Names[RTLIB::SUB_F32] = "__subsf3";
89 Names[RTLIB::SUB_F64] = "__subdf3";
90 Names[RTLIB::SUB_F80] = "__subxf3";
91 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
92 Names[RTLIB::MUL_F32] = "__mulsf3";
93 Names[RTLIB::MUL_F64] = "__muldf3";
94 Names[RTLIB::MUL_F80] = "__mulxf3";
95 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
96 Names[RTLIB::DIV_F32] = "__divsf3";
97 Names[RTLIB::DIV_F64] = "__divdf3";
98 Names[RTLIB::DIV_F80] = "__divxf3";
99 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
100 Names[RTLIB::REM_F32] = "fmodf";
101 Names[RTLIB::REM_F64] = "fmod";
102 Names[RTLIB::REM_F80] = "fmodl";
103 Names[RTLIB::REM_PPCF128] = "fmodl";
104 Names[RTLIB::POWI_F32] = "__powisf2";
105 Names[RTLIB::POWI_F64] = "__powidf2";
106 Names[RTLIB::POWI_F80] = "__powixf2";
107 Names[RTLIB::POWI_PPCF128] = "__powitf2";
108 Names[RTLIB::SQRT_F32] = "sqrtf";
109 Names[RTLIB::SQRT_F64] = "sqrt";
110 Names[RTLIB::SQRT_F80] = "sqrtl";
111 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
112 Names[RTLIB::LOG_F32] = "logf";
113 Names[RTLIB::LOG_F64] = "log";
114 Names[RTLIB::LOG_F80] = "logl";
115 Names[RTLIB::LOG_PPCF128] = "logl";
116 Names[RTLIB::LOG2_F32] = "log2f";
117 Names[RTLIB::LOG2_F64] = "log2";
118 Names[RTLIB::LOG2_F80] = "log2l";
119 Names[RTLIB::LOG2_PPCF128] = "log2l";
120 Names[RTLIB::LOG10_F32] = "log10f";
121 Names[RTLIB::LOG10_F64] = "log10";
122 Names[RTLIB::LOG10_F80] = "log10l";
123 Names[RTLIB::LOG10_PPCF128] = "log10l";
124 Names[RTLIB::EXP_F32] = "expf";
125 Names[RTLIB::EXP_F64] = "exp";
126 Names[RTLIB::EXP_F80] = "expl";
127 Names[RTLIB::EXP_PPCF128] = "expl";
128 Names[RTLIB::EXP2_F32] = "exp2f";
129 Names[RTLIB::EXP2_F64] = "exp2";
130 Names[RTLIB::EXP2_F80] = "exp2l";
131 Names[RTLIB::EXP2_PPCF128] = "exp2l";
132 Names[RTLIB::SIN_F32] = "sinf";
133 Names[RTLIB::SIN_F64] = "sin";
134 Names[RTLIB::SIN_F80] = "sinl";
135 Names[RTLIB::SIN_PPCF128] = "sinl";
136 Names[RTLIB::COS_F32] = "cosf";
137 Names[RTLIB::COS_F64] = "cos";
138 Names[RTLIB::COS_F80] = "cosl";
139 Names[RTLIB::COS_PPCF128] = "cosl";
140 Names[RTLIB::POW_F32] = "powf";
141 Names[RTLIB::POW_F64] = "pow";
142 Names[RTLIB::POW_F80] = "powl";
143 Names[RTLIB::POW_PPCF128] = "powl";
144 Names[RTLIB::CEIL_F32] = "ceilf";
145 Names[RTLIB::CEIL_F64] = "ceil";
146 Names[RTLIB::CEIL_F80] = "ceill";
147 Names[RTLIB::CEIL_PPCF128] = "ceill";
148 Names[RTLIB::TRUNC_F32] = "truncf";
149 Names[RTLIB::TRUNC_F64] = "trunc";
150 Names[RTLIB::TRUNC_F80] = "truncl";
151 Names[RTLIB::TRUNC_PPCF128] = "truncl";
152 Names[RTLIB::RINT_F32] = "rintf";
153 Names[RTLIB::RINT_F64] = "rint";
154 Names[RTLIB::RINT_F80] = "rintl";
155 Names[RTLIB::RINT_PPCF128] = "rintl";
156 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
157 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
158 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
159 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
160 Names[RTLIB::FLOOR_F32] = "floorf";
161 Names[RTLIB::FLOOR_F64] = "floor";
162 Names[RTLIB::FLOOR_F80] = "floorl";
163 Names[RTLIB::FLOOR_PPCF128] = "floorl";
164 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
165 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
166 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
167 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
168 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
169 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
170 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
171 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
172 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
173 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
174 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
175 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
176 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
177 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
178 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
179 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
180 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
181 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
182 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
183 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
184 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
185 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
186 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
187 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
188 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
189 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
190 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
191 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
192 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
193 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
194 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
195 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
196 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
197 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
198 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
199 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
200 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
201 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
202 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
203 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
204 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
205 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
206 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
207 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
208 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
209 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
210 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
211 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
212 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
213 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
214 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
215 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
216 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
217 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
218 Names[RTLIB::OEQ_F32] = "__eqsf2";
219 Names[RTLIB::OEQ_F64] = "__eqdf2";
220 Names[RTLIB::UNE_F32] = "__nesf2";
221 Names[RTLIB::UNE_F64] = "__nedf2";
222 Names[RTLIB::OGE_F32] = "__gesf2";
223 Names[RTLIB::OGE_F64] = "__gedf2";
224 Names[RTLIB::OLT_F32] = "__ltsf2";
225 Names[RTLIB::OLT_F64] = "__ltdf2";
226 Names[RTLIB::OLE_F32] = "__lesf2";
227 Names[RTLIB::OLE_F64] = "__ledf2";
228 Names[RTLIB::OGT_F32] = "__gtsf2";
229 Names[RTLIB::OGT_F64] = "__gtdf2";
230 Names[RTLIB::UO_F32] = "__unordsf2";
231 Names[RTLIB::UO_F64] = "__unorddf2";
232 Names[RTLIB::O_F32] = "__unordsf2";
233 Names[RTLIB::O_F64] = "__unorddf2";
234 }
235
236 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
237 /// UNKNOWN_LIBCALL if there is none.
238 RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) {
239 if (OpVT == MVT::f32) {
240 if (RetVT == MVT::f64)
241 return FPEXT_F32_F64;
242 }
243 return UNKNOWN_LIBCALL;
244 }
245
246 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
247 /// UNKNOWN_LIBCALL if there is none.
248 RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) {
249 if (RetVT == MVT::f32) {
250 if (OpVT == MVT::f64)
251 return FPROUND_F64_F32;
252 if (OpVT == MVT::f80)
253 return FPROUND_F80_F32;
254 if (OpVT == MVT::ppcf128)
255 return FPROUND_PPCF128_F32;
256 } else if (RetVT == MVT::f64) {
257 if (OpVT == MVT::f80)
258 return FPROUND_F80_F64;
259 if (OpVT == MVT::ppcf128)
260 return FPROUND_PPCF128_F64;
261 }
262 return UNKNOWN_LIBCALL;
263 }
264
265 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
266 /// UNKNOWN_LIBCALL if there is none.
267 RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) {
268 if (OpVT == MVT::f32) {
269 if (RetVT == MVT::i32)
270 return FPTOSINT_F32_I32;
271 if (RetVT == MVT::i64)
272 return FPTOSINT_F32_I64;
273 if (RetVT == MVT::i128)
274 return FPTOSINT_F32_I128;
275 } else if (OpVT == MVT::f64) {
276 if (RetVT == MVT::i32)
277 return FPTOSINT_F64_I32;
278 if (RetVT == MVT::i64)
279 return FPTOSINT_F64_I64;
280 if (RetVT == MVT::i128)
281 return FPTOSINT_F64_I128;
282 } else if (OpVT == MVT::f80) {
283 if (RetVT == MVT::i32)
284 return FPTOSINT_F80_I32;
285 if (RetVT == MVT::i64)
286 return FPTOSINT_F80_I64;
287 if (RetVT == MVT::i128)
288 return FPTOSINT_F80_I128;
289 } else if (OpVT == MVT::ppcf128) {
290 if (RetVT == MVT::i32)
291 return FPTOSINT_PPCF128_I32;
292 if (RetVT == MVT::i64)
293 return FPTOSINT_PPCF128_I64;
294 if (RetVT == MVT::i128)
295 return FPTOSINT_PPCF128_I128;
296 }
297 return UNKNOWN_LIBCALL;
298 }
299
300 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
301 /// UNKNOWN_LIBCALL if there is none.
302 RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) {
303 if (OpVT == MVT::f32) {
304 if (RetVT == MVT::i32)
305 return FPTOUINT_F32_I32;
306 if (RetVT == MVT::i64)
307 return FPTOUINT_F32_I64;
308 if (RetVT == MVT::i128)
309 return FPTOUINT_F32_I128;
310 } else if (OpVT == MVT::f64) {
311 if (RetVT == MVT::i32)
312 return FPTOUINT_F64_I32;
313 if (RetVT == MVT::i64)
314 return FPTOUINT_F64_I64;
315 if (RetVT == MVT::i128)
316 return FPTOUINT_F64_I128;
317 } else if (OpVT == MVT::f80) {
318 if (RetVT == MVT::i32)
319 return FPTOUINT_F80_I32;
320 if (RetVT == MVT::i64)
321 return FPTOUINT_F80_I64;
322 if (RetVT == MVT::i128)
323 return FPTOUINT_F80_I128;
324 } else if (OpVT == MVT::ppcf128) {
325 if (RetVT == MVT::i32)
326 return FPTOUINT_PPCF128_I32;
327 if (RetVT == MVT::i64)
328 return FPTOUINT_PPCF128_I64;
329 if (RetVT == MVT::i128)
330 return FPTOUINT_PPCF128_I128;
331 }
332 return UNKNOWN_LIBCALL;
333 }
334
335 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
336 /// UNKNOWN_LIBCALL if there is none.
337 RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) {
338 if (OpVT == MVT::i32) {
339 if (RetVT == MVT::f32)
340 return SINTTOFP_I32_F32;
341 else if (RetVT == MVT::f64)
342 return SINTTOFP_I32_F64;
343 else if (RetVT == MVT::f80)
344 return SINTTOFP_I32_F80;
345 else if (RetVT == MVT::ppcf128)
346 return SINTTOFP_I32_PPCF128;
347 } else if (OpVT == MVT::i64) {
348 if (RetVT == MVT::f32)
349 return SINTTOFP_I64_F32;
350 else if (RetVT == MVT::f64)
351 return SINTTOFP_I64_F64;
352 else if (RetVT == MVT::f80)
353 return SINTTOFP_I64_F80;
354 else if (RetVT == MVT::ppcf128)
355 return SINTTOFP_I64_PPCF128;
356 } else if (OpVT == MVT::i128) {
357 if (RetVT == MVT::f32)
358 return SINTTOFP_I128_F32;
359 else if (RetVT == MVT::f64)
360 return SINTTOFP_I128_F64;
361 else if (RetVT == MVT::f80)
362 return SINTTOFP_I128_F80;
363 else if (RetVT == MVT::ppcf128)
364 return SINTTOFP_I128_PPCF128;
365 }
366 return UNKNOWN_LIBCALL;
367 }
368
369 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
370 /// UNKNOWN_LIBCALL if there is none.
371 RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) {
372 if (OpVT == MVT::i32) {
373 if (RetVT == MVT::f32)
374 return UINTTOFP_I32_F32;
375 else if (RetVT == MVT::f64)
376 return UINTTOFP_I32_F64;
377 else if (RetVT == MVT::f80)
378 return UINTTOFP_I32_F80;
379 else if (RetVT == MVT::ppcf128)
380 return UINTTOFP_I32_PPCF128;
381 } else if (OpVT == MVT::i64) {
382 if (RetVT == MVT::f32)
383 return UINTTOFP_I64_F32;
384 else if (RetVT == MVT::f64)
385 return UINTTOFP_I64_F64;
386 else if (RetVT == MVT::f80)
387 return UINTTOFP_I64_F80;
388 else if (RetVT == MVT::ppcf128)
389 return UINTTOFP_I64_PPCF128;
390 } else if (OpVT == MVT::i128) {
391 if (RetVT == MVT::f32)
392 return UINTTOFP_I128_F32;
393 else if (RetVT == MVT::f64)
394 return UINTTOFP_I128_F64;
395 else if (RetVT == MVT::f80)
396 return UINTTOFP_I128_F80;
397 else if (RetVT == MVT::ppcf128)
398 return UINTTOFP_I128_PPCF128;
399 }
400 return UNKNOWN_LIBCALL;
401 }
402
403 /// InitCmpLibcallCCs - Set default comparison libcall CC.
404 ///
405 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
406 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
407 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
408 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
409 CCs[RTLIB::UNE_F32] = ISD::SETNE;
410 CCs[RTLIB::UNE_F64] = ISD::SETNE;
411 CCs[RTLIB::OGE_F32] = ISD::SETGE;
412 CCs[RTLIB::OGE_F64] = ISD::SETGE;
413 CCs[RTLIB::OLT_F32] = ISD::SETLT;
414 CCs[RTLIB::OLT_F64] = ISD::SETLT;
415 CCs[RTLIB::OLE_F32] = ISD::SETLE;
416 CCs[RTLIB::OLE_F64] = ISD::SETLE;
417 CCs[RTLIB::OGT_F32] = ISD::SETGT;
418 CCs[RTLIB::OGT_F64] = ISD::SETGT;
419 CCs[RTLIB::UO_F32] = ISD::SETNE;
420 CCs[RTLIB::UO_F64] = ISD::SETNE;
421 CCs[RTLIB::O_F32] = ISD::SETEQ;
422 CCs[RTLIB::O_F64] = ISD::SETEQ;
423 }
424
425 TargetLowering::TargetLowering(TargetMachine &tm)
426 : TM(tm), TD(TM.getTargetData()) {
427 // All operations default to being supported.
428 memset(OpActions, 0, sizeof(OpActions));
429 memset(LoadExtActions, 0, sizeof(LoadExtActions));
430 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
431 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
432 memset(ConvertActions, 0, sizeof(ConvertActions));
433 memset(CondCodeActions, 0, sizeof(CondCodeActions));
434
435 // Set default actions for various operations.
436 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
437 // Default all indexed load / store to expand.
438 for (unsigned IM = (unsigned)ISD::PRE_INC;
439 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
440 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
441 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
442 }
443
444 // These operations default to expand.
445 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
446 }
447
448 // Most targets ignore the @llvm.prefetch intrinsic.
449 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
450
451 // ConstantFP nodes default to expand. Targets can either change this to
452 // Legal, in which case all fp constants are legal, or use addLegalFPImmediate
453 // to optimize expansions for certain constants.
454 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
455 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
456 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
457
458 // These library functions default to expand.
459 setOperationAction(ISD::FLOG , MVT::f64, Expand);
460 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
461 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
462 setOperationAction(ISD::FEXP , MVT::f64, Expand);
463 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
464 setOperationAction(ISD::FLOG , MVT::f32, Expand);
465 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
466 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
467 setOperationAction(ISD::FEXP , MVT::f32, Expand);
468 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
469
470 // Default ISD::TRAP to expand (which turns it into abort).
471 setOperationAction(ISD::TRAP, MVT::Other, Expand);
472
473 IsLittleEndian = TD->isLittleEndian();
474 UsesGlobalOffsetTable = false;
475 ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType());
476 ShiftAmtHandling = Undefined;
477 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
478 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
479 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
480 allowUnalignedMemoryAccesses = false;
481 UseUnderscoreSetJmp = false;
482 UseUnderscoreLongJmp = false;
483 SelectIsExpensive = false;
484 IntDivIsCheap = false;
485 Pow2DivIsCheap = false;
486 StackPointerRegisterToSaveRestore = 0;
487 ExceptionPointerRegister = 0;
488 ExceptionSelectorRegister = 0;
489 BooleanContents = UndefinedBooleanContent;
490 SchedPreferenceInfo = SchedulingForLatency;
491 JumpBufSize = 0;
492 JumpBufAlignment = 0;
493 IfCvtBlockSizeLimit = 2;
494 IfCvtDupBlockSizeLimit = 0;
495 PrefLoopAlignment = 0;
496
497 InitLibcallNames(LibcallRoutineNames);
498 InitCmpLibcallCCs(CmpLibcallCCs);
499
500 // Tell Legalize whether the assembler supports DEBUG_LOC.
501 const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
502 if (!TASM || !TASM->hasDotLocAndDotFile())
503 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
504 }
505
506 TargetLowering::~TargetLowering() {}
507
508 /// computeRegisterProperties - Once all of the register classes are added,
509 /// this allows us to compute derived properties we expose.
510 void TargetLowering::computeRegisterProperties() {
511 assert(MVT::LAST_VALUETYPE <= 32 &&
512 "Too many value types for ValueTypeActions to hold!");
513
514 // Everything defaults to needing one register.
515 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
516 NumRegistersForVT[i] = 1;
517 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
518 }
519 // ...except isVoid, which doesn't need any registers.
520 NumRegistersForVT[MVT::isVoid] = 0;
521
522 // Find the largest integer register class.
523 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
524 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
525 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
526
527 // Every integer value type larger than this largest register takes twice as
528 // many registers to represent as the previous ValueType.
529 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
530 MVT EVT = (MVT::SimpleValueType)ExpandedReg;
531 if (!EVT.isInteger())
532 break;
533 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
534 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
535 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
536 ValueTypeActions.setTypeAction(EVT, Expand);
537 }
538
539 // Inspect all of the ValueType's smaller than the largest integer
540 // register to see which ones need promotion.
541 unsigned LegalIntReg = LargestIntReg;
542 for (unsigned IntReg = LargestIntReg - 1;
543 IntReg >= (unsigned)MVT::i1; --IntReg) {
544 MVT IVT = (MVT::SimpleValueType)IntReg;
545 if (isTypeLegal(IVT)) {
546 LegalIntReg = IntReg;
547 } else {
548 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
549 (MVT::SimpleValueType)LegalIntReg;
550 ValueTypeActions.setTypeAction(IVT, Promote);
551 }
552 }
553
554 // ppcf128 type is really two f64's.
555 if (!isTypeLegal(MVT::ppcf128)) {
556 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
557 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
558 TransformToType[MVT::ppcf128] = MVT::f64;
559 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
560 }
561
562 // Decide how to handle f64. If the target does not have native f64 support,
563 // expand it to i64 and we will be generating soft float library calls.
564 if (!isTypeLegal(MVT::f64)) {
565 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
566 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
567 TransformToType[MVT::f64] = MVT::i64;
568 ValueTypeActions.setTypeAction(MVT::f64, Expand);
569 }
570
571 // Decide how to handle f32. If the target does not have native support for
572 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
573 if (!isTypeLegal(MVT::f32)) {
574 if (isTypeLegal(MVT::f64)) {
575 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
576 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
577 TransformToType[MVT::f32] = MVT::f64;
578 ValueTypeActions.setTypeAction(MVT::f32, Promote);
579 } else {
580 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
581 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
582 TransformToType[MVT::f32] = MVT::i32;
583 ValueTypeActions.setTypeAction(MVT::f32, Expand);
584 }
585 }
586
587 // Loop over all of the vector value types to see which need transformations.
588 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
589 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
590 MVT VT = (MVT::SimpleValueType)i;
591 if (!isTypeLegal(VT)) {
592 MVT IntermediateVT, RegisterVT;
593 unsigned NumIntermediates;
594 NumRegistersForVT[i] =
595 getVectorTypeBreakdown(VT,
596 IntermediateVT, NumIntermediates,
597 RegisterVT);
598 RegisterTypeForVT[i] = RegisterVT;
599
600 // Determine if there is a legal wider type.
601 bool IsLegalWiderType = false;
602 MVT EltVT = VT.getVectorElementType();
603 unsigned NElts = VT.getVectorNumElements();
604 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
605 MVT SVT = (MVT::SimpleValueType)nVT;
606 if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
607 SVT.getVectorNumElements() > NElts) {
608 TransformToType[i] = SVT;
609 ValueTypeActions.setTypeAction(VT, Promote);
610 IsLegalWiderType = true;
611 break;
612 }
613 }
614 if (!IsLegalWiderType) {
615 MVT NVT = VT.getPow2VectorType();
616 if (NVT == VT) {
617 // Type is already a power of 2. The default action is to split.
618 TransformToType[i] = MVT::Other;
619 ValueTypeActions.setTypeAction(VT, Expand);
620 } else {
621 TransformToType[i] = NVT;
622 ValueTypeActions.setTypeAction(VT, Promote);
623 }
624 }
625 }
626 }
627 }
628
629 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
630 return NULL;
631 }
632
633
634 MVT TargetLowering::getSetCCResultType(MVT VT) const {
635 return getValueType(TD->getIntPtrType());
636 }
637
638
639 /// getVectorTypeBreakdown - Vector types are broken down into some number of
640 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
641 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
642 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
643 ///
644 /// This method returns the number of registers needed, and the VT for each
645 /// register. It also returns the VT and quantity of the intermediate values
646 /// before they are promoted/expanded.
647 ///
648 unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
649 MVT &IntermediateVT,
650 unsigned &NumIntermediates,
651 MVT &RegisterVT) const {
652 // Figure out the right, legal destination reg to copy into.
653 unsigned NumElts = VT.getVectorNumElements();
654 MVT EltTy = VT.getVectorElementType();
655
656 unsigned NumVectorRegs = 1;
657
658 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
659 // could break down into LHS/RHS like LegalizeDAG does.
660 if (!isPowerOf2_32(NumElts)) {
661 NumVectorRegs = NumElts;
662 NumElts = 1;
663 }
664
665 // Divide the input until we get to a supported size. This will always
666 // end with a scalar if the target doesn't support vectors.
667 while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
668 NumElts >>= 1;
669 NumVectorRegs <<= 1;
670 }
671
672 NumIntermediates = NumVectorRegs;
673
674 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
675 if (!isTypeLegal(NewVT))
676 NewVT = EltTy;
677 IntermediateVT = NewVT;
678
679 MVT DestVT = getRegisterType(NewVT);
680 RegisterVT = DestVT;
681 if (DestVT.bitsLT(NewVT)) {
682 // Value is expanded, e.g. i64 -> i16.
683 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
684 } else {
685 // Otherwise, promotion or legal types use the same number of registers as
686 // the vector decimated to the appropriate level.
687 return NumVectorRegs;
688 }
689
690 return 1;
691 }
692
693 /// getWidenVectorType: given a vector type, returns the type to widen to
694 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
695 /// If there is no vector type that we want to widen to, returns MVT::Other
696 /// When and where to widen is target dependent based on the cost of
697 /// scalarizing vs using the wider vector type.
698 MVT TargetLowering::getWidenVectorType(MVT VT) const {
699 assert(VT.isVector());
700 if (isTypeLegal(VT))
701 return VT;
702
703 // Default is not to widen until moved to LegalizeTypes
704 return MVT::Other;
705 }
706
707 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
708 /// function arguments in the caller parameter area. This is the actual
709 /// alignment, not its logarithm.
710 unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
711 return TD->getCallFrameTypeAlignment(Ty);
712 }
713
714 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
715 SelectionDAG &DAG) const {
716 if (usesGlobalOffsetTable())
717 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
718 return Table;
719 }
720
721 bool
722 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
723 // Assume that everything is safe in static mode.
724 if (getTargetMachine().getRelocationModel() == Reloc::Static)
725 return true;
726
727 // In dynamic-no-pic mode, assume that known defined values are safe.
728 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
729 GA &&
730 !GA->getGlobal()->isDeclaration() &&
731 !GA->getGlobal()->isWeakForLinker())
732 return true;
733
734 // Otherwise assume nothing is safe.
735 return false;
736 }
737
738 //===----------------------------------------------------------------------===//
739 // Optimization Methods
740 //===----------------------------------------------------------------------===//
741
742 /// ShrinkDemandedConstant - Check to see if the specified operand of the
743 /// specified instruction is a constant integer. If so, check to see if there
744 /// are any bits set in the constant that are not demanded. If so, shrink the
745 /// constant and return true.
746 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
747 const APInt &Demanded) {
748 DebugLoc dl = Op.getDebugLoc();
749
750 // FIXME: ISD::SELECT, ISD::SELECT_CC
751 switch (Op.getOpcode()) {
752 default: break;
753 case ISD::XOR:
754 case ISD::AND:
755 case ISD::OR: {
756 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
757 if (!C) return false;
758
759 if (Op.getOpcode() == ISD::XOR &&
760 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
761 return false;
762
763 // if we can expand it to have all bits set, do it
764 if (C->getAPIntValue().intersects(~Demanded)) {
765 MVT VT = Op.getValueType();
766 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
767 DAG.getConstant(Demanded &
768 C->getAPIntValue(),
769 VT));
770 return CombineTo(Op, New);
771 }
772
773 break;
774 }
775 }
776
777 return false;
778 }
779
780 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
781 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
782 /// cast, but it could be generalized for targets with other types of
783 /// implicit widening casts.
784 bool
785 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
786 unsigned BitWidth,
787 const APInt &Demanded,
788 DebugLoc dl) {
789 assert(Op.getNumOperands() == 2 &&
790 "ShrinkDemandedOp only supports binary operators!");
791 assert(Op.getNode()->getNumValues() == 1 &&
792 "ShrinkDemandedOp only supports nodes with one result!");
793
794 // Don't do this if the node has another user, which may require the
795 // full value.
796 if (!Op.getNode()->hasOneUse())
797 return false;
798
799 // Search for the smallest integer type with free casts to and from
800 // Op's type. For expedience, just check power-of-2 integer types.
801 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
802 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
803 if (!isPowerOf2_32(SmallVTBits))
804 SmallVTBits = NextPowerOf2(SmallVTBits);
805 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
806 MVT SmallVT = MVT::getIntegerVT(SmallVTBits);
807 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
808 TLI.isZExtFree(SmallVT, Op.getValueType())) {
809 // We found a type with free casts.
810 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
811 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
812 Op.getNode()->getOperand(0)),
813 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
814 Op.getNode()->getOperand(1)));
815 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
816 return CombineTo(Op, Z);
817 }
818 }
819 return false;
820 }
821
822 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
823 /// DemandedMask bits of the result of Op are ever used downstream. If we can
824 /// use this information to simplify Op, create a new simplified DAG node and
825 /// return true, returning the original and new nodes in Old and New. Otherwise,
826 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
827 /// the expression (used to simplify the caller). The KnownZero/One bits may
828 /// only be accurate for those bits in the DemandedMask.
829 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
830 const APInt &DemandedMask,
831 APInt &KnownZero,
832 APInt &KnownOne,
833 TargetLoweringOpt &TLO,
834 unsigned Depth) const {
835 unsigned BitWidth = DemandedMask.getBitWidth();
836 assert(Op.getValueSizeInBits() == BitWidth &&
837 "Mask size mismatches value type size!");
838 APInt NewMask = DemandedMask;
839 DebugLoc dl = Op.getDebugLoc();
840
841 // Don't know anything.
842 KnownZero = KnownOne = APInt(BitWidth, 0);
843
844 // Other users may use these bits.
845 if (!Op.getNode()->hasOneUse()) {
846 if (Depth != 0) {
847 // If not at the root, Just compute the KnownZero/KnownOne bits to
848 // simplify things downstream.
849 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
850 return false;
851 }
852 // If this is the root being simplified, allow it to have multiple uses,
853 // just set the NewMask to all bits.
854 NewMask = APInt::getAllOnesValue(BitWidth);
855 } else if (DemandedMask == 0) {
856 // Not demanding any bits from Op.
857 if (Op.getOpcode() != ISD::UNDEF)
858 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
859 return false;
860 } else if (Depth == 6) { // Limit search depth.
861 return false;
862 }
863
864 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
865 switch (Op.getOpcode()) {
866 case ISD::Constant:
867 // We know all of the bits for a constant!
868 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
869 KnownZero = ~KnownOne & NewMask;
870 return false; // Don't fall through, will infinitely loop.
871 case ISD::AND:
872 // If the RHS is a constant, check to see if the LHS would be zero without
873 // using the bits from the RHS. Below, we use knowledge about the RHS to
874 // simplify the LHS, here we're using information from the LHS to simplify
875 // the RHS.
876 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
877 APInt LHSZero, LHSOne;
878 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
879 LHSZero, LHSOne, Depth+1);
880 // If the LHS already has zeros where RHSC does, this and is dead.
881 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
882 return TLO.CombineTo(Op, Op.getOperand(0));
883 // If any of the set bits in the RHS are known zero on the LHS, shrink
884 // the constant.
885 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
886 return true;
887 }
888
889 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
890 KnownOne, TLO, Depth+1))
891 return true;
892 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
893 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
894 KnownZero2, KnownOne2, TLO, Depth+1))
895 return true;
896 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
897
898 // If all of the demanded bits are known one on one side, return the other.
899 // These bits cannot contribute to the result of the 'and'.
900 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
901 return TLO.CombineTo(Op, Op.getOperand(0));
902 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
903 return TLO.CombineTo(Op, Op.getOperand(1));
904 // If all of the demanded bits in the inputs are known zeros, return zero.
905 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
906 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
907 // If the RHS is a constant, see if we can simplify it.
908 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
909 return true;
910 // If the operation can be done in a smaller type, do so.
911 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
912 return true;
913
914 // Output known-1 bits are only known if set in both the LHS & RHS.
915 KnownOne &= KnownOne2;
916 // Output known-0 are known to be clear if zero in either the LHS | RHS.
917 KnownZero |= KnownZero2;
918 break;
919 case ISD::OR:
920 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
921 KnownOne, TLO, Depth+1))
922 return true;
923 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
924 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
925 KnownZero2, KnownOne2, TLO, Depth+1))
926 return true;
927 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
928
929 // If all of the demanded bits are known zero on one side, return the other.
930 // These bits cannot contribute to the result of the 'or'.
931 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
932 return TLO.CombineTo(Op, Op.getOperand(0));
933 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
934 return TLO.CombineTo(Op, Op.getOperand(1));
935 // If all of the potentially set bits on one side are known to be set on
936 // the other side, just use the 'other' side.
937 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
938 return TLO.CombineTo(Op, Op.getOperand(0));
939 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
940 return TLO.CombineTo(Op, Op.getOperand(1));
941 // If the RHS is a constant, see if we can simplify it.
942 if (TLO.ShrinkDemandedConstant(Op, NewMask))
943 return true;
944 // If the operation can be done in a smaller type, do so.
945 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
946 return true;
947
948 // Output known-0 bits are only known if clear in both the LHS & RHS.
949 KnownZero &= KnownZero2;
950 // Output known-1 are known to be set if set in either the LHS | RHS.
951 KnownOne |= KnownOne2;
952 break;
953 case ISD::XOR:
954 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
955 KnownOne, TLO, Depth+1))
956 return true;
957 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
958 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
959 KnownOne2, TLO, Depth+1))
960 return true;
961 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
962
963 // If all of the demanded bits are known zero on one side, return the other.
964 // These bits cannot contribute to the result of the 'xor'.
965 if ((KnownZero & NewMask) == NewMask)
966 return TLO.CombineTo(Op, Op.getOperand(0));
967 if ((KnownZero2 & NewMask) == NewMask)
968 return TLO.CombineTo(Op, Op.getOperand(1));
969 // If the operation can be done in a smaller type, do so.
970 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
971 return true;
972
973 // If all of the unknown bits are known to be zero on one side or the other
974 // (but not both) turn this into an *inclusive* or.
975 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
976 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
977 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
978 Op.getOperand(0),
979 Op.getOperand(1)));
980
981 // Output known-0 bits are known if clear or set in both the LHS & RHS.
982 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
983 // Output known-1 are known to be set if set in only one of the LHS, RHS.
984 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
985
986 // If all of the demanded bits on one side are known, and all of the set
987 // bits on that side are also known to be set on the other side, turn this
988 // into an AND, as we know the bits will be cleared.
989 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
990 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
991 if ((KnownOne & KnownOne2) == KnownOne) {
992 MVT VT = Op.getValueType();
993 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
994 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
995 Op.getOperand(0), ANDC));
996 }
997 }
998
999 // If the RHS is a constant, see if we can simplify it.
1000 // for XOR, we prefer to force bits to 1 if they will make a -1.
1001 // if we can't force bits, try to shrink constant
1002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1003 APInt Expanded = C->getAPIntValue() | (~NewMask);
1004 // if we can expand it to have all bits set, do it
1005 if (Expanded.isAllOnesValue()) {
1006 if (Expanded != C->getAPIntValue()) {
1007 MVT VT = Op.getValueType();
1008 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1009 TLO.DAG.getConstant(Expanded, VT));
1010 return TLO.CombineTo(Op, New);
1011 }
1012 // if it already has all the bits set, nothing to change
1013 // but don't shrink either!
1014 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1015 return true;
1016 }
1017 }
1018
1019 KnownZero = KnownZeroOut;
1020 KnownOne = KnownOneOut;
1021 break;
1022 case ISD::SELECT:
1023 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1024 KnownOne, TLO, Depth+1))
1025 return true;
1026 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1027 KnownOne2, TLO, Depth+1))
1028 return true;
1029 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1030 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1031
1032 // If the operands are constants, see if we can simplify them.
1033 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1034 return true;
1035
1036 // Only known if known in both the LHS and RHS.
1037 KnownOne &= KnownOne2;
1038 KnownZero &= KnownZero2;
1039 break;
1040 case ISD::SELECT_CC:
1041 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1042 KnownOne, TLO, Depth+1))
1043 return true;
1044 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1045 KnownOne2, TLO, Depth+1))
1046 return true;
1047 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1048 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1049
1050 // If the operands are constants, see if we can simplify them.
1051 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1052 return true;
1053
1054 // Only known if known in both the LHS and RHS.
1055 KnownOne &= KnownOne2;
1056 KnownZero &= KnownZero2;
1057 break;
1058 case ISD::SHL:
1059 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1060 unsigned ShAmt = SA->getZExtValue();
1061 SDValue InOp = Op.getOperand(0);
1062
1063 // If the shift count is an invalid immediate, don't do anything.
1064 if (ShAmt >= BitWidth)
1065 break;
1066
1067 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1068 // single shift. We can do this if the bottom bits (which are shifted
1069 // out) are never demanded.
1070 if (InOp.getOpcode() == ISD::SRL &&
1071 isa<ConstantSDNode>(InOp.getOperand(1))) {
1072 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1073 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1074 unsigned Opc = ISD::SHL;
1075 int Diff = ShAmt-C1;
1076 if (Diff < 0) {
1077 Diff = -Diff;
1078 Opc = ISD::SRL;
1079 }
1080
1081 SDValue NewSA =
1082 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1083 MVT VT = Op.getValueType();
1084 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1085 InOp.getOperand(0), NewSA));
1086 }
1087 }
1088
1089 if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
1090 KnownZero, KnownOne, TLO, Depth+1))
1091 return true;
1092 KnownZero <<= SA->getZExtValue();
1093 KnownOne <<= SA->getZExtValue();
1094 // low bits known zero.
1095 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1096 }
1097 break;
1098 case ISD::SRL:
1099 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1100 MVT VT = Op.getValueType();
1101 unsigned ShAmt = SA->getZExtValue();
1102 unsigned VTSize = VT.getSizeInBits();
1103 SDValue InOp = Op.getOperand(0);
1104
1105 // If the shift count is an invalid immediate, don't do anything.
1106 if (ShAmt >= BitWidth)
1107 break;
1108
1109 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1110 // single shift. We can do this if the top bits (which are shifted out)
1111 // are never demanded.
1112 if (InOp.getOpcode() == ISD::SHL &&
1113 isa<ConstantSDNode>(InOp.getOperand(1))) {
1114 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1115 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1116 unsigned Opc = ISD::SRL;
1117 int Diff = ShAmt-C1;
1118 if (Diff < 0) {
1119 Diff = -Diff;
1120 Opc = ISD::SHL;
1121 }
1122
1123 SDValue NewSA =
1124 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1125 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1126 InOp.getOperand(0), NewSA));
1127 }
1128 }
1129
1130 // Compute the new bits that are at the top now.
1131 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1132 KnownZero, KnownOne, TLO, Depth+1))
1133 return true;
1134 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1135 KnownZero = KnownZero.lshr(ShAmt);
1136 KnownOne = KnownOne.lshr(ShAmt);
1137
1138 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1139 KnownZero |= HighBits; // High bits known zero.
1140 }
1141 break;
1142 case ISD::SRA:
1143 // If this is an arithmetic shift right and only the low-bit is set, we can
1144 // always convert this into a logical shr, even if the shift amount is
1145 // variable. The low bit of the shift cannot be an input sign bit unless
1146 // the shift amount is >= the size of the datatype, which is undefined.
1147 if (DemandedMask == 1)
1148 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1149 Op.getOperand(0), Op.getOperand(1)));
1150
1151 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1152 MVT VT = Op.getValueType();
1153 unsigned ShAmt = SA->getZExtValue();
1154
1155 // If the shift count is an invalid immediate, don't do anything.
1156 if (ShAmt >= BitWidth)
1157 break;
1158
1159 APInt InDemandedMask = (NewMask << ShAmt);
1160
1161 // If any of the demanded bits are produced by the sign extension, we also
1162 // demand the input sign bit.
1163 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1164 if (HighBits.intersects(NewMask))
1165 InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
1166
1167 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1168 KnownZero, KnownOne, TLO, Depth+1))
1169 return true;
1170 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1171 KnownZero = KnownZero.lshr(ShAmt);
1172 KnownOne = KnownOne.lshr(ShAmt);
1173
1174 // Handle the sign bit, adjusted to where it is now in the mask.
1175 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1176
1177 // If the input sign bit is known to be zero, or if none of the top bits
1178 // are demanded, turn this into an unsigned shift right.
1179 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1180 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1181 Op.getOperand(0),
1182 Op.getOperand(1)));
1183 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1184 KnownOne |= HighBits;
1185 }
1186 }
1187 break;
1188 case ISD::SIGN_EXTEND_INREG: {
1189 MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1190
1191 // Sign extension. Compute the demanded bits in the result that are not
1192 // present in the input.
1193 APInt NewBits = APInt::getHighBitsSet(BitWidth,
1194 BitWidth - EVT.getSizeInBits()) &
1195 NewMask;
1196
1197 // If none of the extended bits are demanded, eliminate the sextinreg.
1198 if (NewBits == 0)
1199 return TLO.CombineTo(Op, Op.getOperand(0));
1200
1201 APInt InSignBit = APInt::getSignBit(EVT.getSizeInBits());
1202 InSignBit.zext(BitWidth);
1203 APInt InputDemandedBits = APInt::getLowBitsSet(BitWidth,
1204 EVT.getSizeInBits()) &
1205 NewMask;
1206
1207 // Since the sign extended bits are demanded, we know that the sign
1208 // bit is demanded.
1209 InputDemandedBits |= InSignBit;
1210
1211 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1212 KnownZero, KnownOne, TLO, Depth+1))
1213 return true;
1214 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1215
1216 // If the sign bit of the input is known set or clear, then we know the
1217 // top bits of the result.
1218
1219 // If the input sign bit is known zero, convert this into a zero extension.
1220 if (KnownZero.intersects(InSignBit))
1221 return TLO.CombineTo(Op,
1222 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
1223
1224 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1225 KnownOne |= NewBits;
1226 KnownZero &= ~NewBits;
1227 } else { // Input sign bit unknown
1228 KnownZero &= ~NewBits;
1229 KnownOne &= ~NewBits;
1230 }
1231 break;
1232 }
1233 case ISD::ZERO_EXTEND: {
1234 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1235 APInt InMask = NewMask;
1236 InMask.trunc(OperandBitWidth);
1237
1238 // If none of the top bits are demanded, convert this into an any_extend.
1239 APInt NewBits =
1240 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1241 if (!NewBits.intersects(NewMask))
1242 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1243 Op.getValueType(),
1244 Op.getOperand(0)));
1245
1246 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1247 KnownZero, KnownOne, TLO, Depth+1))
1248 return true;
1249 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1250 KnownZero.zext(BitWidth);
1251 KnownOne.zext(BitWidth);
1252 KnownZero |= NewBits;
1253 break;
1254 }
1255 case ISD::SIGN_EXTEND: {
1256 MVT InVT = Op.getOperand(0).getValueType();
1257 unsigned InBits = InVT.getSizeInBits();
1258 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1259 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1260 APInt NewBits = ~InMask & NewMask;
1261
1262 // If none of the top bits are demanded, convert this into an any_extend.
1263 if (NewBits == 0)
1264 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1265 Op.getValueType(),
1266 Op.getOperand(0)));
1267
1268 // Since some of the sign extended bits are demanded, we know that the sign
1269 // bit is demanded.
1270 APInt InDemandedBits = InMask & NewMask;
1271 InDemandedBits |= InSignBit;
1272 InDemandedBits.trunc(InBits);
1273
1274 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1275 KnownOne, TLO, Depth+1))
1276 return true;
1277 KnownZero.zext(BitWidth);
1278 KnownOne.zext(BitWidth);
1279
1280 // If the sign bit is known zero, convert this to a zero extend.
1281 if (KnownZero.intersects(InSignBit))
1282 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1283 Op.getValueType(),
1284 Op.getOperand(0)));
1285
1286 // If the sign bit is known one, the top bits match.
1287 if (KnownOne.intersects(InSignBit)) {
1288 KnownOne |= NewBits;
1289 KnownZero &= ~NewBits;
1290 } else { // Otherwise, top bits aren't known.
1291 KnownOne &= ~NewBits;
1292 KnownZero &= ~NewBits;
1293 }
1294 break;
1295 }
1296 case ISD::ANY_EXTEND: {
1297 unsigned OperandBitWidth = Op.getOperand(0).getValueSizeInBits();
1298 APInt InMask = NewMask;
1299 InMask.trunc(OperandBitWidth);
1300 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1301 KnownZero, KnownOne, TLO, Depth+1))
1302 return true;
1303 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1304 KnownZero.zext(BitWidth);
1305 KnownOne.zext(BitWidth);
1306 break;
1307 }
1308 case ISD::TRUNCATE: {
1309 // Simplify the input, using demanded bit information, and compute the known
1310 // zero/one bits live out.
1311 APInt TruncMask = NewMask;
1312 TruncMask.zext(Op.getOperand(0).getValueSizeInBits());
1313 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1314 KnownZero, KnownOne, TLO, Depth+1))
1315 return true;
1316 KnownZero.trunc(BitWidth);
1317 KnownOne.trunc(BitWidth);
1318
1319 // If the input is only used by this truncate, see if we can shrink it based
1320 // on the known demanded bits.
1321 if (Op.getOperand(0).getNode()->hasOneUse()) {
1322 SDValue In = Op.getOperand(0);
1323 unsigned InBitWidth = In.getValueSizeInBits();
1324 switch (In.getOpcode()) {
1325 default: break;
1326 case ISD::SRL:
1327 // Shrink SRL by a constant if none of the high bits shifted in are
1328 // demanded.
1329 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
1330 APInt HighBits = APInt::getHighBitsSet(InBitWidth,
1331 InBitWidth - BitWidth);
1332 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1333 HighBits.trunc(BitWidth);
1334
1335 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1336 // None of the shifted in bits are needed. Add a truncate of the
1337 // shift input, then shift it.
1338 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1339 Op.getValueType(),
1340 In.getOperand(0));
1341 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1342 Op.getValueType(),
1343 NewTrunc,
1344 In.getOperand(1)));
1345 }
1346 }
1347 break;
1348 }
1349 }
1350
1351 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1352 break;
1353 }
1354 case ISD::AssertZext: {
1355 MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1356 APInt InMask = APInt::getLowBitsSet(BitWidth,
1357 VT.getSizeInBits());
1358 if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
1359 KnownZero, KnownOne, TLO, Depth+1))
1360 return true;
1361 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1362 KnownZero |= ~InMask & NewMask;
1363 break;
1364 }
1365 case ISD::BIT_CONVERT:
1366 #if 0
1367 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1368 // is demanded, turn this into a FGETSIGN.
1369 if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) &&
1370 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1371 !MVT::isVector(Op.getOperand(0).getValueType())) {
1372 // Only do this xform if FGETSIGN is valid or if before legalize.
1373 if (!TLO.AfterLegalize ||
1374 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1375 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1376 // place. We expect the SHL to be eliminated by other optimizations.
1377 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
1378 Op.getOperand(0));
1379 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1380 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
1381 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1382 Sign, ShAmt));
1383 }
1384 }
1385 #endif
1386 break;
1387 case ISD::ADD:
1388 case ISD::MUL:
1389 case ISD::SUB: {
1390 // Add, Sub, and Mul don't demand any bits in positions beyond that
1391 // of the highest bit demanded of them.
1392 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1393 BitWidth - NewMask.countLeadingZeros());
1394 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1395 KnownOne2, TLO, Depth+1))
1396 return true;
1397 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1398 KnownOne2, TLO, Depth+1))
1399 return true;
1400 // See if the operation should be performed at a smaller bit width.
1401 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1402 return true;
1403 }
1404 // FALL THROUGH
1405 default:
1406 // Just use ComputeMaskedBits to compute output bits.
1407 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
1408 break;
1409 }
1410
1411 // If we know the value of all of the demanded bits, return this as a
1412 // constant.
1413 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1414 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1415
1416 return false;
1417 }
1418
1419 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1420 /// in Mask are known to be either zero or one and return them in the
1421 /// KnownZero/KnownOne bitsets.
1422 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1423 const APInt &Mask,
1424 APInt &KnownZero,
1425 APInt &KnownOne,
1426 const SelectionDAG &DAG,
1427 unsigned Depth) const {
1428 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1429 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1430 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1431 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1432 "Should use MaskedValueIsZero if you don't know whether Op"
1433 " is a target node!");
1434 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1435 }
1436
1437 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1438 /// targets that want to expose additional information about sign bits to the
1439 /// DAG Combiner.
1440 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1441 unsigned Depth) const {
1442 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1443 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1444 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1445 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1446 "Should use ComputeNumSignBits if you don't know whether Op"
1447 " is a target node!");
1448 return 1;
1449 }
1450
1451 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1452 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1453 /// determine which bit is set.
1454 ///
1455 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1456 // A left-shift of a constant one will have exactly one bit set, because
1457 // shifting the bit off the end is undefined.
1458 if (Val.getOpcode() == ISD::SHL)
1459 if (ConstantSDNode *C =
1460 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1461 if (C->getAPIntValue() == 1)
1462 return true;
1463
1464 // Similarly, a right-shift of a constant sign-bit will have exactly
1465 // one bit set.
1466 if (Val.getOpcode() == ISD::SRL)
1467 if (ConstantSDNode *C =
1468 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1469 if (C->getAPIntValue().isSignBit())
1470 return true;
1471
1472 // More could be done here, though the above checks are enough
1473 // to handle some common cases.
1474
1475 // Fall back to ComputeMaskedBits to catch other known cases.
1476 MVT OpVT = Val.getValueType();
1477 unsigned BitWidth = OpVT.getSizeInBits();
1478 APInt Mask = APInt::getAllOnesValue(BitWidth);
1479 APInt KnownZero, KnownOne;
1480 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
1481 return (KnownZero.countPopulation() == BitWidth - 1) &&
1482 (KnownOne.countPopulation() == 1);
1483 }
1484
1485 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1486 /// and cc. If it is unable to simplify it, return a null SDValue.
1487 SDValue
1488 TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
1489 ISD::CondCode Cond, bool foldBooleans,
1490 DAGCombinerInfo &DCI, DebugLoc dl) const {
1491 SelectionDAG &DAG = DCI.DAG;
1492
1493 // These setcc operations always fold.
1494 switch (Cond) {
1495 default: break;
1496 case ISD::SETFALSE:
1497 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1498 case ISD::SETTRUE:
1499 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1500 }
1501
1502 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1503 const APInt &C1 = N1C->getAPIntValue();
1504 if (isa<ConstantSDNode>(N0.getNode())) {
1505 return DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1506 } else {
1507 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1508 // equality comparison, then we're just comparing whether X itself is
1509 // zero.
1510 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1511 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1512 N0.getOperand(1).getOpcode() == ISD::Constant) {
1513 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1514 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1515 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1516 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1517 // (srl (ctlz x), 5) == 0 -> X != 0
1518 // (srl (ctlz x), 5) != 1 -> X != 0
1519 Cond = ISD::SETNE;
1520 } else {
1521 // (srl (ctlz x), 5) != 0 -> X == 0
1522 // (srl (ctlz x), 5) == 1 -> X == 0
1523 Cond = ISD::SETEQ;
1524 }
1525 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1526 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1527 Zero, Cond);
1528 }
1529 }
1530
1531 // If the LHS is '(and load, const)', the RHS is 0,
1532 // the test is for equality or unsigned, and all 1 bits of the const are
1533 // in the same partial word, see if we can shorten the load.
1534 if (DCI.isBeforeLegalize() &&
1535 N0.getOpcode() == ISD::AND && C1 == 0 &&
1536 N0.getNode()->hasOneUse() &&
1537 isa<LoadSDNode>(N0.getOperand(0)) &&
1538 N0.getOperand(0).getNode()->hasOneUse() &&
1539 isa<ConstantSDNode>(N0.getOperand(1))) {
1540 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1541 uint64_t bestMask = 0;
1542 unsigned bestWidth = 0, bestOffset = 0;
1543 if (!Lod->isVolatile() && Lod->isUnindexed() &&
1544 // FIXME: This uses getZExtValue() below so it only works on i64 and
1545 // below.
1546 N0.getValueType().getSizeInBits() <= 64) {
1547 unsigned origWidth = N0.getValueType().getSizeInBits();
1548 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1549 // 8 bits, but have to be careful...
1550 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1551 origWidth = Lod->getMemoryVT().getSizeInBits();
1552 uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
1553 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1554 uint64_t newMask = (1ULL << width) - 1;
1555 for (unsigned offset=0; offset<origWidth/width; offset++) {
1556 if ((newMask & Mask) == Mask) {
1557 if (!TD->isLittleEndian())
1558 bestOffset = (origWidth/width - offset - 1) * (width/8);
1559 else
1560 bestOffset = (uint64_t)offset * (width/8);
1561 bestMask = Mask >> (offset * (width/8) * 8);
1562 bestWidth = width;
1563 break;
1564 }
1565 newMask = newMask << width;
1566 }
1567 }
1568 }
1569 if (bestWidth) {
1570 MVT newVT = MVT::getIntegerVT(bestWidth);
1571 if (newVT.isRound()) {
1572 MVT PtrType = Lod->getOperand(1).getValueType();
1573 SDValue Ptr = Lod->getBasePtr();
1574 if (bestOffset != 0)
1575 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1576 DAG.getConstant(bestOffset, PtrType));
1577 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1578 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1579 Lod->getSrcValue(),
1580 Lod->getSrcValueOffset() + bestOffset,
1581 false, NewAlign);
1582 return DAG.getSetCC(dl, VT,
1583 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1584 DAG.getConstant(bestMask, newVT)),
1585 DAG.getConstant(0LL, newVT), Cond);
1586 }
1587 }
1588 }
1589
1590 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1591 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1592 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1593
1594 // If the comparison constant has bits in the upper part, the
1595 // zero-extended value could never match.
1596 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1597 C1.getBitWidth() - InSize))) {
1598 switch (Cond) {
1599 case ISD::SETUGT:
1600 case ISD::SETUGE:
1601 case ISD::SETEQ: return DAG.getConstant(0, VT);
1602 case ISD::SETULT:
1603 case ISD::SETULE:
1604 case ISD::SETNE: return DAG.getConstant(1, VT);
1605 case ISD::SETGT:
1606 case ISD::SETGE:
1607 // True if the sign bit of C1 is set.
1608 return DAG.getConstant(C1.isNegative(), VT);
1609 case ISD::SETLT:
1610 case ISD::SETLE:
1611 // True if the sign bit of C1 isn't set.
1612 return DAG.getConstant(C1.isNonNegative(), VT);
1613 default:
1614 break;
1615 }
1616 }
1617
1618 // Otherwise, we can perform the comparison with the low bits.
1619 switch (Cond) {
1620 case ISD::SETEQ:
1621 case ISD::SETNE:
1622 case ISD::SETUGT:
1623 case ISD::SETUGE:
1624 case ISD::SETULT:
1625 case ISD::SETULE:
1626 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1627 DAG.getConstant(APInt(C1).trunc(InSize),
1628 N0.getOperand(0).getValueType()),
1629 Cond);
1630 default:
1631 break; // todo, be more careful with signed comparisons
1632 }
1633 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1634 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1635 MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1636 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1637 MVT ExtDstTy = N0.getValueType();
1638 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1639
1640 // If the extended part has any inconsistent bits, it cannot ever
1641 // compare equal. In other words, they have to be all ones or all
1642 // zeros.
1643 APInt ExtBits =
1644 APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
1645 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1646 return DAG.getConstant(Cond == ISD::SETNE, VT);
1647
1648 SDValue ZextOp;
1649 MVT Op0Ty = N0.getOperand(0).getValueType();
1650 if (Op0Ty == ExtSrcTy) {
1651 ZextOp = N0.getOperand(0);
1652 } else {
1653 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1654 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1655 DAG.getConstant(Imm, Op0Ty));
1656 }
1657 if (!DCI.isCalledByLegalizer())
1658 DCI.AddToWorklist(ZextOp.getNode());
1659 // Otherwise, make this a use of a zext.
1660 return DAG.getSetCC(dl, VT, ZextOp,
1661 DAG.getConstant(C1 & APInt::getLowBitsSet(
1662 ExtDstTyBits,
1663 ExtSrcTyBits),
1664 ExtDstTy),
1665 Cond);
1666 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1667 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1668
1669 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1670 if (N0.getOpcode() == ISD::SETCC) {
1671 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getZExtValue() != 1);
1672 if (TrueWhenTrue)
1673 return N0;
1674
1675 // Invert the condition.
1676 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1677 CC = ISD::getSetCCInverse(CC,
1678 N0.getOperand(0).getValueType().isInteger());
1679 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1680 }
1681
1682 if ((N0.getOpcode() == ISD::XOR ||
1683 (N0.getOpcode() == ISD::AND &&
1684 N0.getOperand(0).getOpcode() == ISD::XOR &&
1685 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1686 isa<ConstantSDNode>(N0.getOperand(1)) &&
1687 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1688 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1689 // can only do this if the top bits are known zero.
1690 unsigned BitWidth = N0.getValueSizeInBits();
1691 if (DAG.MaskedValueIsZero(N0,
1692 APInt::getHighBitsSet(BitWidth,
1693 BitWidth-1))) {
1694 // Okay, get the un-inverted input value.
1695 SDValue Val;
1696 if (N0.getOpcode() == ISD::XOR)
1697 Val = N0.getOperand(0);
1698 else {
1699 assert(N0.getOpcode() == ISD::AND &&
1700 N0.getOperand(0).getOpcode() == ISD::XOR);
1701 // ((X^1)&1)^1 -> X & 1
1702 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1703 N0.getOperand(0).getOperand(0),
1704 N0.getOperand(1));
1705 }
1706 return DAG.getSetCC(dl, VT, Val, N1,
1707 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1708 }
1709 }
1710 }
1711
1712 APInt MinVal, MaxVal;
1713 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1714 if (ISD::isSignedIntSetCC(Cond)) {
1715 MinVal = APInt::getSignedMinValue(OperandBitSize);
1716 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1717 } else {
1718 MinVal = APInt::getMinValue(OperandBitSize);
1719 MaxVal = APInt::getMaxValue(OperandBitSize);
1720 }
1721
1722 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1723 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1724 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1725 // X >= C0 --> X > (C0-1)
1726 return DAG.getSetCC(dl, VT, N0,
1727 DAG.getConstant(C1-1, N1.getValueType()),
1728 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1729 }
1730
1731 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1732 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1733 // X <= C0 --> X < (C0+1)
1734 return DAG.getSetCC(dl, VT, N0,
1735 DAG.getConstant(C1+1, N1.getValueType()),
1736 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1737 }
1738
1739 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1740 return DAG.getConstant(0, VT); // X < MIN --> false
1741 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1742 return DAG.getConstant(1, VT); // X >= MIN --> true
1743 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1744 return DAG.getConstant(0, VT); // X > MAX --> false
1745 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1746 return DAG.getConstant(1, VT); // X <= MAX --> true
1747
1748 // Canonicalize setgt X, Min --> setne X, Min
1749 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1750 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1751 // Canonicalize setlt X, Max --> setne X, Max
1752 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1753 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1754
1755 // If we have setult X, 1, turn it into seteq X, 0
1756 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1757 return DAG.getSetCC(dl, VT, N0,
1758 DAG.getConstant(MinVal, N0.getValueType()),
1759 ISD::SETEQ);
1760 // If we have setugt X, Max-1, turn it into seteq X, Max
1761 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1762 return DAG.getSetCC(dl, VT, N0,
1763 DAG.getConstant(MaxVal, N0.getValueType()),
1764 ISD::SETEQ);
1765
1766 // If we have "setcc X, C0", check to see if we can shrink the immediate
1767 // by changing cc.
1768
1769 // SETUGT X, SINTMAX -> SETLT X, 0
1770 if (Cond == ISD::SETUGT &&
1771 C1 == APInt::getSignedMaxValue(OperandBitSize))
1772 return DAG.getSetCC(dl, VT, N0,
1773 DAG.getConstant(0, N1.getValueType()),
1774 ISD::SETLT);
1775
1776 // SETULT X, SINTMIN -> SETGT X, -1
1777 if (Cond == ISD::SETULT &&
1778 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1779 SDValue ConstMinusOne =
1780 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
1781 N1.getValueType());
1782 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1783 }
1784
1785 // Fold bit comparisons when we can.
1786 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1787 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1788 if (ConstantSDNode *AndRHS =
1789 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1790 MVT ShiftTy = DCI.isBeforeLegalize() ?
1791 getPointerTy() : getShiftAmountTy();
1792 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1793 // Perform the xform if the AND RHS is a single bit.
1794 if (isPowerOf2_64(AndRHS->getZExtValue())) {
1795 return DAG.getNode(ISD::SRL, dl, VT, N0,
1796 DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
1797 ShiftTy));
1798 }
1799 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
1800 // (X & 8) == 8 --> (X & 8) >> 3
1801 // Perform the xform if C1 is a single bit.
1802 if (C1.isPowerOf2()) {
1803 return DAG.getNode(ISD::SRL, dl, VT, N0,
1804 DAG.getConstant(C1.logBase2(), ShiftTy));
1805 }
1806 }
1807 }
1808 }
1809 } else if (isa<ConstantSDNode>(N0.getNode())) {
1810 // Ensure that the constant occurs on the RHS.
1811 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1812 }
1813
1814 if (isa<ConstantFPSDNode>(N0.getNode())) {
1815 // Constant fold or commute setcc.
1816 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1817 if (O.getNode()) return O;
1818 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1819 // If the RHS of an FP comparison is a constant, simplify it away in
1820 // some cases.
1821 if (CFP->getValueAPF().isNaN()) {
1822 // If an operand is known to be a nan, we can fold it.
1823 switch (ISD::getUnorderedFlavor(Cond)) {
1824 default: assert(0 && "Unknown flavor!");
1825 case 0: // Known false.
1826 return DAG.getConstant(0, VT);
1827 case 1: // Known true.
1828 return DAG.getConstant(1, VT);
1829 case 2: // Undefined.
1830 return DAG.getUNDEF(VT);
1831 }
1832 }
1833
1834 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1835 // constant if knowing that the operand is non-nan is enough. We prefer to
1836 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1837 // materialize 0.0.
1838 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1839 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1840 }
1841
1842 if (N0 == N1) {
1843 // We can always fold X == X for integer setcc's.
1844 if (N0.getValueType().isInteger())
1845 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1846 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1847 if (UOF == 2) // FP operators that are undefined on NaNs.
1848 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1849 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1850 return DAG.getConstant(UOF, VT);
1851 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1852 // if it is not already.
1853 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1854 if (NewCond != Cond)
1855 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1856 }
1857
1858 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1859 N0.getValueType().isInteger()) {
1860 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1861 N0.getOpcode() == ISD::XOR) {
1862 // Simplify (X+Y) == (X+Z) --> Y == Z
1863 if (N0.getOpcode() == N1.getOpcode()) {
1864 if (N0.getOperand(0) == N1.getOperand(0))
1865 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1866 if (N0.getOperand(1) == N1.getOperand(1))
1867 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1868 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1869 // If X op Y == Y op X, try other combinations.
1870 if (N0.getOperand(0) == N1.getOperand(1))
1871 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1872 Cond);
1873 if (N0.getOperand(1) == N1.getOperand(0))
1874 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1875 Cond);
1876 }
1877 }
1878
1879 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1880 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1881 // Turn (X+C1) == C2 --> X == C2-C1
1882 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1883 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1884 DAG.getConstant(RHSC->getAPIntValue()-
1885 LHSR->getAPIntValue(),
1886 N0.getValueType()), Cond);
1887 }
1888
1889 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1890 if (N0.getOpcode() == ISD::XOR)
1891 // If we know that all of the inverted bits are zero, don't bother
1892 // performing the inversion.
1893 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1894 return
1895 DAG.getSetCC(dl, VT, N0.getOperand(0),
1896 DAG.getConstant(LHSR->getAPIntValue() ^
1897 RHSC->getAPIntValue(),
1898 N0.getValueType()),
1899 Cond);
1900 }
1901
1902 // Turn (C1-X) == C2 --> X == C1-C2
1903 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1904 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1905 return
1906 DAG.getSetCC(dl, VT, N0.getOperand(1),
1907 DAG.getConstant(SUBC->getAPIntValue() -
1908 RHSC->getAPIntValue(),
1909 N0.getValueType()),
1910 Cond);
1911 }
1912 }
1913 }
1914
1915 // Simplify (X+Z) == X --> Z == 0
1916 if (N0.getOperand(0) == N1)
1917 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1918 DAG.getConstant(0, N0.getValueType()), Cond);
1919 if (N0.getOperand(1) == N1) {
1920 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1921 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1922 DAG.getConstant(0, N0.getValueType()), Cond);
1923 else if (N0.getNode()->hasOneUse()) {
1924 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1925 // (Z-X) == X --> Z == X<<1
1926 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
1927 N1,
1928 DAG.getConstant(1, getShiftAmountTy()));
1929 if (!DCI.isCalledByLegalizer())
1930 DCI.AddToWorklist(SH.getNode());
1931 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1932 }
1933 }
1934 }
1935
1936 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1937 N1.getOpcode() == ISD::XOR) {
1938 // Simplify X == (X+Z) --> Z == 0
1939 if (N1.getOperand(0) == N0) {
1940 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1941 DAG.getConstant(0, N1.getValueType()), Cond);
1942 } else if (N1.getOperand(1) == N0) {
1943 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1944 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1945 DAG.getConstant(0, N1.getValueType()), Cond);
1946 } else if (N1.getNode()->hasOneUse()) {
1947 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1948 // X == (Z-X) --> X<<1 == Z
1949 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1950 DAG.getConstant(1, getShiftAmountTy()));
1951 if (!DCI.isCalledByLegalizer())
1952 DCI.AddToWorklist(SH.getNode());
1953 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1954 }
1955 }
1956 }
1957
1958 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1959 // Note that where y is variable and is known to have at most
1960 // one bit set (for example, if it is z&1) we cannot do this;
1961 // the expressions are not equivalent when y==0.
1962 if (N0.getOpcode() == ISD::AND)
1963 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1964 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1965 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1966 SDValue Zero = DAG.getConstant(0, N1.getValueType());
1967 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1968 }
1969 }
1970 if (N1.getOpcode() == ISD::AND)
1971 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1972 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1973 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1974 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1975 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1976 }
1977 }
1978 }
1979
1980 // Fold away ALL boolean setcc's.
1981 SDValue Temp;
1982 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1983 switch (Cond) {
1984 default: assert(0 && "Unknown integer setcc!");
1985 case ISD::SETEQ: // X == Y -> ~(X^Y)
1986 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1987 N0 = DAG.getNOT(dl, Temp, MVT::i1);
1988 if (!DCI.isCalledByLegalizer())
1989 DCI.AddToWorklist(Temp.getNode());
1990 break;
1991 case ISD::SETNE: // X != Y --> (X^Y)
1992 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1993 break;
1994 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1995 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1996 Temp = DAG.getNOT(dl, N0, MVT::i1);
1997 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1998 if (!DCI.isCalledByLegalizer())
1999 DCI.AddToWorklist(Temp.getNode());
2000 break;
2001 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2002 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2003 Temp = DAG.getNOT(dl, N1, MVT::i1);
2004 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2005 if (!DCI.isCalledByLegalizer())
2006 DCI.AddToWorklist(Temp.getNode());
2007 break;
2008 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2009 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2010 Temp = DAG.getNOT(dl, N0, MVT::i1);
2011 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2012 if (!DCI.isCalledByLegalizer())
2013 DCI.AddToWorklist(Temp.getNode());
2014 break;
2015 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2016 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2017 Temp = DAG.getNOT(dl, N1, MVT::i1);
2018 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2019 break;
2020 }
2021 if (VT != MVT::i1) {
2022 if (!DCI.isCalledByLegalizer())
2023 DCI.AddToWorklist(N0.getNode());
2024 // FIXME: If running after legalize, we probably can't do this.
2025 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2026 }
2027 return N0;
2028 }
2029
2030 // Could not fold it.
2031 return SDValue();
2032 }
2033
2034 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2035 /// node is a GlobalAddress + offset.
2036 bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
2037 int64_t &Offset) const {
2038 if (isa<GlobalAddressSDNode>(N)) {
2039 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2040 GA = GASD->getGlobal();
2041 Offset += GASD->getOffset();
2042 return true;
2043 }
2044
2045 if (N->getOpcode() == ISD::ADD) {
2046 SDValue N1 = N->getOperand(0);
2047 SDValue N2 = N->getOperand(1);
2048 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2049 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2050 if (V) {
2051 Offset += V->getSExtValue();
2052 return true;
2053 }
2054 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2055 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2056 if (V) {
2057 Offset += V->getSExtValue();
2058 return true;
2059 }
2060 }
2061 }
2062 return false;
2063 }
2064
2065
2066 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
2067 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
2068 /// location that the 'Base' load is loading from.
2069 bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
2070 unsigned Bytes, int Dist,
2071 const MachineFrameInfo *MFI) const {
2072 if (LD->getOperand(0).getNode() != Base->getOperand(0).getNode())
2073 return false;
2074 MVT VT = LD->getValueType(0);
2075 if (VT.getSizeInBits() / 8 != Bytes)
2076 return false;
2077
2078 SDValue Loc = LD->getOperand(1);
2079 SDValue BaseLoc = Base->getOperand(1);
2080 if (Loc.getOpcode() == ISD::FrameIndex) {
2081 if (BaseLoc.getOpcode() != ISD::FrameIndex)
2082 return false;
2083 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
2084 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
2085 int FS = MFI->getObjectSize(FI);
2086 int BFS = MFI->getObjectSize(BFI);
2087 if (FS != BFS || FS != (int)Bytes) return false;
2088 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
2089 }
2090
2091 GlobalValue *GV1 = NULL;
2092 GlobalValue *GV2 = NULL;
2093 int64_t Offset1 = 0;
2094 int64_t Offset2 = 0;
2095 bool isGA1 = isGAPlusOffset(Loc.getNode(), GV1, Offset1);
2096 bool isGA2 = isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
2097 if (isGA1 && isGA2 && GV1 == GV2)
2098 return Offset1 == (Offset2 + Dist*Bytes);
2099 return false;
2100 }
2101
2102
2103 SDValue TargetLowering::
2104 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2105 // Default implementation: no optimization.
2106 return SDValue();
2107 }
2108
2109 //===----------------------------------------------------------------------===//
2110 // Inline Assembler Implementation Methods
2111 //===----------------------------------------------------------------------===//
2112
2113
2114 TargetLowering::ConstraintType
2115 TargetLowering::getConstraintType(const std::string &Constraint) const {
2116 // FIXME: lots more standard ones to handle.
2117 if (Constraint.size() == 1) {
2118 switch (Constraint[0]) {
2119 default: break;
2120 case 'r': return C_RegisterClass;
2121 case 'm': // memory
2122 case 'o': // offsetable
2123 case 'V': // not offsetable
2124 return C_Memory;
2125 case 'i': // Simple Integer or Relocatable Constant
2126 case 'n': // Simple Integer
2127 case 's': // Relocatable Constant
2128 case 'X': // Allow ANY value.
2129 case 'I': // Target registers.
2130 case 'J':
2131 case 'K':
2132 case 'L':
2133 case 'M':
2134 case 'N':
2135 case 'O':
2136 case 'P':
2137 return C_Other;
2138 }
2139 }
2140
2141 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2142 Constraint[Constraint.size()-1] == '}')
2143 return C_Register;
2144 return C_Unknown;
2145 }
2146
2147 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2148 /// with another that has more specific requirements based on the type of the
2149 /// corresponding operand.
2150 const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
2151 if (ConstraintVT.isInteger())
2152 return "r";
2153 if (ConstraintVT.isFloatingPoint())
2154 return "f"; // works for many targets
2155 return 0;
2156 }
2157
2158 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2159 /// vector. If it is invalid, don't add anything to Ops.
2160 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2161 char ConstraintLetter,
2162 bool hasMemory,
2163 std::vector<SDValue> &Ops,
2164 SelectionDAG &DAG) const {
2165 switch (ConstraintLetter) {
2166 default: break;
2167 case 'X': // Allows any operand; labels (basic block) use this.
2168 if (Op.getOpcode() == ISD::BasicBlock) {
2169 Ops.push_back(Op);
2170 return;
2171 }
2172 // fall through
2173 case 'i': // Simple Integer or Relocatable Constant
2174 case 'n': // Simple Integer
2175 case 's': { // Relocatable Constant
2176 // These operands are interested in values of the form (GV+C), where C may
2177 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2178 // is possible and fine if either GV or C are missing.
2179 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2180 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2181
2182 // If we have "(add GV, C)", pull out GV/C
2183 if (Op.getOpcode() == ISD::ADD) {
2184 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2185 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2186 if (C == 0 || GA == 0) {
2187 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2188 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2189 }
2190 if (C == 0 || GA == 0)
2191 C = 0, GA = 0;
2192 }
2193
2194 // If we find a valid operand, map to the TargetXXX version so that the
2195 // value itself doesn't get selected.
2196 if (GA) { // Either &GV or &GV+C
2197 if (ConstraintLetter != 'n') {
2198 int64_t Offs = GA->getOffset();
2199 if (C) Offs += C->getZExtValue();
2200 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2201 Op.getValueType(), Offs));
2202 return;
2203 }
2204 }
2205 if (C) { // just C, no GV.
2206 // Simple constants are not allowed for 's'.
2207 if (ConstraintLetter != 's') {
2208 // gcc prints these as sign extended. Sign extend value to 64 bits
2209 // now; without this it would get ZExt'd later in
2210 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2211 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2212 MVT::i64));
2213 return;
2214 }
2215 }
2216 break;
2217 }
2218 }
2219 }
2220
2221 std::vector<unsigned> TargetLowering::
2222 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2223 MVT VT) const {
2224 return std::vector<unsigned>();
2225 }
2226
2227
2228 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2229 getRegForInlineAsmConstraint(const std::string &Constraint,
2230 MVT VT) const {
2231 if (Constraint[0] != '{')
2232 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2233 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2234
2235 // Remove the braces from around the name.
2236 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
2237
2238 // Figure out which register class contains this reg.
2239 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2240 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2241 E = RI->regclass_end(); RCI != E; ++RCI) {
2242 const TargetRegisterClass *RC = *RCI;
2243
2244 // If none of the the value types for this register class are valid, we
2245 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2246 bool isLegal = false;
2247 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2248 I != E; ++I) {
2249 if (isTypeLegal(*I)) {
2250 isLegal = true;
2251 break;
2252 }
2253 }
2254
2255 if (!isLegal) continue;
2256
2257 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2258 I != E; ++I) {
2259 if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
2260 return std::make_pair(*I, RC);
2261 }
2262 }
2263
2264 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
2265 }
2266
2267 //===----------------------------------------------------------------------===//
2268 // Constraint Selection.
2269
2270 /// isMatchingInputConstraint - Return true of this is an input operand that is
2271 /// a matching constraint like "4".
2272 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2273 assert(!ConstraintCode.empty() && "No known constraint!");
2274 return isdigit(ConstraintCode[0]);
2275 }
2276
2277 /// getMatchedOperand - If this is an input matching constraint, this method
2278 /// returns the output operand it matches.
2279 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2280 assert(!ConstraintCode.empty() && "No known constraint!");
2281 return atoi(ConstraintCode.c_str());
2282 }
2283
2284
2285 /// getConstraintGenerality - Return an integer indicating how general CT
2286 /// is.
2287 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2288 switch (CT) {
2289 default: assert(0 && "Unknown constraint type!");
2290 case TargetLowering::C_Other:
2291 case TargetLowering::C_Unknown:
2292 return 0;
2293 case TargetLowering::C_Register:
2294 return 1;
2295 case TargetLowering::C_RegisterClass:
2296 return 2;
2297 case TargetLowering::C_Memory:
2298 return 3;
2299 }
2300 }
2301
2302 /// ChooseConstraint - If there are multiple different constraints that we
2303 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2304 /// This is somewhat tricky: constraints fall into four classes:
2305 /// Other -> immediates and magic values
2306 /// Register -> one specific register
2307 /// RegisterClass -> a group of regs
2308 /// Memory -> memory
2309 /// Ideally, we would pick the most specific constraint possible: if we have
2310 /// something that fits into a register, we would pick it. The problem here
2311 /// is that if we have something that could either be in a register or in
2312 /// memory that use of the register could cause selection of *other*
2313 /// operands to fail: they might only succeed if we pick memory. Because of
2314 /// this the heuristic we use is:
2315 ///
2316 /// 1) If there is an 'other' constraint, and if the operand is valid for
2317 /// that constraint, use it. This makes us take advantage of 'i'
2318 /// constraints when available.
2319 /// 2) Otherwise, pick the most general constraint present. This prefers
2320 /// 'm' over 'r', for example.
2321 ///
2322 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2323 bool hasMemory, const TargetLowering &TLI,
2324 SDValue Op, SelectionDAG *DAG) {
2325 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2326 unsigned BestIdx = 0;
2327 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2328 int BestGenerality = -1;
2329
2330 // Loop over the options, keeping track of the most general one.
2331 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2332 TargetLowering::ConstraintType CType =
2333 TLI.getConstraintType(OpInfo.Codes[i]);
2334
2335 // If this is an 'other' constraint, see if the operand is valid for it.
2336 // For example, on X86 we might have an 'rI' constraint. If the operand
2337 // is an integer in the range [0..31] we want to use I (saving a load
2338 // of a register), otherwise we must use 'r'.
2339 if (CType == TargetLowering::C_Other && Op.getNode()) {
2340 assert(OpInfo.Codes[i].size() == 1 &&
2341 "Unhandled multi-letter 'other' constraint");
2342 std::vector<SDValue> ResultOps;
2343 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], hasMemory,
2344 ResultOps, *DAG);
2345 if (!ResultOps.empty()) {
2346 BestType = CType;
2347 BestIdx = i;
2348 break;
2349 }
2350 }
2351
2352 // This constraint letter is more general than the previous one, use it.
2353 int Generality = getConstraintGenerality(CType);
2354 if (Generality > BestGenerality) {
2355 BestType = CType;
2356 BestIdx = i;
2357 BestGenerality = Generality;
2358 }
2359 }
2360
2361 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2362 OpInfo.ConstraintType = BestType;
2363 }
2364
2365 /// ComputeConstraintToUse - Determines the constraint code and constraint
2366 /// type to use for the specific AsmOperandInfo, setting
2367 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2368 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2369 SDValue Op,
2370 bool hasMemory,
2371 SelectionDAG *DAG) const {
2372 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2373
2374 // Single-letter constraints ('r') are very common.
2375 if (OpInfo.Codes.size() == 1) {
2376 OpInfo.ConstraintCode = OpInfo.Codes[0];
2377 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2378 } else {
2379 ChooseConstraint(OpInfo, hasMemory, *this, Op, DAG);
2380 }
2381
2382 // 'X' matches anything.
2383 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2384 // Labels and constants are handled elsewhere ('X' is the only thing
2385 // that matches labels).
2386 if (isa<BasicBlock>(OpInfo.CallOperandVal) ||
2387 isa<ConstantInt>(OpInfo.CallOperandVal))
2388 return;
2389
2390 // Otherwise, try to resolve it to something we know about by looking at
2391 // the actual operand type.
2392 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2393 OpInfo.ConstraintCode = Repl;
2394 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2395 }
2396 }
2397 }
2398
2399 //===----------------------------------------------------------------------===//
2400 // Loop Strength Reduction hooks
2401 //===----------------------------------------------------------------------===//
2402
2403 /// isLegalAddressingMode - Return true if the addressing mode represented
2404 /// by AM is legal for this target, for a load/store of the specified type.
2405 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2406 const Type *Ty) const {
2407 // The default implementation of this implements a conservative RISCy, r+r and
2408 // r+i addr mode.
2409
2410 // Allows a sign-extended 16-bit immediate field.
2411 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2412 return false;
2413
2414 // No global is ever allowed as a base.
2415 if (AM.BaseGV)
2416 return false;
2417
2418 // Only support r+r,
2419 switch (AM.Scale) {
2420 case 0: // "r+i" or just "i", depending on HasBaseReg.
2421 break;
2422 case 1:
2423 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2424 return false;
2425 // Otherwise we have r+r or r+i.
2426 break;
2427 case 2:
2428 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2429 return false;
2430 // Allow 2*r as r+r.
2431 break;
2432 }
2433
2434 return true;
2435 }
2436
2437 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2438 /// return a DAG expression to select that will generate the same value by
2439 /// multiplying by a magic number. See:
2440 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2441 SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2442 std::vector<SDNode*>* Created) const {
2443 MVT VT = N->getValueType(0);
2444 DebugLoc dl= N->getDebugLoc();
2445
2446 // Check to see if we can do this.
2447 // FIXME: We should be more aggressive here.
2448 if (!isTypeLegal(VT))
2449 return SDValue();
2450
2451 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
2452 APInt::ms magics = d.magic();
2453
2454 // Multiply the numerator (operand 0) by the magic value
2455 // FIXME: We should support doing a MUL in a wider type
2456 SDValue Q;
2457 if (isOperationLegalOrCustom(ISD::MULHS, VT))
2458 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2459 DAG.getConstant(magics.m, VT));
2460 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2461 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2462 N->getOperand(0),
2463 DAG.getConstant(magics.m, VT)).getNode(), 1);
2464 else
2465 return SDValue(); // No mulhs or equvialent
2466 // If d > 0 and m < 0, add the numerator
2467 if (d.isStrictlyPositive() && magics.m.isNegative()) {
2468 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2469 if (Created)
2470 Created->push_back(Q.getNode());
2471 }
2472 // If d < 0 and m > 0, subtract the numerator.
2473 if (d.isNegative() && magics.m.isStrictlyPositive()) {
2474 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2475 if (Created)
2476 Created->push_back(Q.getNode());
2477 }
2478 // Shift right algebraic if shift value is nonzero
2479 if (magics.s > 0) {
2480 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2481 DAG.getConstant(magics.s, getShiftAmountTy()));
2482 if (Created)
2483 Created->push_back(Q.getNode());
2484 }
2485 // Extract the sign bit and add it to the quotient
2486 SDValue T =
2487 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2488 getShiftAmountTy()));
2489 if (Created)
2490 Created->push_back(T.getNode());
2491 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2492 }
2493
2494 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2495 /// return a DAG expression to select that will generate the same value by
2496 /// multiplying by a magic number. See:
2497 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2498 SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2499 std::vector<SDNode*>* Created) const {
2500 MVT VT = N->getValueType(0);
2501 DebugLoc dl = N->getDebugLoc();
2502
2503 // Check to see if we can do this.
2504 // FIXME: We should be more aggressive here.
2505 if (!isTypeLegal(VT))
2506 return SDValue();
2507
2508 // FIXME: We should use a narrower constant when the upper
2509 // bits are known to be zero.
2510 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
2511 APInt::mu magics = N1C->getAPIntValue().magicu();
2512
2513 // Multiply the numerator (operand 0) by the magic value
2514 // FIXME: We should support doing a MUL in a wider type
2515 SDValue Q;
2516 if (isOperationLegalOrCustom(ISD::MULHU, VT))
2517 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
2518 DAG.getConstant(magics.m, VT));
2519 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2520 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
2521 N->getOperand(0),
2522 DAG.getConstant(magics.m, VT)).getNode(), 1);
2523 else
2524 return SDValue(); // No mulhu or equvialent
2525 if (Created)
2526 Created->push_back(Q.getNode());
2527
2528 if (magics.a == 0) {
2529 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2530 "We shouldn't generate an undefined shift!");
2531 return DAG.getNode(ISD::SRL, dl, VT, Q,
2532 DAG.getConstant(magics.s, getShiftAmountTy()));
2533 } else {
2534 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2535 if (Created)
2536 Created->push_back(NPQ.getNode());
2537 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2538 DAG.getConstant(1, getShiftAmountTy()));
2539 if (Created)
2540 Created->push_back(NPQ.getNode());
2541 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2542 if (Created)
2543 Created->push_back(NPQ.getNode());
2544 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2545 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2546 }
2547 }
2548
2549 /// IgnoreHarmlessInstructions - Ignore instructions between a CALL and RET
2550 /// node that don't prevent tail call optimization.
2551 static SDValue IgnoreHarmlessInstructions(SDValue node) {
2552 // Found call return.
2553 if (node.getOpcode() == ISD::CALL) return node;
2554 // Ignore MERGE_VALUES. Will have at least one operand.
2555 if (node.getOpcode() == ISD::MERGE_VALUES)
2556 return IgnoreHarmlessInstructions(node.getOperand(0));
2557 // Ignore ANY_EXTEND node.
2558 if (node.getOpcode() == ISD::ANY_EXTEND)
2559 return IgnoreHarmlessInstructions(node.getOperand(0));
2560 if (node.getOpcode() == ISD::TRUNCATE)
2561 return IgnoreHarmlessInstructions(node.getOperand(0));
2562 // Any other node type.
2563 return node;
2564 }
2565
2566 bool TargetLowering::CheckTailCallReturnConstraints(CallSDNode *TheCall,
2567 SDValue Ret) {
2568 unsigned NumOps = Ret.getNumOperands();
2569 // ISD::CALL results:(value0, ..., valuen, chain)
2570 // ISD::RET operands:(chain, value0, flag0, ..., valuen, flagn)
2571 // Value return:
2572 // Check that operand of the RET node sources from the CALL node. The RET node
2573 // has at least two operands. Operand 0 holds the chain. Operand 1 holds the
2574 // value.
2575 if (NumOps > 1 &&
2576 IgnoreHarmlessInstructions(Ret.getOperand(1)) == SDValue(TheCall,0))
2577 return true;
2578 // void return: The RET node has the chain result value of the CALL node as
2579 // input.
2580 if (NumOps == 1 &&
2581 Ret.getOperand(0) == SDValue(TheCall, TheCall->getNumValues()-1))
2582 return true;
2583
2584 return false;
2585 }
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