lib/Target/X86/X86FastISel.cpp

   1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the X86-specific support for the FastISel class. Much
  11 // of the target-specific code is generated by tablegen in the file
  12 // X86GenFastISel.inc, which is #included here.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #include "X86.h"
  17 #include "X86InstrBuilder.h"
  18 #include "X86ISelLowering.h"
  19 #include "X86RegisterInfo.h"
  20 #include "X86Subtarget.h"
  21 #include "X86TargetMachine.h"
  22 #include "llvm/CallingConv.h"
  23 #include "llvm/DerivedTypes.h"
  24 #include "llvm/GlobalVariable.h"
  25 #include "llvm/Instructions.h"
  26 #include "llvm/IntrinsicInst.h"
  27 #include "llvm/CodeGen/FastISel.h"
  28 #include "llvm/CodeGen/MachineConstantPool.h"
  29 #include "llvm/CodeGen/MachineFrameInfo.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/Support/CallSite.h"
  32 #include "llvm/Support/GetElementPtrTypeIterator.h"
  33 using namespace llvm;
  34
  35 namespace {
  36
  37 class X86FastISel : public FastISel {
  38   /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
  39   /// make the right decision when generating code for different targets.
  40   const X86Subtarget *Subtarget;
  41
  42   /// StackPtr - Register used as the stack pointer.
  43   ///
  44   unsigned StackPtr;
  45
  46   /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
  47   /// floating point ops.
  48   /// When SSE is available, use it for f32 operations.
  49   /// When SSE2 is available, use it for f64 operations.
  50   bool X86ScalarSSEf64;
  51   bool X86ScalarSSEf32;
  52
  53 public:
  54   explicit X86FastISel(MachineFunction &mf,
  55                        MachineModuleInfo *mmi,
  56                        DwarfWriter *dw,
  57                        DenseMap<const Value *, unsigned> &vm,
  58                        DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
  59                        DenseMap<const AllocaInst *, int> &am
  60 #ifndef NDEBUG
  61                        , SmallSet<Instruction*, 8> &cil
  62 #endif
  63                        )
  64     : FastISel(mf, mmi, dw, vm, bm, am
  65 #ifndef NDEBUG
  66                , cil
  67 #endif
  68                ) {
  69     Subtarget = &TM.getSubtarget<X86Subtarget>();
  70     StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
  71     X86ScalarSSEf64 = Subtarget->hasSSE2();
  72     X86ScalarSSEf32 = Subtarget->hasSSE1();
  73   }
  74
  75   virtual bool TargetSelectInstruction(Instruction *I);
  76
  77 #include "X86GenFastISel.inc"
  78
  79 private:
  80   bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT);
  81
  82   bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR);
  83
  84   bool X86FastEmitStore(MVT VT, Value *Val,
  85                         const X86AddressMode &AM);
  86   bool X86FastEmitStore(MVT VT, unsigned Val,
  87                         const X86AddressMode &AM);
  88
  89   bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
  90                          unsigned &ResultReg);
  91
  92   bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
  93
  94   bool X86SelectLoad(Instruction *I);
  95
  96   bool X86SelectStore(Instruction *I);
  97
  98   bool X86SelectCmp(Instruction *I);
  99
 100   bool X86SelectZExt(Instruction *I);
 101
 102   bool X86SelectBranch(Instruction *I);
 103
 104   bool X86SelectShift(Instruction *I);
 105
 106   bool X86SelectSelect(Instruction *I);
 107
 108   bool X86SelectTrunc(Instruction *I);
 109
 110   bool X86SelectFPExt(Instruction *I);
 111   bool X86SelectFPTrunc(Instruction *I);
 112
 113   bool X86SelectExtractValue(Instruction *I);
 114
 115   bool X86VisitIntrinsicCall(IntrinsicInst &I);
 116   bool X86SelectCall(Instruction *I);
 117
 118   CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
 119
 120   const X86InstrInfo *getInstrInfo() const {
 121     return getTargetMachine()->getInstrInfo();
 122   }
 123   const X86TargetMachine *getTargetMachine() const {
 124     return static_cast<const X86TargetMachine *>(&TM);
 125   }
 126
 127   unsigned TargetMaterializeConstant(Constant *C);
 128
 129   unsigned TargetMaterializeAlloca(AllocaInst *C);
 130
 131   /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
 132   /// computed in an SSE register, not on the X87 floating point stack.
 133   bool isScalarFPTypeInSSEReg(MVT VT) const {
 134     return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
 135       (VT == MVT::f32 && X86ScalarSSEf32);   // f32 is when SSE1
 136   }
 137
 138   bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false);
 139 };
 140
 141 } // end anonymous namespace.
 142
 143 bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) {
 144   VT = TLI.getValueType(Ty, /*HandleUnknown=*/true);
 145   if (VT == MVT::Other || !VT.isSimple())
 146     // Unhandled type. Halt "fast" selection and bail.
 147     return false;
 148
 149   // For now, require SSE/SSE2 for performing floating-point operations,
 150   // since x87 requires additional work.
 151   if (VT == MVT::f64 && !X86ScalarSSEf64)
 152      return false;
 153   if (VT == MVT::f32 && !X86ScalarSSEf32)
 154      return false;
 155   // Similarly, no f80 support yet.
 156   if (VT == MVT::f80)
 157     return false;
 158   // We only handle legal types. For example, on x86-32 the instruction
 159   // selector contains all of the 64-bit instructions from x86-64,
 160   // under the assumption that i64 won't be used if the target doesn't
 161   // support it.
 162   return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
 163 }
 164
 165 #include "X86GenCallingConv.inc"
 166
 167 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
 168 /// convention.
 169 CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) {
 170   if (Subtarget->is64Bit()) {
 171     if (Subtarget->isTargetWin64())
 172       return CC_X86_Win64_C;
 173     else if (CC == CallingConv::Fast && isTaillCall)
 174       return CC_X86_64_TailCall;
 175     else
 176       return CC_X86_64_C;
 177   }
 178
 179   if (CC == CallingConv::X86_FastCall)
 180     return CC_X86_32_FastCall;
 181   else if (CC == CallingConv::Fast)
 182     return CC_X86_32_FastCC;
 183   else
 184     return CC_X86_32_C;
 185 }
 186
 187 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
 188 /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
 189 /// Return true and the result register by reference if it is possible.
 190 bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM,
 191                                   unsigned &ResultReg) {
 192   // Get opcode and regclass of the output for the given load instruction.
 193   unsigned Opc = 0;
 194   const TargetRegisterClass *RC = NULL;
 195   switch (VT.getSimpleVT()) {
 196   default: return false;
 197   case MVT::i8:
 198     Opc = X86::MOV8rm;
 199     RC  = X86::GR8RegisterClass;
 200     break;
 201   case MVT::i16:
 202     Opc = X86::MOV16rm;
 203     RC  = X86::GR16RegisterClass;
 204     break;
 205   case MVT::i32:
 206     Opc = X86::MOV32rm;
 207     RC  = X86::GR32RegisterClass;
 208     break;
 209   case MVT::i64:
 210     // Must be in x86-64 mode.
 211     Opc = X86::MOV64rm;
 212     RC  = X86::GR64RegisterClass;
 213     break;
 214   case MVT::f32:
 215     if (Subtarget->hasSSE1()) {
 216       Opc = X86::MOVSSrm;
 217       RC  = X86::FR32RegisterClass;
 218     } else {
 219       Opc = X86::LD_Fp32m;
 220       RC  = X86::RFP32RegisterClass;
 221     }
 222     break;
 223   case MVT::f64:
 224     if (Subtarget->hasSSE2()) {
 225       Opc = X86::MOVSDrm;
 226       RC  = X86::FR64RegisterClass;
 227     } else {
 228       Opc = X86::LD_Fp64m;
 229       RC  = X86::RFP64RegisterClass;
 230     }
 231     break;
 232   case MVT::f80:
 233     // No f80 support yet.
 234     return false;
 235   }
 236
 237   ResultReg = createResultReg(RC);
 238   addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
 239   return true;
 240 }
 241
 242 /// X86FastEmitStore - Emit a machine instruction to store a value Val of
 243 /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
 244 /// and a displacement offset, or a GlobalAddress,
 245 /// i.e. V. Return true if it is possible.
 246 bool
 247 X86FastISel::X86FastEmitStore(MVT VT, unsigned Val,
 248                               const X86AddressMode &AM) {
 249   // Get opcode and regclass of the output for the given store instruction.
 250   unsigned Opc = 0;
 251   switch (VT.getSimpleVT()) {
 252   case MVT::f80: // No f80 support yet.
 253   default: return false;
 254   case MVT::i8:  Opc = X86::MOV8mr;  break;
 255   case MVT::i16: Opc = X86::MOV16mr; break;
 256   case MVT::i32: Opc = X86::MOV32mr; break;
 257   case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
 258   case MVT::f32:
 259     Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m;
 260     break;
 261   case MVT::f64:
 262     Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m;
 263     break;
 264   }
 265
 266   addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
 267   return true;
 268 }
 269
 270 bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val,
 271                                    const X86AddressMode &AM) {
 272   // Handle 'null' like i32/i64 0.
 273   if (isa<ConstantPointerNull>(Val))
 274     Val = Constant::getNullValue(TD.getIntPtrType());
 275
 276   // If this is a store of a simple constant, fold the constant into the store.
 277   if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
 278     unsigned Opc = 0;
 279     switch (VT.getSimpleVT()) {
 280     default: break;
 281     case MVT::i8:  Opc = X86::MOV8mi;  break;
 282     case MVT::i16: Opc = X86::MOV16mi; break;
 283     case MVT::i32: Opc = X86::MOV32mi; break;
 284     case MVT::i64:
 285       // Must be a 32-bit sign extended value.
 286       if ((int)CI->getSExtValue() == CI->getSExtValue())
 287         Opc = X86::MOV64mi32;
 288       break;
 289     }
 290
 291     if (Opc) {
 292       addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
 293                              .addImm(CI->getSExtValue());
 294       return true;
 295     }
 296   }
 297
 298   unsigned ValReg = getRegForValue(Val);
 299   if (ValReg == 0)
 300     return false;
 301
 302   return X86FastEmitStore(VT, ValReg, AM);
 303 }
 304
 305 /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
 306 /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
 307 /// ISD::SIGN_EXTEND).
 308 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
 309                                     unsigned Src, MVT SrcVT,
 310                                     unsigned &ResultReg) {
 311   unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src);
 312
 313   if (RR != 0) {
 314     ResultReg = RR;
 315     return true;
 316   } else
 317     return false;
 318 }
 319
 320 /// X86SelectAddress - Attempt to fill in an address from the given value.
 321 ///
 322 bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
 323   User *U;
 324   unsigned Opcode = Instruction::UserOp1;
 325   if (Instruction *I = dyn_cast<Instruction>(V)) {
 326     Opcode = I->getOpcode();
 327     U = I;
 328   } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
 329     Opcode = C->getOpcode();
 330     U = C;
 331   }
 332
 333   switch (Opcode) {
 334   default: break;
 335   case Instruction::BitCast:
 336     // Look past bitcasts.
 337     return X86SelectAddress(U->getOperand(0), AM, isCall);
 338
 339   case Instruction::IntToPtr:
 340     // Look past no-op inttoptrs.
 341     if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
 342       return X86SelectAddress(U->getOperand(0), AM, isCall);
 343     break;
 344
 345   case Instruction::PtrToInt:
 346     // Look past no-op ptrtoints.
 347     if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
 348       return X86SelectAddress(U->getOperand(0), AM, isCall);
 349     break;
 350
 351   case Instruction::Alloca: {
 352     if (isCall) break;
 353     // Do static allocas.
 354     const AllocaInst *A = cast<AllocaInst>(V);
 355     DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
 356     if (SI != StaticAllocaMap.end()) {
 357       AM.BaseType = X86AddressMode::FrameIndexBase;
 358       AM.Base.FrameIndex = SI->second;
 359       return true;
 360     }
 361     break;
 362   }
 363
 364   case Instruction::Add: {
 365     if (isCall) break;
 366     // Adds of constants are common and easy enough.
 367     if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
 368       uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
 369       // They have to fit in the 32-bit signed displacement field though.
 370       if (isInt32(Disp)) {
 371         AM.Disp = (uint32_t)Disp;
 372         return X86SelectAddress(U->getOperand(0), AM, isCall);
 373       }
 374     }
 375     break;
 376   }
 377
 378   case Instruction::GetElementPtr: {
 379     if (isCall) break;
 380     // Pattern-match simple GEPs.
 381     uint64_t Disp = (int32_t)AM.Disp;
 382     unsigned IndexReg = AM.IndexReg;
 383     unsigned Scale = AM.Scale;
 384     gep_type_iterator GTI = gep_type_begin(U);
 385     // Iterate through the indices, folding what we can. Constants can be
 386     // folded, and one dynamic index can be handled, if the scale is supported.
 387     for (User::op_iterator i = U->op_begin() + 1, e = U->op_end();
 388          i != e; ++i, ++GTI) {
 389       Value *Op = *i;
 390       if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
 391         const StructLayout *SL = TD.getStructLayout(STy);
 392         unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
 393         Disp += SL->getElementOffset(Idx);
 394       } else {
 395         uint64_t S = TD.getTypePaddedSize(GTI.getIndexedType());
 396         if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
 397           // Constant-offset addressing.
 398           Disp += CI->getSExtValue() * S;
 399         } else if (IndexReg == 0 &&
 400                    (!AM.GV ||
 401                     !getTargetMachine()->symbolicAddressesAreRIPRel()) &&
 402                    (S == 1 || S == 2 || S == 4 || S == 8)) {
 403           // Scaled-index addressing.
 404           Scale = S;
 405           IndexReg = getRegForGEPIndex(Op);
 406           if (IndexReg == 0)
 407             return false;
 408         } else
 409           // Unsupported.
 410           goto unsupported_gep;
 411       }
 412     }
 413     // Check for displacement overflow.
 414     if (!isInt32(Disp))
 415       break;
 416     // Ok, the GEP indices were covered by constant-offset and scaled-index
 417     // addressing. Update the address state and move on to examining the base.
 418     AM.IndexReg = IndexReg;
 419     AM.Scale = Scale;
 420     AM.Disp = (uint32_t)Disp;
 421     return X86SelectAddress(U->getOperand(0), AM, isCall);
 422   unsupported_gep:
 423     // Ok, the GEP indices weren't all covered.
 424     break;
 425   }
 426   }
 427
 428   // Handle constant address.
 429   if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
 430     // Can't handle alternate code models yet.
 431     if (TM.getCodeModel() != CodeModel::Default &&
 432         TM.getCodeModel() != CodeModel::Small)
 433       return false;
 434
 435     // RIP-relative addresses can't have additional register operands.
 436     if (getTargetMachine()->symbolicAddressesAreRIPRel() &&
 437         (AM.Base.Reg != 0 || AM.IndexReg != 0))
 438       return false;
 439
 440     // Can't handle TLS yet.
 441     if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
 442       if (GVar->isThreadLocal())
 443         return false;
 444
 445     // Set up the basic address.
 446     AM.GV = GV;
 447     if (!isCall &&
 448         TM.getRelocationModel() == Reloc::PIC_ &&
 449         !Subtarget->is64Bit())
 450       AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
 451
 452     // Emit an extra load if the ABI requires it.
 453     if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
 454       // Check to see if we've already materialized this
 455       // value in a register in this block.
 456       if (unsigned Reg = LocalValueMap[V]) {
 457         AM.Base.Reg = Reg;
 458         AM.GV = 0;
 459         return true;
 460       }
 461       // Issue load from stub if necessary.
 462       unsigned Opc = 0;
 463       const TargetRegisterClass *RC = NULL;
 464       if (TLI.getPointerTy() == MVT::i32) {
 465         Opc = X86::MOV32rm;
 466         RC  = X86::GR32RegisterClass;
 467       } else {
 468         Opc = X86::MOV64rm;
 469         RC  = X86::GR64RegisterClass;
 470       }
 471
 472       X86AddressMode StubAM;
 473       StubAM.Base.Reg = AM.Base.Reg;
 474       StubAM.GV = AM.GV;
 475       unsigned ResultReg = createResultReg(RC);
 476       addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), StubAM);
 477
 478       // Now construct the final address. Note that the Disp, Scale,
 479       // and Index values may already be set here.
 480       AM.Base.Reg = ResultReg;
 481       AM.GV = 0;
 482
 483       // Prevent loading GV stub multiple times in same MBB.
 484       LocalValueMap[V] = AM.Base.Reg;
 485     }
 486     return true;
 487   }
 488
 489   // If all else fails, try to materialize the value in a register.
 490   if (!AM.GV || !getTargetMachine()->symbolicAddressesAreRIPRel()) {
 491     if (AM.Base.Reg == 0) {
 492       AM.Base.Reg = getRegForValue(V);
 493       return AM.Base.Reg != 0;
 494     }
 495     if (AM.IndexReg == 0) {
 496       assert(AM.Scale == 1 && "Scale with no index!");
 497       AM.IndexReg = getRegForValue(V);
 498       return AM.IndexReg != 0;
 499     }
 500   }
 501
 502   return false;
 503 }
 504
 505 /// X86SelectStore - Select and emit code to implement store instructions.
 506 bool X86FastISel::X86SelectStore(Instruction* I) {
 507   MVT VT;
 508   if (!isTypeLegal(I->getOperand(0)->getType(), VT))
 509     return false;
 510
 511   X86AddressMode AM;
 512   if (!X86SelectAddress(I->getOperand(1), AM, false))
 513     return false;
 514
 515   return X86FastEmitStore(VT, I->getOperand(0), AM);
 516 }
 517
 518 /// X86SelectLoad - Select and emit code to implement load instructions.
 519 ///
 520 bool X86FastISel::X86SelectLoad(Instruction *I)  {
 521   MVT VT;
 522   if (!isTypeLegal(I->getType(), VT))
 523     return false;
 524
 525   X86AddressMode AM;
 526   if (!X86SelectAddress(I->getOperand(0), AM, false))
 527     return false;
 528
 529   unsigned ResultReg = 0;
 530   if (X86FastEmitLoad(VT, AM, ResultReg)) {
 531     UpdateValueMap(I, ResultReg);
 532     return true;
 533   }
 534   return false;
 535 }
 536
 537 static unsigned X86ChooseCmpOpcode(MVT VT) {
 538   switch (VT.getSimpleVT()) {
 539   default:       return 0;
 540   case MVT::i8:  return X86::CMP8rr;
 541   case MVT::i16: return X86::CMP16rr;
 542   case MVT::i32: return X86::CMP32rr;
 543   case MVT::i64: return X86::CMP64rr;
 544   case MVT::f32: return X86::UCOMISSrr;
 545   case MVT::f64: return X86::UCOMISDrr;
 546   }
 547 }
 548
 549 /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS
 550 /// of the comparison, return an opcode that works for the compare (e.g.
 551 /// CMP32ri) otherwise return 0.
 552 static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) {
 553   switch (VT.getSimpleVT()) {
 554   // Otherwise, we can't fold the immediate into this comparison.
 555   default: return 0;
 556   case MVT::i8: return X86::CMP8ri;
 557   case MVT::i16: return X86::CMP16ri;
 558   case MVT::i32: return X86::CMP32ri;
 559   case MVT::i64:
 560     // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
 561     // field.
 562     if ((int)RHSC->getSExtValue() == RHSC->getSExtValue())
 563       return X86::CMP64ri32;
 564     return 0;
 565   }
 566 }
 567
 568 bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) {
 569   unsigned Op0Reg = getRegForValue(Op0);
 570   if (Op0Reg == 0) return false;
 571
 572   // Handle 'null' like i32/i64 0.
 573   if (isa<ConstantPointerNull>(Op1))
 574     Op1 = Constant::getNullValue(TD.getIntPtrType());
 575
 576   // We have two options: compare with register or immediate.  If the RHS of
 577   // the compare is an immediate that we can fold into this compare, use
 578   // CMPri, otherwise use CMPrr.
 579   if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
 580     if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
 581       BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
 582                                           .addImm(Op1C->getSExtValue());
 583       return true;
 584     }
 585   }
 586
 587   unsigned CompareOpc = X86ChooseCmpOpcode(VT);
 588   if (CompareOpc == 0) return false;
 589
 590   unsigned Op1Reg = getRegForValue(Op1);
 591   if (Op1Reg == 0) return false;
 592   BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
 593
 594   return true;
 595 }
 596
 597 bool X86FastISel::X86SelectCmp(Instruction *I) {
 598   CmpInst *CI = cast<CmpInst>(I);
 599
 600   MVT VT;
 601   if (!isTypeLegal(I->getOperand(0)->getType(), VT))
 602     return false;
 603
 604   unsigned ResultReg = createResultReg(&X86::GR8RegClass);
 605   unsigned SetCCOpc;
 606   bool SwapArgs;  // false -> compare Op0, Op1.  true -> compare Op1, Op0.
 607   switch (CI->getPredicate()) {
 608   case CmpInst::FCMP_OEQ: {
 609     if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
 610       return false;
 611
 612     unsigned EReg = createResultReg(&X86::GR8RegClass);
 613     unsigned NPReg = createResultReg(&X86::GR8RegClass);
 614     BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
 615     BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
 616     BuildMI(MBB, DL,
 617             TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
 618     UpdateValueMap(I, ResultReg);
 619     return true;
 620   }
 621   case CmpInst::FCMP_UNE: {
 622     if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT))
 623       return false;
 624
 625     unsigned NEReg = createResultReg(&X86::GR8RegClass);
 626     unsigned PReg = createResultReg(&X86::GR8RegClass);
 627     BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
 628     BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
 629     BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
 630     UpdateValueMap(I, ResultReg);
 631     return true;
 632   }
 633   case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr;  break;
 634   case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
 635   case CmpInst::FCMP_OLT: SwapArgs = true;  SetCCOpc = X86::SETAr;  break;
 636   case CmpInst::FCMP_OLE: SwapArgs = true;  SetCCOpc = X86::SETAEr; break;
 637   case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
 638   case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
 639   case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr;  break;
 640   case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr;  break;
 641   case CmpInst::FCMP_UGT: SwapArgs = true;  SetCCOpc = X86::SETBr;  break;
 642   case CmpInst::FCMP_UGE: SwapArgs = true;  SetCCOpc = X86::SETBEr; break;
 643   case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr;  break;
 644   case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
 645
 646   case CmpInst::ICMP_EQ:  SwapArgs = false; SetCCOpc = X86::SETEr;  break;
 647   case CmpInst::ICMP_NE:  SwapArgs = false; SetCCOpc = X86::SETNEr; break;
 648   case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr;  break;
 649   case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
 650   case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr;  break;
 651   case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
 652   case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr;  break;
 653   case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
 654   case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr;  break;
 655   case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
 656   default:
 657     return false;
 658   }
 659
 660   Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
 661   if (SwapArgs)
 662     std::swap(Op0, Op1);
 663
 664   // Emit a compare of Op0/Op1.
 665   if (!X86FastEmitCompare(Op0, Op1, VT))
 666     return false;
 667
 668   BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
 669   UpdateValueMap(I, ResultReg);
 670   return true;
 671 }
 672
 673 bool X86FastISel::X86SelectZExt(Instruction *I) {
 674   // Handle zero-extension from i1 to i8, which is common.
 675   if (I->getType() == Type::Int8Ty &&
 676       I->getOperand(0)->getType() == Type::Int1Ty) {
 677     unsigned ResultReg = getRegForValue(I->getOperand(0));
 678     if (ResultReg == 0) return false;
 679     // Set the high bits to zero.
 680     ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg);
 681     if (ResultReg == 0) return false;
 682     UpdateValueMap(I, ResultReg);
 683     return true;
 684   }
 685
 686   return false;
 687 }
 688
 689
 690 bool X86FastISel::X86SelectBranch(Instruction *I) {
 691   // Unconditional branches are selected by tablegen-generated code.
 692   // Handle a conditional branch.
 693   BranchInst *BI = cast<BranchInst>(I);
 694   MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
 695   MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
 696
 697   // Fold the common case of a conditional branch with a comparison.
 698   if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
 699     if (CI->hasOneUse()) {
 700       MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
 701
 702       // Try to take advantage of fallthrough opportunities.
 703       CmpInst::Predicate Predicate = CI->getPredicate();
 704       if (MBB->isLayoutSuccessor(TrueMBB)) {
 705         std::swap(TrueMBB, FalseMBB);
 706         Predicate = CmpInst::getInversePredicate(Predicate);
 707       }
 708
 709       bool SwapArgs;  // false -> compare Op0, Op1.  true -> compare Op1, Op0.
 710       unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
 711
 712       switch (Predicate) {
 713       case CmpInst::FCMP_OEQ:
 714         std::swap(TrueMBB, FalseMBB);
 715         Predicate = CmpInst::FCMP_UNE;
 716         // FALL THROUGH
 717       case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE; break;
 718       case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA;  break;
 719       case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE; break;
 720       case CmpInst::FCMP_OLT: SwapArgs = true;  BranchOpc = X86::JA;  break;
 721       case CmpInst::FCMP_OLE: SwapArgs = true;  BranchOpc = X86::JAE; break;
 722       case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE; break;
 723       case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP; break;
 724       case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP;  break;
 725       case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE;  break;
 726       case CmpInst::FCMP_UGT: SwapArgs = true;  BranchOpc = X86::JB;  break;
 727       case CmpInst::FCMP_UGE: SwapArgs = true;  BranchOpc = X86::JBE; break;
 728       case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB;  break;
 729       case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
 730
 731       case CmpInst::ICMP_EQ:  SwapArgs = false; BranchOpc = X86::JE;  break;
 732       case CmpInst::ICMP_NE:  SwapArgs = false; BranchOpc = X86::JNE; break;
 733       case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA;  break;
 734       case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE; break;
 735       case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB;  break;
 736       case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE; break;
 737       case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG;  break;
 738       case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE; break;
 739       case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL;  break;
 740       case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE; break;
 741       default:
 742         return false;
 743       }
 744
 745       Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1);
 746       if (SwapArgs)
 747         std::swap(Op0, Op1);
 748
 749       // Emit a compare of the LHS and RHS, setting the flags.
 750       if (!X86FastEmitCompare(Op0, Op1, VT))
 751         return false;
 752
 753       BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
 754
 755       if (Predicate == CmpInst::FCMP_UNE) {
 756         // X86 requires a second branch to handle UNE (and OEQ,
 757         // which is mapped to UNE above).
 758         BuildMI(MBB, DL, TII.get(X86::JP)).addMBB(TrueMBB);
 759       }
 760
 761       FastEmitBranch(FalseMBB);
 762       MBB->addSuccessor(TrueMBB);
 763       return true;
 764     }
 765   } else if (ExtractValueInst *EI =
 766              dyn_cast<ExtractValueInst>(BI->getCondition())) {
 767     // Check to see if the branch instruction is from an "arithmetic with
 768     // overflow" intrinsic. The main way these intrinsics are used is:
 769     //
 770     //   %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
 771     //   %sum = extractvalue { i32, i1 } %t, 0
 772     //   %obit = extractvalue { i32, i1 } %t, 1
 773     //   br i1 %obit, label %overflow, label %normal
 774     //
 775     // The %sum and %obit are converted in an ADD and a SETO/SETB before
 776     // reaching the branch. Therefore, we search backwards through the MBB
 777     // looking for the SETO/SETB instruction. If an instruction modifies the
 778     // EFLAGS register before we reach the SETO/SETB instruction, then we can't
 779     // convert the branch into a JO/JB instruction.
 780     if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){
 781       if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow ||
 782           CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) {
 783         const MachineInstr *SetMI = 0;
 784         unsigned Reg = lookUpRegForValue(EI);
 785
 786         for (MachineBasicBlock::const_reverse_iterator
 787                RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
 788           const MachineInstr &MI = *RI;
 789
 790           if (MI.modifiesRegister(Reg)) {
 791             unsigned Src, Dst, SrcSR, DstSR;
 792
 793             if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) {
 794               Reg = Src;
 795               continue;
 796             }
 797
 798             SetMI = &MI;
 799             break;
 800           }
 801
 802           const TargetInstrDesc &TID = MI.getDesc();
 803           if (TID.hasUnmodeledSideEffects() ||
 804               TID.hasImplicitDefOfPhysReg(X86::EFLAGS))
 805             break;
 806         }
 807
 808         if (SetMI) {
 809           unsigned OpCode = SetMI->getOpcode();
 810
 811           if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
 812             BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? X86::JO : X86::JB))
 813               .addMBB(TrueMBB);
 814             FastEmitBranch(FalseMBB);
 815             MBB->addSuccessor(TrueMBB);
 816             return true;
 817           }
 818         }
 819       }
 820     }
 821   }
 822
 823   // Otherwise do a clumsy setcc and re-test it.
 824   unsigned OpReg = getRegForValue(BI->getCondition());
 825   if (OpReg == 0) return false;
 826
 827   BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
 828   BuildMI(MBB, DL, TII.get(X86::JNE)).addMBB(TrueMBB);
 829   FastEmitBranch(FalseMBB);
 830   MBB->addSuccessor(TrueMBB);
 831   return true;
 832 }
 833
 834 bool X86FastISel::X86SelectShift(Instruction *I) {
 835   unsigned CReg = 0, OpReg = 0, OpImm = 0;
 836   const TargetRegisterClass *RC = NULL;
 837   if (I->getType() == Type::Int8Ty) {
 838     CReg = X86::CL;
 839     RC = &X86::GR8RegClass;
 840     switch (I->getOpcode()) {
 841     case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break;
 842     case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break;
 843     case Instruction::Shl:  OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break;
 844     default: return false;
 845     }
 846   } else if (I->getType() == Type::Int16Ty) {
 847     CReg = X86::CX;
 848     RC = &X86::GR16RegClass;
 849     switch (I->getOpcode()) {
 850     case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break;
 851     case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break;
 852     case Instruction::Shl:  OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break;
 853     default: return false;
 854     }
 855   } else if (I->getType() == Type::Int32Ty) {
 856     CReg = X86::ECX;
 857     RC = &X86::GR32RegClass;
 858     switch (I->getOpcode()) {
 859     case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break;
 860     case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break;
 861     case Instruction::Shl:  OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break;
 862     default: return false;
 863     }
 864   } else if (I->getType() == Type::Int64Ty) {
 865     CReg = X86::RCX;
 866     RC = &X86::GR64RegClass;
 867     switch (I->getOpcode()) {
 868     case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break;
 869     case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break;
 870     case Instruction::Shl:  OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break;
 871     default: return false;
 872     }
 873   } else {
 874     return false;
 875   }
 876
 877   MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
 878   if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
 879     return false;
 880
 881   unsigned Op0Reg = getRegForValue(I->getOperand(0));
 882   if (Op0Reg == 0) return false;
 883
 884   // Fold immediate in shl(x,3).
 885   if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
 886     unsigned ResultReg = createResultReg(RC);
 887     BuildMI(MBB, DL, TII.get(OpImm),
 888             ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
 889     UpdateValueMap(I, ResultReg);
 890     return true;
 891   }
 892
 893   unsigned Op1Reg = getRegForValue(I->getOperand(1));
 894   if (Op1Reg == 0) return false;
 895   TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
 896
 897   // The shift instruction uses X86::CL. If we defined a super-register
 898   // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
 899   // we're doing here.
 900   if (CReg != X86::CL)
 901     BuildMI(MBB, DL, TII.get(TargetInstrInfo::EXTRACT_SUBREG), X86::CL)
 902       .addReg(CReg).addImm(X86::SUBREG_8BIT);
 903
 904   unsigned ResultReg = createResultReg(RC);
 905   BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
 906   UpdateValueMap(I, ResultReg);
 907   return true;
 908 }
 909
 910 bool X86FastISel::X86SelectSelect(Instruction *I) {
 911   MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
 912   if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
 913     return false;
 914
 915   unsigned Opc = 0;
 916   const TargetRegisterClass *RC = NULL;
 917   if (VT.getSimpleVT() == MVT::i16) {
 918     Opc = X86::CMOVE16rr;
 919     RC = &X86::GR16RegClass;
 920   } else if (VT.getSimpleVT() == MVT::i32) {
 921     Opc = X86::CMOVE32rr;
 922     RC = &X86::GR32RegClass;
 923   } else if (VT.getSimpleVT() == MVT::i64) {
 924     Opc = X86::CMOVE64rr;
 925     RC = &X86::GR64RegClass;
 926   } else {
 927     return false;
 928   }
 929
 930   unsigned Op0Reg = getRegForValue(I->getOperand(0));
 931   if (Op0Reg == 0) return false;
 932   unsigned Op1Reg = getRegForValue(I->getOperand(1));
 933   if (Op1Reg == 0) return false;
 934   unsigned Op2Reg = getRegForValue(I->getOperand(2));
 935   if (Op2Reg == 0) return false;
 936
 937   BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
 938   unsigned ResultReg = createResultReg(RC);
 939   BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
 940   UpdateValueMap(I, ResultReg);
 941   return true;
 942 }
 943
 944 bool X86FastISel::X86SelectFPExt(Instruction *I) {
 945   // fpext from float to double.
 946   if (Subtarget->hasSSE2() && I->getType() == Type::DoubleTy) {
 947     Value *V = I->getOperand(0);
 948     if (V->getType() == Type::FloatTy) {
 949       unsigned OpReg = getRegForValue(V);
 950       if (OpReg == 0) return false;
 951       unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
 952       BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
 953       UpdateValueMap(I, ResultReg);
 954       return true;
 955     }
 956   }
 957
 958   return false;
 959 }
 960
 961 bool X86FastISel::X86SelectFPTrunc(Instruction *I) {
 962   if (Subtarget->hasSSE2()) {
 963     if (I->getType() == Type::FloatTy) {
 964       Value *V = I->getOperand(0);
 965       if (V->getType() == Type::DoubleTy) {
 966         unsigned OpReg = getRegForValue(V);
 967         if (OpReg == 0) return false;
 968         unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
 969         BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
 970         UpdateValueMap(I, ResultReg);
 971         return true;
 972       }
 973     }
 974   }
 975
 976   return false;
 977 }
 978
 979 bool X86FastISel::X86SelectTrunc(Instruction *I) {
 980   if (Subtarget->is64Bit())
 981     // All other cases should be handled by the tblgen generated code.
 982     return false;
 983   MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 984   MVT DstVT = TLI.getValueType(I->getType());
 985
 986   // This code only handles truncation to byte right now.
 987   if (DstVT != MVT::i8 && DstVT != MVT::i1)
 988     // All other cases should be handled by the tblgen generated code.
 989     return false;
 990   if (SrcVT != MVT::i16 && SrcVT != MVT::i32)
 991     // All other cases should be handled by the tblgen generated code.
 992     return false;
 993
 994   unsigned InputReg = getRegForValue(I->getOperand(0));
 995   if (!InputReg)
 996     // Unhandled operand.  Halt "fast" selection and bail.
 997     return false;
 998
 999   // First issue a copy to GR16_ABCD or GR32_ABCD.
1000   unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
1001   const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
1002     ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
1003   unsigned CopyReg = createResultReg(CopyRC);
1004   BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1005
1006   // Then issue an extract_subreg.
1007   unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
1008                                                   CopyReg, X86::SUBREG_8BIT);
1009   if (!ResultReg)
1010     return false;
1011
1012   UpdateValueMap(I, ResultReg);
1013   return true;
1014 }
1015
1016 bool X86FastISel::X86SelectExtractValue(Instruction *I) {
1017   ExtractValueInst *EI = cast<ExtractValueInst>(I);
1018   Value *Agg = EI->getAggregateOperand();
1019
1020   if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) {
1021     switch (CI->getIntrinsicID()) {
1022     default: break;
1023     case Intrinsic::sadd_with_overflow:
1024     case Intrinsic::uadd_with_overflow:
1025       // Cheat a little. We know that the registers for "add" and "seto" are
1026       // allocated sequentially. However, we only keep track of the register
1027       // for "add" in the value map. Use extractvalue's index to get the
1028       // correct register for "seto".
1029       UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1030       return true;
1031     }
1032   }
1033
1034   return false;
1035 }
1036
1037 bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) {
1038   // FIXME: Handle more intrinsics.
1039   switch (I.getIntrinsicID()) {
1040   default: return false;
1041   case Intrinsic::sadd_with_overflow:
1042   case Intrinsic::uadd_with_overflow: {
1043     // Replace "add with overflow" intrinsics with an "add" instruction followed
1044     // by a seto/setc instruction. Later on, when the "extractvalue"
1045     // instructions are encountered, we use the fact that two registers were
1046     // created sequentially to get the correct registers for the "sum" and the
1047     // "overflow bit".
1048     const Function *Callee = I.getCalledFunction();
1049     const Type *RetTy =
1050       cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0));
1051
1052     MVT VT;
1053     if (!isTypeLegal(RetTy, VT))
1054       return false;
1055
1056     Value *Op1 = I.getOperand(1);
1057     Value *Op2 = I.getOperand(2);
1058     unsigned Reg1 = getRegForValue(Op1);
1059     unsigned Reg2 = getRegForValue(Op2);
1060
1061     if (Reg1 == 0 || Reg2 == 0)
1062       // FIXME: Handle values *not* in registers.
1063       return false;
1064
1065     unsigned OpC = 0;
1066     if (VT == MVT::i32)
1067       OpC = X86::ADD32rr;
1068     else if (VT == MVT::i64)
1069       OpC = X86::ADD64rr;
1070     else
1071       return false;
1072
1073     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1074     BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1075     unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
1076
1077     // If the add with overflow is an intra-block value then we just want to
1078     // create temporaries for it like normal.  If it is a cross-block value then
1079     // UpdateValueMap will return the cross-block register used.  Since we
1080     // *really* want the value to be live in the register pair known by
1081     // UpdateValueMap, we have to use DestReg1+1 as the destination register in
1082     // the cross block case.  In the non-cross-block case, we should just make
1083     // another register for the value.
1084     if (DestReg1 != ResultReg)
1085       ResultReg = DestReg1+1;
1086     else
1087       ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8));
1088
1089     unsigned Opc = X86::SETBr;
1090     if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
1091       Opc = X86::SETOr;
1092     BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1093     return true;
1094   }
1095   }
1096 }
1097
1098 bool X86FastISel::X86SelectCall(Instruction *I) {
1099   CallInst *CI = cast<CallInst>(I);
1100   Value *Callee = I->getOperand(0);
1101
1102   // Can't handle inline asm yet.
1103   if (isa<InlineAsm>(Callee))
1104     return false;
1105
1106   // Handle intrinsic calls.
1107   if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI))
1108     return X86VisitIntrinsicCall(*II);
1109
1110   // Handle only C and fastcc calling conventions for now.
1111   CallSite CS(CI);
1112   unsigned CC = CS.getCallingConv();
1113   if (CC != CallingConv::C &&
1114       CC != CallingConv::Fast &&
1115       CC != CallingConv::X86_FastCall)
1116     return false;
1117
1118   // Let SDISel handle vararg functions.
1119   const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1120   const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1121   if (FTy->isVarArg())
1122     return false;
1123
1124   // Handle *simple* calls for now.
1125   const Type *RetTy = CS.getType();
1126   MVT RetVT;
1127   if (RetTy == Type::VoidTy)
1128     RetVT = MVT::isVoid;
1129   else if (!isTypeLegal(RetTy, RetVT, true))
1130     return false;
1131
1132   // Materialize callee address in a register. FIXME: GV address can be
1133   // handled with a CALLpcrel32 instead.
1134   X86AddressMode CalleeAM;
1135   if (!X86SelectAddress(Callee, CalleeAM, true))
1136     return false;
1137   unsigned CalleeOp = 0;
1138   GlobalValue *GV = 0;
1139   if (CalleeAM.Base.Reg != 0) {
1140     assert(CalleeAM.GV == 0);
1141     CalleeOp = CalleeAM.Base.Reg;
1142   } else if (CalleeAM.GV != 0) {
1143     assert(CalleeAM.GV != 0);
1144     GV = CalleeAM.GV;
1145   } else
1146     return false;
1147
1148   // Allow calls which produce i1 results.
1149   bool AndToI1 = false;
1150   if (RetVT == MVT::i1) {
1151     RetVT = MVT::i8;
1152     AndToI1 = true;
1153   }
1154
1155   // Deal with call operands first.
1156   SmallVector<Value*, 8> ArgVals;
1157   SmallVector<unsigned, 8> Args;
1158   SmallVector<MVT, 8> ArgVTs;
1159   SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1160   Args.reserve(CS.arg_size());
1161   ArgVals.reserve(CS.arg_size());
1162   ArgVTs.reserve(CS.arg_size());
1163   ArgFlags.reserve(CS.arg_size());
1164   for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1165        i != e; ++i) {
1166     unsigned Arg = getRegForValue(*i);
1167     if (Arg == 0)
1168       return false;
1169     ISD::ArgFlagsTy Flags;
1170     unsigned AttrInd = i - CS.arg_begin() + 1;
1171     if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1172       Flags.setSExt();
1173     if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1174       Flags.setZExt();
1175
1176     // FIXME: Only handle *easy* calls for now.
1177     if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1178         CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1179         CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1180         CS.paramHasAttr(AttrInd, Attribute::ByVal))
1181       return false;
1182
1183     const Type *ArgTy = (*i)->getType();
1184     MVT ArgVT;
1185     if (!isTypeLegal(ArgTy, ArgVT))
1186       return false;
1187     unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1188     Flags.setOrigAlign(OriginalAlignment);
1189
1190     Args.push_back(Arg);
1191     ArgVals.push_back(*i);
1192     ArgVTs.push_back(ArgVT);
1193     ArgFlags.push_back(Flags);
1194   }
1195
1196   // Analyze operands of the call, assigning locations to each operand.
1197   SmallVector<CCValAssign, 16> ArgLocs;
1198   CCState CCInfo(CC, false, TM, ArgLocs);
1199   CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
1200
1201   // Get a count of how many bytes are to be pushed on the stack.
1202   unsigned NumBytes = CCInfo.getNextStackOffset();
1203
1204   // Issue CALLSEQ_START
1205   unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1206   BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1207
1208   // Process argument: walk the register/memloc assignments, inserting
1209   // copies / loads.
1210   SmallVector<unsigned, 4> RegArgs;
1211   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1212     CCValAssign &VA = ArgLocs[i];
1213     unsigned Arg = Args[VA.getValNo()];
1214     MVT ArgVT = ArgVTs[VA.getValNo()];
1215
1216     // Promote the value if needed.
1217     switch (VA.getLocInfo()) {
1218     default: assert(0 && "Unknown loc info!");
1219     case CCValAssign::Full: break;
1220     case CCValAssign::SExt: {
1221       bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1222                                        Arg, ArgVT, Arg);
1223       assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1224       Emitted = true;
1225       ArgVT = VA.getLocVT();
1226       break;
1227     }
1228     case CCValAssign::ZExt: {
1229       bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1230                                        Arg, ArgVT, Arg);
1231       assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1232       Emitted = true;
1233       ArgVT = VA.getLocVT();
1234       break;
1235     }
1236     case CCValAssign::AExt: {
1237       bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1238                                        Arg, ArgVT, Arg);
1239       if (!Emitted)
1240         Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1241                                     Arg, ArgVT, Arg);
1242       if (!Emitted)
1243         Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1244                                     Arg, ArgVT, Arg);
1245
1246       assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1247       ArgVT = VA.getLocVT();
1248       break;
1249     }
1250     }
1251
1252     if (VA.isRegLoc()) {
1253       TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1254       bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1255                                       Arg, RC, RC);
1256       assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1257       Emitted = true;
1258       RegArgs.push_back(VA.getLocReg());
1259     } else {
1260       unsigned LocMemOffset = VA.getLocMemOffset();
1261       X86AddressMode AM;
1262       AM.Base.Reg = StackPtr;
1263       AM.Disp = LocMemOffset;
1264       Value *ArgVal = ArgVals[VA.getValNo()];
1265
1266       // If this is a really simple value, emit this with the Value* version of
1267       // X86FastEmitStore.  If it isn't simple, we don't want to do this, as it
1268       // can cause us to reevaluate the argument.
1269       if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal))
1270         X86FastEmitStore(ArgVT, ArgVal, AM);
1271       else
1272         X86FastEmitStore(ArgVT, Arg, AM);
1273     }
1274   }
1275
1276   // ELF / PIC requires GOT in the EBX register before function calls via PLT
1277   // GOT pointer.
1278   if (!Subtarget->is64Bit() &&
1279       TM.getRelocationModel() == Reloc::PIC_ &&
1280       Subtarget->isPICStyleGOT()) {
1281     TargetRegisterClass *RC = X86::GR32RegisterClass;
1282     unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
1283     bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
1284     assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1285     Emitted = true;
1286   }
1287
1288   // Issue the call.
1289   unsigned CallOpc = CalleeOp
1290     ? (Subtarget->is64Bit() ? X86::CALL64r       : X86::CALL32r)
1291     : (Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32);
1292   MachineInstrBuilder MIB = CalleeOp
1293     ? BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp)
1294     : BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV);
1295
1296   // Add an implicit use GOT pointer in EBX.
1297   if (!Subtarget->is64Bit() &&
1298       TM.getRelocationModel() == Reloc::PIC_ &&
1299       Subtarget->isPICStyleGOT())
1300     MIB.addReg(X86::EBX);
1301
1302   // Add implicit physical register uses to the call.
1303   for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1304     MIB.addReg(RegArgs[i]);
1305
1306   // Issue CALLSEQ_END
1307   unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1308   BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1309
1310   // Now handle call return value (if any).
1311   if (RetVT.getSimpleVT() != MVT::isVoid) {
1312     SmallVector<CCValAssign, 16> RVLocs;
1313     CCState CCInfo(CC, false, TM, RVLocs);
1314     CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
1315
1316     // Copy all of the result registers out of their specified physreg.
1317     assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1318     MVT CopyVT = RVLocs[0].getValVT();
1319     TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1320     TargetRegisterClass *SrcRC = DstRC;
1321
1322     // If this is a call to a function that returns an fp value on the x87 fp
1323     // stack, but where we prefer to use the value in xmm registers, copy it
1324     // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1325     if ((RVLocs[0].getLocReg() == X86::ST0 ||
1326          RVLocs[0].getLocReg() == X86::ST1) &&
1327         isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
1328       CopyVT = MVT::f80;
1329       SrcRC = X86::RSTRegisterClass;
1330       DstRC = X86::RFP80RegisterClass;
1331     }
1332
1333     unsigned ResultReg = createResultReg(DstRC);
1334     bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1335                                     RVLocs[0].getLocReg(), DstRC, SrcRC);
1336     assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
1337     Emitted = true;
1338     if (CopyVT != RVLocs[0].getValVT()) {
1339       // Round the F80 the right size, which also moves to the appropriate xmm
1340       // register. This is accomplished by storing the F80 value in memory and
1341       // then loading it back. Ewww...
1342       MVT ResVT = RVLocs[0].getValVT();
1343       unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
1344       unsigned MemSize = ResVT.getSizeInBits()/8;
1345       int FI = MFI.CreateStackObject(MemSize, MemSize);
1346       addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1347       DstRC = ResVT == MVT::f32
1348         ? X86::FR32RegisterClass : X86::FR64RegisterClass;
1349       Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
1350       ResultReg = createResultReg(DstRC);
1351       addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1352     }
1353
1354     if (AndToI1) {
1355       // Mask out all but lowest bit for some call which produces an i1.
1356       unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1357       BuildMI(MBB, DL,
1358               TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
1359       ResultReg = AndResult;
1360     }
1361
1362     UpdateValueMap(I, ResultReg);
1363   }
1364
1365   return true;
1366 }
1367
1368
1369 bool
1370 X86FastISel::TargetSelectInstruction(Instruction *I)  {
1371   switch (I->getOpcode()) {
1372   default: break;
1373   case Instruction::Load:
1374     return X86SelectLoad(I);
1375   case Instruction::Store:
1376     return X86SelectStore(I);
1377   case Instruction::ICmp:
1378   case Instruction::FCmp:
1379     return X86SelectCmp(I);
1380   case Instruction::ZExt:
1381     return X86SelectZExt(I);
1382   case Instruction::Br:
1383     return X86SelectBranch(I);
1384   case Instruction::Call:
1385     return X86SelectCall(I);
1386   case Instruction::LShr:
1387   case Instruction::AShr:
1388   case Instruction::Shl:
1389     return X86SelectShift(I);
1390   case Instruction::Select:
1391     return X86SelectSelect(I);
1392   case Instruction::Trunc:
1393     return X86SelectTrunc(I);
1394   case Instruction::FPExt:
1395     return X86SelectFPExt(I);
1396   case Instruction::FPTrunc:
1397     return X86SelectFPTrunc(I);
1398   case Instruction::ExtractValue:
1399     return X86SelectExtractValue(I);
1400   case Instruction::IntToPtr: // Deliberate fall-through.
1401   case Instruction::PtrToInt: {
1402     MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1403     MVT DstVT = TLI.getValueType(I->getType());
1404     if (DstVT.bitsGT(SrcVT))
1405       return X86SelectZExt(I);
1406     if (DstVT.bitsLT(SrcVT))
1407       return X86SelectTrunc(I);
1408     unsigned Reg = getRegForValue(I->getOperand(0));
1409     if (Reg == 0) return false;
1410     UpdateValueMap(I, Reg);
1411     return true;
1412   }
1413   }
1414
1415   return false;
1416 }
1417
1418 unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
1419   MVT VT;
1420   if (!isTypeLegal(C->getType(), VT))
1421     return false;
1422
1423   // Get opcode and regclass of the output for the given load instruction.
1424   unsigned Opc = 0;
1425   const TargetRegisterClass *RC = NULL;
1426   switch (VT.getSimpleVT()) {
1427   default: return false;
1428   case MVT::i8:
1429     Opc = X86::MOV8rm;
1430     RC  = X86::GR8RegisterClass;
1431     break;
1432   case MVT::i16:
1433     Opc = X86::MOV16rm;
1434     RC  = X86::GR16RegisterClass;
1435     break;
1436   case MVT::i32:
1437     Opc = X86::MOV32rm;
1438     RC  = X86::GR32RegisterClass;
1439     break;
1440   case MVT::i64:
1441     // Must be in x86-64 mode.
1442     Opc = X86::MOV64rm;
1443     RC  = X86::GR64RegisterClass;
1444     break;
1445   case MVT::f32:
1446     if (Subtarget->hasSSE1()) {
1447       Opc = X86::MOVSSrm;
1448       RC  = X86::FR32RegisterClass;
1449     } else {
1450       Opc = X86::LD_Fp32m;
1451       RC  = X86::RFP32RegisterClass;
1452     }
1453     break;
1454   case MVT::f64:
1455     if (Subtarget->hasSSE2()) {
1456       Opc = X86::MOVSDrm;
1457       RC  = X86::FR64RegisterClass;
1458     } else {
1459       Opc = X86::LD_Fp64m;
1460       RC  = X86::RFP64RegisterClass;
1461     }
1462     break;
1463   case MVT::f80:
1464     // No f80 support yet.
1465     return false;
1466   }
1467
1468   // Materialize addresses with LEA instructions.
1469   if (isa<GlobalValue>(C)) {
1470     X86AddressMode AM;
1471     if (X86SelectAddress(C, AM, false)) {
1472       if (TLI.getPointerTy() == MVT::i32)
1473         Opc = X86::LEA32r;
1474       else
1475         Opc = X86::LEA64r;
1476       unsigned ResultReg = createResultReg(RC);
1477       addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1478       return ResultReg;
1479     }
1480     return 0;
1481   }
1482
1483   // MachineConstantPool wants an explicit alignment.
1484   unsigned Align = TD.getPrefTypeAlignment(C->getType());
1485   if (Align == 0) {
1486     // Alignment of vector types.  FIXME!
1487     Align = TD.getTypePaddedSize(C->getType());
1488   }
1489
1490   // x86-32 PIC requires a PIC base register for constant pools.
1491   unsigned PICBase = 0;
1492   if (TM.getRelocationModel() == Reloc::PIC_ &&
1493       !Subtarget->is64Bit())
1494     PICBase = getInstrInfo()->getGlobalBaseReg(&MF);
1495
1496   // Create the load from the constant pool.
1497   unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
1498   unsigned ResultReg = createResultReg(RC);
1499   addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), MCPOffset,
1500                            PICBase);
1501
1502   return ResultReg;
1503 }
1504
1505 unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
1506   // Fail on dynamic allocas. At this point, getRegForValue has already
1507   // checked its CSE maps, so if we're here trying to handle a dynamic
1508   // alloca, we're not going to succeed. X86SelectAddress has a
1509   // check for dynamic allocas, because it's called directly from
1510   // various places, but TargetMaterializeAlloca also needs a check
1511   // in order to avoid recursion between getRegForValue,
1512   // X86SelectAddrss, and TargetMaterializeAlloca.
1513   if (!StaticAllocaMap.count(C))
1514     return 0;
1515
1516   X86AddressMode AM;
1517   if (!X86SelectAddress(C, AM, false))
1518     return 0;
1519   unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
1520   TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
1521   unsigned ResultReg = createResultReg(RC);
1522   addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1523   return ResultReg;
1524 }
1525
1526 namespace llvm {
1527   llvm::FastISel *X86::createFastISel(MachineFunction &mf,
1528                         MachineModuleInfo *mmi,
1529                         DwarfWriter *dw,
1530                         DenseMap<const Value *, unsigned> &vm,
1531                         DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
1532                         DenseMap<const AllocaInst *, int> &am
1533 #ifndef NDEBUG
1534                         , SmallSet<Instruction*, 8> &cil
1535 #endif
1536                         ) {
1537     return new X86FastISel(mf, mmi, dw, vm, bm, am
1538 #ifndef NDEBUG
1539                            , cil
1540 #endif
1541                            );
1542   }
1543 }