lib/Target/PowerPC/PPCHazardRecognizers.h

   1 //===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines hazard recognizers for scheduling on PowerPC processors.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef PPCHAZRECS_H
  15 #define PPCHAZRECS_H
  16
  17 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
  18 #include "llvm/CodeGen/SelectionDAGNodes.h"
  19 #include "PPCInstrInfo.h"
  20
  21 namespace llvm {
  22
  23 /// PPCHazardRecognizer970 - This class defines a finite state automata that
  24 /// models the dispatch logic on the PowerPC 970 (aka G5) processor.  This
  25 /// promotes good dispatch group formation and implements noop insertion to
  26 /// avoid structural hazards that cause significant performance penalties (e.g.
  27 /// setting the CTR register then branching through it within a dispatch group),
  28 /// or storing then loading from the same address within a dispatch group.
  29 class PPCHazardRecognizer970 : public ScheduleHazardRecognizer {
  30   const TargetInstrInfo &TII;
  31
  32   unsigned NumIssued;  // Number of insts issued, including advanced cycles.
  33
  34   // Various things that can cause a structural hazard.
  35
  36   // HasCTRSet - If the CTR register is set in this group, disallow BCTRL.
  37   bool HasCTRSet;
  38
  39   // StoredPtr - Keep track of the address of any store.  If we see a load from
  40   // the same address (or one that aliases it), disallow the store.  We can have
  41   // up to four stores in one dispatch group, hence we track up to 4.
  42   //
  43   // This is null if we haven't seen a store yet.  We keep track of both
  44   // operands of the store here, since we support [r+r] and [r+i] addressing.
  45   SDValue StorePtr1[4], StorePtr2[4];
  46   unsigned  StoreSize[4];
  47   unsigned NumStores;
  48
  49 public:
  50   PPCHazardRecognizer970(const TargetInstrInfo &TII);
  51   virtual HazardType getHazardType(SUnit *SU);
  52   virtual void EmitInstruction(SUnit *SU);
  53   virtual void AdvanceCycle();
  54
  55 private:
  56   /// EndDispatchGroup - Called when we are finishing a new dispatch group.
  57   ///
  58   void EndDispatchGroup();
  59
  60   /// GetInstrType - Classify the specified powerpc opcode according to its
  61   /// pipeline.
  62   PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
  63                                   bool &isFirst, bool &isSingle,bool &isCracked,
  64                                   bool &isLoad, bool &isStore);
  65
  66   bool isLoadOfStoredAddress(unsigned LoadSize,
  67                              SDValue Ptr1, SDValue Ptr2) const;
  68 };
  69
  70 } // end namespace llvm
  71
  72 #endif
  73