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Hanle i8 returns
[llvm/msp430.git] / lib / Target / PowerPC / PPCRegisterInfo.cpp
blob657fc29bc6f79d878877377b94dd09e2c7dd4665
1 //===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #define DEBUG_TYPE "reginfo"
16 #include "PPC.h"
17 #include "PPCInstrBuilder.h"
18 #include "PPCMachineFunctionInfo.h"
19 #include "PPCRegisterInfo.h"
20 #include "PPCFrameInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineLocation.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/RegisterScavenging.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/ADT/BitVector.h"
42 #include "llvm/ADT/STLExtras.h"
43 #include <cstdlib>
44 using namespace llvm;
45
46 // FIXME This disables some code that aligns the stack to a boundary
47 // bigger than the default (16 bytes on Darwin) when there is a stack local
48 // of greater alignment. This does not currently work, because the delta
49 // between old and new stack pointers is added to offsets that reference
50 // incoming parameters after the prolog is generated, and the code that
51 // does that doesn't handle a variable delta. You don't want to do that
52 // anyway; a better approach is to reserve another register that retains
53 // to the incoming stack pointer, and reference parameters relative to that.
54 #define ALIGN_STACK 0
55
56 // FIXME (64-bit): Eventually enable by default.
57 cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
58 cl::init(false),
59 cl::desc("Enable PPC32 register scavenger"),
60 cl::Hidden);
61 cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
62 cl::init(false),
63 cl::desc("Enable PPC64 register scavenger"),
64 cl::Hidden);
65 #define EnableRegisterScavenging \
66 ((EnablePPC32RS && !Subtarget.isPPC64()) || \
67 (EnablePPC64RS && Subtarget.isPPC64()))
68
69 // FIXME (64-bit): Should be inlined.
70 bool
71 PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
72 return EnableRegisterScavenging;
73 }
74
75 /// getRegisterNumbering - Given the enum value for some register, e.g.
76 /// PPC::F14, return the number that it corresponds to (e.g. 14).
77 unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
78 using namespace PPC;
79 switch (RegEnum) {
80 case 0: return 0;
81 case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
82 case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
83 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
84 case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
85 case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
86 case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
87 case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
88 case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
89 case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
90 case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
91 case R10: case X10: case F10: case V10: case CR2EQ: return 10;
92 case R11: case X11: case F11: case V11: case CR2UN: return 11;
93 case R12: case X12: case F12: case V12: case CR3LT: return 12;
94 case R13: case X13: case F13: case V13: case CR3GT: return 13;
95 case R14: case X14: case F14: case V14: case CR3EQ: return 14;
96 case R15: case X15: case F15: case V15: case CR3UN: return 15;
97 case R16: case X16: case F16: case V16: case CR4LT: return 16;
98 case R17: case X17: case F17: case V17: case CR4GT: return 17;
99 case R18: case X18: case F18: case V18: case CR4EQ: return 18;
100 case R19: case X19: case F19: case V19: case CR4UN: return 19;
101 case R20: case X20: case F20: case V20: case CR5LT: return 20;
102 case R21: case X21: case F21: case V21: case CR5GT: return 21;
103 case R22: case X22: case F22: case V22: case CR5EQ: return 22;
104 case R23: case X23: case F23: case V23: case CR5UN: return 23;
105 case R24: case X24: case F24: case V24: case CR6LT: return 24;
106 case R25: case X25: case F25: case V25: case CR6GT: return 25;
107 case R26: case X26: case F26: case V26: case CR6EQ: return 26;
108 case R27: case X27: case F27: case V27: case CR6UN: return 27;
109 case R28: case X28: case F28: case V28: case CR7LT: return 28;
110 case R29: case X29: case F29: case V29: case CR7GT: return 29;
111 case R30: case X30: case F30: case V30: case CR7EQ: return 30;
112 case R31: case X31: case F31: case V31: case CR7UN: return 31;
113 default:
114 cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
115 abort();
116 }
117 }
118
119 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
120 const TargetInstrInfo &tii)
121 : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
122 Subtarget(ST), TII(tii) {
123 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
124 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
125 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
126 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
127 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
128 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
129 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
130 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
131
132 // 64-bit
133 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
134 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
135 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
136 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
137 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
138 }
139
140 /// getPointerRegClass - Return the register class to use to hold pointers.
141 /// This is used for addressing modes.
142 const TargetRegisterClass *PPCRegisterInfo::getPointerRegClass() const {
143 if (Subtarget.isPPC64())
144 return &PPC::G8RCRegClass;
145 else
146 return &PPC::GPRCRegClass;
147 }
148
149 const unsigned*
150 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
151 // 32-bit Darwin calling convention.
152 static const unsigned Macho32_CalleeSavedRegs[] = {
153 PPC::R13, PPC::R14, PPC::R15,
154 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
155 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
156 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
157 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
158
159 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
160 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
161 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
162 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
163 PPC::F30, PPC::F31,
164
165 PPC::CR2, PPC::CR3, PPC::CR4,
166 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
167 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
168 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
169
170 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
171 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
172 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
173
174 PPC::LR, 0
175 };
176
177 static const unsigned ELF32_CalleeSavedRegs[] = {
178 PPC::R13, PPC::R14, PPC::R15,
179 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
180 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
181 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
182 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
183
184 PPC::F9,
185 PPC::F10, PPC::F11, PPC::F12, PPC::F13,
186 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
187 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
188 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
189 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
190 PPC::F30, PPC::F31,
191
192 PPC::CR2, PPC::CR3, PPC::CR4,
193 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
194 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
195 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
196
197 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
198 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
199 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
200
201 PPC::LR, 0
202 };
203 // 64-bit Darwin calling convention.
204 static const unsigned Macho64_CalleeSavedRegs[] = {
205 PPC::X14, PPC::X15,
206 PPC::X16, PPC::X17, PPC::X18, PPC::X19,
207 PPC::X20, PPC::X21, PPC::X22, PPC::X23,
208 PPC::X24, PPC::X25, PPC::X26, PPC::X27,
209 PPC::X28, PPC::X29, PPC::X30, PPC::X31,
210
211 PPC::F14, PPC::F15, PPC::F16, PPC::F17,
212 PPC::F18, PPC::F19, PPC::F20, PPC::F21,
213 PPC::F22, PPC::F23, PPC::F24, PPC::F25,
214 PPC::F26, PPC::F27, PPC::F28, PPC::F29,
215 PPC::F30, PPC::F31,
216
217 PPC::CR2, PPC::CR3, PPC::CR4,
218 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
219 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
220 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
221
222 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
223 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
224 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
225
226 PPC::LR8, 0
227 };
228
229 if (Subtarget.isMachoABI())
230 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
231 Macho32_CalleeSavedRegs;
232
233 // ELF 32.
234 return ELF32_CalleeSavedRegs;
235 }
236
237 const TargetRegisterClass* const*
238 PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
239 // 32-bit Macho calling convention.
240 static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
241 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
242 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
243 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
244 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
245 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
246
247 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
248 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
249 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
250 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
251 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
252
253 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
254
255 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
256 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
257 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
258
259 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
260 &PPC::CRBITRCRegClass,
261 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
262 &PPC::CRBITRCRegClass,
263 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
264 &PPC::CRBITRCRegClass,
265
266 &PPC::GPRCRegClass, 0
267 };
268
269 static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
270 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
271 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
272 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
273 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
274 &PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
275
276 &PPC::F8RCRegClass,
277 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
278 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
279 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
280 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
281 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
282 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
283
284 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
285
286 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
287 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
288 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
289
290 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
291 &PPC::CRBITRCRegClass,
292 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
293 &PPC::CRBITRCRegClass,
294 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
295 &PPC::CRBITRCRegClass,
296
297 &PPC::GPRCRegClass, 0
298 };
299
300 // 64-bit Macho calling convention.
301 static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
302 &PPC::G8RCRegClass,&PPC::G8RCRegClass,
303 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
304 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
305 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
306 &PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
307
308 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
309 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
310 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
311 &PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
312 &PPC::F8RCRegClass,&PPC::F8RCRegClass,
313
314 &PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
315
316 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
317 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
318 &PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
319
320 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
321 &PPC::CRBITRCRegClass,
322 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
323 &PPC::CRBITRCRegClass,
324 &PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
325 &PPC::CRBITRCRegClass,
326
327 &PPC::G8RCRegClass, 0
328 };
329
330 if (Subtarget.isMachoABI())
331 return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
332 Macho32_CalleeSavedRegClasses;
333
334 // ELF 32.
335 return ELF32_CalleeSavedRegClasses;
336 }
337
338 // needsFP - Return true if the specified function should have a dedicated frame
339 // pointer register. This is true if the function has variable sized allocas or
340 // if frame pointer elimination is disabled.
341 //
342 static bool needsFP(const MachineFunction &MF) {
343 const MachineFrameInfo *MFI = MF.getFrameInfo();
344 return NoFramePointerElim || MFI->hasVarSizedObjects() ||
345 (PerformTailCallOpt && MF.getInfo<PPCFunctionInfo>()->hasFastCall());
346 }
347
348 static bool spillsCR(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->isCRSpilled();
351 }
352
353 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
354 BitVector Reserved(getNumRegs());
355 Reserved.set(PPC::R0);
356 Reserved.set(PPC::R1);
357 Reserved.set(PPC::LR);
358 Reserved.set(PPC::LR8);
359 Reserved.set(PPC::RM);
360
361 // In Linux, r2 is reserved for the OS.
362 if (!Subtarget.isDarwin())
363 Reserved.set(PPC::R2);
364
365 // On PPC64, r13 is the thread pointer. Never allocate this register. Note
366 // that this is over conservative, as it also prevents allocation of R31 when
367 // the FP is not needed.
368 if (Subtarget.isPPC64()) {
369 Reserved.set(PPC::R13);
370 Reserved.set(PPC::R31);
371
372 if (!EnableRegisterScavenging)
373 Reserved.set(PPC::R0); // FIXME (64-bit): Remove
374
375 Reserved.set(PPC::X0);
376 Reserved.set(PPC::X1);
377 Reserved.set(PPC::X13);
378 Reserved.set(PPC::X31);
379 }
380
381 if (needsFP(MF))
382 Reserved.set(PPC::R31);
383
384 return Reserved;
385 }
386
387 //===----------------------------------------------------------------------===//
388 // Stack Frame Processing methods
389 //===----------------------------------------------------------------------===//
390
391 // hasFP - Return true if the specified function actually has a dedicated frame
392 // pointer register. This is true if the function needs a frame pointer and has
393 // a non-zero stack size.
394 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
395 const MachineFrameInfo *MFI = MF.getFrameInfo();
396 return MFI->getStackSize() && needsFP(MF);
397 }
398
399 /// MustSaveLR - Return true if this function requires that we save the LR
400 /// register onto the stack in the prolog and restore it in the epilog of the
401 /// function.
402 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
403 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
404
405 // We need a save/restore of LR if there is any def of LR (which is
406 // defined by calls, including the PIC setup sequence), or if there is
407 // some use of the LR stack slot (e.g. for builtin_return_address).
408 // (LR comes in 32 and 64 bit versions.)
409 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
410 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
411 }
412
413
414
415 void PPCRegisterInfo::
416 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
417 MachineBasicBlock::iterator I) const {
418 if (PerformTailCallOpt && I->getOpcode() == PPC::ADJCALLSTACKUP) {
419 // Add (actually subtract) back the amount the callee popped on return.
420 if (int CalleeAmt = I->getOperand(1).getImm()) {
421 bool is64Bit = Subtarget.isPPC64();
422 CalleeAmt *= -1;
423 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
424 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
425 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
426 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
427 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
428 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
429 MachineInstr *MI = I;
430 DebugLoc dl = MI->getDebugLoc();
431
432 if (isInt16(CalleeAmt)) {
433 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
434 addImm(CalleeAmt);
435 } else {
436 MachineBasicBlock::iterator MBBI = I;
437 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
438 .addImm(CalleeAmt >> 16);
439 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
440 .addReg(TmpReg, false, false, true)
441 .addImm(CalleeAmt & 0xFFFF);
442 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
443 .addReg(StackReg)
444 .addReg(StackReg)
445 .addReg(TmpReg);
446 }
447 }
448 }
449 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
450 MBB.erase(I);
451 }
452
453 /// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
454 /// register first and then a spilled callee-saved register if that fails.
455 static
456 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
457 const TargetRegisterClass *RC, int SPAdj) {
458 assert(RS && "Register scavenging must be on");
459 unsigned Reg = RS->FindUnusedReg(RC, true);
460 // FIXME: move ARM callee-saved reg scan to target independent code, then
461 // search for already spilled CS register here.
462 if (Reg == 0)
463 Reg = RS->scavengeRegister(RC, II, SPAdj);
464 return Reg;
465 }
466
467 /// lowerDynamicAlloc - Generate the code for allocating an object in the
468 /// current frame. The sequence of code with be in the general form
469 ///
470 /// addi R0, SP, \#frameSize ; get the address of the previous frame
471 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
472 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
473 ///
474 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
475 int SPAdj, RegScavenger *RS) const {
476 // Get the instruction.
477 MachineInstr &MI = *II;
478 // Get the instruction's basic block.
479 MachineBasicBlock &MBB = *MI.getParent();
480 // Get the basic block's function.
481 MachineFunction &MF = *MBB.getParent();
482 // Get the frame info.
483 MachineFrameInfo *MFI = MF.getFrameInfo();
484 // Determine whether 64-bit pointers are used.
485 bool LP64 = Subtarget.isPPC64();
486 DebugLoc dl = MI.getDebugLoc();
487
488 // Get the maximum call stack size.
489 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
490 // Get the total frame size.
491 unsigned FrameSize = MFI->getStackSize();
492
493 // Get stack alignments.
494 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
495 unsigned MaxAlign = MFI->getMaxAlignment();
496 assert(MaxAlign <= TargetAlign &&
497 "Dynamic alloca with large aligns not supported");
498
499 // Determine the previous frame's address. If FrameSize can't be
500 // represented as 16 bits or we need special alignment, then we load the
501 // previous frame's address from 0(SP). Why not do an addis of the hi?
502 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
503 // Constructing the constant and adding would take 3 instructions.
504 // Fortunately, a frame greater than 32K is rare.
505 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
506 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
507 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
508
509 // FIXME (64-bit): Use "findScratchRegister"
510 unsigned Reg;
511 if (EnableRegisterScavenging)
512 Reg = findScratchRegister(II, RS, RC, SPAdj);
513 else
514 Reg = PPC::R0;
515
516 if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
517 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
518 .addReg(PPC::R31)
519 .addImm(FrameSize);
520 } else if (LP64) {
521 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
522 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
523 .addImm(0)
524 .addReg(PPC::X1);
525 else
526 BuildMI(MBB, II, dl, TII.get(PPC::LD), PPC::X0)
527 .addImm(0)
528 .addReg(PPC::X1);
529 } else {
530 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
531 .addImm(0)
532 .addReg(PPC::R1);
533 }
534
535 // Grow the stack and update the stack pointer link, then determine the
536 // address of new allocated space.
537 if (LP64) {
538 if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
539 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
540 .addReg(Reg, false, false, true)
541 .addReg(PPC::X1)
542 .addReg(MI.getOperand(1).getReg());
543 else
544 BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
545 .addReg(PPC::X0, false, false, true)
546 .addReg(PPC::X1)
547 .addReg(MI.getOperand(1).getReg());
548
549 if (!MI.getOperand(1).isKill())
550 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
551 .addReg(PPC::X1)
552 .addImm(maxCallFrameSize);
553 else
554 // Implicitly kill the register.
555 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
556 .addReg(PPC::X1)
557 .addImm(maxCallFrameSize)
558 .addReg(MI.getOperand(1).getReg(), false, true, true);
559 } else {
560 BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
561 .addReg(Reg, false, false, true)
562 .addReg(PPC::R1)
563 .addReg(MI.getOperand(1).getReg());
564
565 if (!MI.getOperand(1).isKill())
566 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
567 .addReg(PPC::R1)
568 .addImm(maxCallFrameSize);
569 else
570 // Implicitly kill the register.
571 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
572 .addReg(PPC::R1)
573 .addImm(maxCallFrameSize)
574 .addReg(MI.getOperand(1).getReg(), false, true, true);
575 }
576
577 // Discard the DYNALLOC instruction.
578 MBB.erase(II);
579 }
580
581 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
582 /// reserving a whole register (R0), we scrounge for one here. This generates
583 /// code like this:
584 ///
585 /// mfcr rA ; Move the conditional register into GPR rA.
586 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
587 /// stw rA, FI ; Store rA to the frame.
588 ///
589 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
590 unsigned FrameIndex, int SPAdj,
591 RegScavenger *RS) const {
592 // Get the instruction.
593 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
594 // Get the instruction's basic block.
595 MachineBasicBlock &MBB = *MI.getParent();
596 DebugLoc dl = MI.getDebugLoc();
597
598 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
599 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
600 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
601 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
602
603 // We need to store the CR in the low 4-bits of the saved value. First, issue
604 // an MFCR to save all of the CRBits. Add an implicit kill of the CR.
605 if (!MI.getOperand(0).isKill())
606 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg);
607 else
608 // Implicitly kill the CR register.
609 BuildMI(MBB, II, dl, TII.get(PPC::MFCR), Reg)
610 .addReg(MI.getOperand(0).getReg(), false, true, true);
611
612 // If the saved register wasn't CR0, shift the bits left so that they are in
613 // CR0's slot.
614 unsigned SrcReg = MI.getOperand(0).getReg();
615 if (SrcReg != PPC::CR0)
616 // rlwinm rA, rA, ShiftBits, 0, 31.
617 BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg)
618 .addReg(Reg, false, false, true)
619 .addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
620 .addImm(0)
621 .addImm(31);
622
623 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
624 .addReg(Reg, false, false, MI.getOperand(1).getImm()),
625 FrameIndex);
626
627 // Discard the pseudo instruction.
628 MBB.erase(II);
629 }
630
631 void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
632 int SPAdj, RegScavenger *RS) const {
633 assert(SPAdj == 0 && "Unexpected");
634
635 // Get the instruction.
636 MachineInstr &MI = *II;
637 // Get the instruction's basic block.
638 MachineBasicBlock &MBB = *MI.getParent();
639 // Get the basic block's function.
640 MachineFunction &MF = *MBB.getParent();
641 // Get the frame info.
642 MachineFrameInfo *MFI = MF.getFrameInfo();
643 DebugLoc dl = MI.getDebugLoc();
644
645 // Find out which operand is the frame index.
646 unsigned FIOperandNo = 0;
647 while (!MI.getOperand(FIOperandNo).isFI()) {
648 ++FIOperandNo;
649 assert(FIOperandNo != MI.getNumOperands() &&
650 "Instr doesn't have FrameIndex operand!");
651 }
652 // Take into account whether it's an add or mem instruction
653 unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
654 if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
655 OffsetOperandNo = FIOperandNo-1;
656
657 // Get the frame index.
658 int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
659
660 // Get the frame pointer save index. Users of this index are primarily
661 // DYNALLOC instructions.
662 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
663 int FPSI = FI->getFramePointerSaveIndex();
664 // Get the instruction opcode.
665 unsigned OpC = MI.getOpcode();
666
667 // Special case for dynamic alloca.
668 if (FPSI && FrameIndex == FPSI &&
669 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
670 lowerDynamicAlloc(II, SPAdj, RS);
671 return;
672 }
673
674 // Special case for pseudo-op SPILL_CR.
675 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
676 if (OpC == PPC::SPILL_CR) {
677 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
678 return;
679 }
680
681 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
682 MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
683 false);
684
685 // Figure out if the offset in the instruction is shifted right two bits. This
686 // is true for instructions like "STD", which the machine implicitly adds two
687 // low zeros to.
688 bool isIXAddr = false;
689 switch (OpC) {
690 case PPC::LWA:
691 case PPC::LD:
692 case PPC::STD:
693 case PPC::STD_32:
694 isIXAddr = true;
695 break;
696 }
697
698 // Now add the frame object offset to the offset from r1.
699 int Offset = MFI->getObjectOffset(FrameIndex);
700 if (!isIXAddr)
701 Offset += MI.getOperand(OffsetOperandNo).getImm();
702 else
703 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
704
705 // If we're not using a Frame Pointer that has been set to the value of the
706 // SP before having the stack size subtracted from it, then add the stack size
707 // to Offset to get the correct offset.
708 Offset += MFI->getStackSize();
709
710 // If we can, encode the offset directly into the instruction. If this is a
711 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
712 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
713 // clear can be encoded. This is extremely uncommon, because normally you
714 // only "std" to a stack slot that is at least 4-byte aligned, but it can
715 // happen in invalid code.
716 if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
717 if (isIXAddr)
718 Offset >>= 2; // The actual encoded value has the low two bits zero.
719 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
720 return;
721 }
722
723 // The offset doesn't fit into a single register, scavenge one to build the
724 // offset in.
725 // FIXME: figure out what SPAdj is doing here.
726
727 // FIXME (64-bit): Use "findScratchRegister".
728 unsigned SReg;
729 if (EnableRegisterScavenging)
730 SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
731 else
732 SReg = PPC::R0;
733
734 // Insert a set of rA with the full offset value before the ld, st, or add
735 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
736 .addImm(Offset >> 16);
737 BuildMI(MBB, II, dl, TII.get(PPC::ORI), SReg)
738 .addReg(SReg, false, false, true)
739 .addImm(Offset);
740
741 // Convert into indexed form of the instruction:
742 //
743 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
744 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
745 unsigned OperandBase;
746
747 if (OpC != TargetInstrInfo::INLINEASM) {
748 assert(ImmToIdxMap.count(OpC) &&
749 "No indexed form of load or store available!");
750 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
751 MI.setDesc(TII.get(NewOpcode));
752 OperandBase = 1;
753 } else {
754 OperandBase = OffsetOperandNo;
755 }
756
757 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
758 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
759 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
760 }
761
762 /// VRRegNo - Map from a numbered VR register to its enum value.
763 ///
764 static const unsigned short VRRegNo[] = {
765 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
766 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
767 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
768 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
769 };
770
771 /// RemoveVRSaveCode - We have found that this function does not need any code
772 /// to manipulate the VRSAVE register, even though it uses vector registers.
773 /// This can happen when the only registers used are known to be live in or out
774 /// of the function. Remove all of the VRSAVE related code from the function.
775 static void RemoveVRSaveCode(MachineInstr *MI) {
776 MachineBasicBlock *Entry = MI->getParent();
777 MachineFunction *MF = Entry->getParent();
778
779 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
780 MachineBasicBlock::iterator MBBI = MI;
781 ++MBBI;
782 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
783 MBBI->eraseFromParent();
784
785 bool RemovedAllMTVRSAVEs = true;
786 // See if we can find and remove the MTVRSAVE instruction from all of the
787 // epilog blocks.
788 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
789 // If last instruction is a return instruction, add an epilogue
790 if (!I->empty() && I->back().getDesc().isReturn()) {
791 bool FoundIt = false;
792 for (MBBI = I->end(); MBBI != I->begin(); ) {
793 --MBBI;
794 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
795 MBBI->eraseFromParent(); // remove it.
796 FoundIt = true;
797 break;
798 }
799 }
800 RemovedAllMTVRSAVEs &= FoundIt;
801 }
802 }
803
804 // If we found and removed all MTVRSAVE instructions, remove the read of
805 // VRSAVE as well.
806 if (RemovedAllMTVRSAVEs) {
807 MBBI = MI;
808 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
809 --MBBI;
810 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
811 MBBI->eraseFromParent();
812 }
813
814 // Finally, nuke the UPDATE_VRSAVE.
815 MI->eraseFromParent();
816 }
817
818 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
819 // instruction selector. Based on the vector registers that have been used,
820 // transform this into the appropriate ORI instruction.
821 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
822 MachineFunction *MF = MI->getParent()->getParent();
823 DebugLoc dl = MI->getDebugLoc();
824
825 unsigned UsedRegMask = 0;
826 for (unsigned i = 0; i != 32; ++i)
827 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
828 UsedRegMask |= 1 << (31-i);
829
830 // Live in and live out values already must be in the mask, so don't bother
831 // marking them.
832 for (MachineRegisterInfo::livein_iterator
833 I = MF->getRegInfo().livein_begin(),
834 E = MF->getRegInfo().livein_end(); I != E; ++I) {
835 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
836 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
837 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
838 }
839 for (MachineRegisterInfo::liveout_iterator
840 I = MF->getRegInfo().liveout_begin(),
841 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
842 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
843 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
844 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
845 }
846
847 // If no registers are used, turn this into a copy.
848 if (UsedRegMask == 0) {
849 // Remove all VRSAVE code.
850 RemoveVRSaveCode(MI);
851 return;
852 }
853
854 unsigned SrcReg = MI->getOperand(1).getReg();
855 unsigned DstReg = MI->getOperand(0).getReg();
856
857 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
858 if (DstReg != SrcReg)
859 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
860 .addReg(SrcReg)
861 .addImm(UsedRegMask);
862 else
863 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
864 .addReg(SrcReg, false, false, true)
865 .addImm(UsedRegMask);
866 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
867 if (DstReg != SrcReg)
868 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
869 .addReg(SrcReg)
870 .addImm(UsedRegMask >> 16);
871 else
872 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
873 .addReg(SrcReg, false, false, true)
874 .addImm(UsedRegMask >> 16);
875 } else {
876 if (DstReg != SrcReg)
877 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
878 .addReg(SrcReg)
879 .addImm(UsedRegMask >> 16);
880 else
881 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
882 .addReg(SrcReg, false, false, true)
883 .addImm(UsedRegMask >> 16);
884
885 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
886 .addReg(DstReg, false, false, true)
887 .addImm(UsedRegMask & 0xFFFF);
888 }
889
890 // Remove the old UPDATE_VRSAVE instruction.
891 MI->eraseFromParent();
892 }
893
894 /// determineFrameLayout - Determine the size of the frame and maximum call
895 /// frame size.
896 void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
897 MachineFrameInfo *MFI = MF.getFrameInfo();
898
899 // Get the number of bytes to allocate from the FrameInfo
900 unsigned FrameSize = MFI->getStackSize();
901
902 // Get the alignments provided by the target, and the maximum alignment
903 // (if any) of the fixed frame objects.
904 unsigned MaxAlign = MFI->getMaxAlignment();
905 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
906 unsigned AlignMask = TargetAlign - 1; //
907
908 // If we are a leaf function, and use up to 224 bytes of stack space,
909 // don't have a frame pointer, calls, or dynamic alloca then we do not need
910 // to adjust the stack pointer (we fit in the Red Zone).
911 if (!DisableRedZone &&
912 FrameSize <= 224 && // Fits in red zone.
913 !MFI->hasVarSizedObjects() && // No dynamic alloca.
914 !MFI->hasCalls() && // No calls.
915 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
916 // No need for frame
917 MFI->setStackSize(0);
918 return;
919 }
920
921 // Get the maximum call frame size of all the calls.
922 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
923
924 // Maximum call frame needs to be at least big enough for linkage and 8 args.
925 unsigned minCallFrameSize =
926 PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
927 Subtarget.isMachoABI());
928 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
929
930 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
931 // that allocations will be aligned.
932 if (MFI->hasVarSizedObjects())
933 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
934
935 // Update maximum call frame size.
936 MFI->setMaxCallFrameSize(maxCallFrameSize);
937
938 // Include call frame size in total.
939 FrameSize += maxCallFrameSize;
940
941 // Make sure the frame is aligned.
942 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
943
944 // Update frame info.
945 MFI->setStackSize(FrameSize);
946 }
947
948 void
949 PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
950 RegScavenger *RS) const {
951 // Save and clear the LR state.
952 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
953 unsigned LR = getRARegister();
954 FI->setMustSaveLR(MustSaveLR(MF, LR));
955 MF.getRegInfo().setPhysRegUnused(LR);
956
957 // Save R31 if necessary
958 int FPSI = FI->getFramePointerSaveIndex();
959 bool IsPPC64 = Subtarget.isPPC64();
960 bool IsELF32_ABI = Subtarget.isELF32_ABI();
961 bool IsMachoABI = Subtarget.isMachoABI();
962 MachineFrameInfo *MFI = MF.getFrameInfo();
963
964 // If the frame pointer save index hasn't been defined yet.
965 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
966 IsELF32_ABI) {
967 // Find out what the fix offset of the frame pointer save area.
968 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
969 IsMachoABI);
970 // Allocate the frame index for frame pointer save area.
971 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
972 // Save the result.
973 FI->setFramePointerSaveIndex(FPSI);
974 }
975
976 // Reserve stack space to move the linkage area to in case of a tail call.
977 int TCSPDelta = 0;
978 if (PerformTailCallOpt && (TCSPDelta=FI->getTailCallSPDelta()) < 0) {
979 int AddFPOffsetAmount = IsELF32_ABI ? -4 : 0;
980 MF.getFrameInfo()->CreateFixedObject( -1 * TCSPDelta,
981 AddFPOffsetAmount + TCSPDelta);
982 }
983 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
984 // a large stack, which will require scavenging a register to materialize a
985 // large offset.
986 // FIXME: this doesn't actually check stack size, so is a bit pessimistic
987 // FIXME: doesn't detect whether or not we need to spill vXX, which requires
988 // r0 for now.
989
990 if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
991 if (needsFP(MF) || spillsCR(MF)) {
992 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
993 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
994 const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
995 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
996 RC->getAlignment()));
997 }
998 }
999
1000 void
1001 PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
1002 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
1003 MachineBasicBlock::iterator MBBI = MBB.begin();
1004 MachineFrameInfo *MFI = MF.getFrameInfo();
1005 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
1006 DebugLoc dl = DebugLoc::getUnknownLoc();
1007 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
1008 !MF.getFunction()->doesNotThrow() ||
1009 UnwindTablesMandatory;
1010
1011 // Prepare for frame info.
1012 unsigned FrameLabelId = 0;
1013
1014 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
1015 // process it.
1016 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
1017 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
1018 HandleVRSaveUpdate(MBBI, TII);
1019 break;
1020 }
1021 }
1022
1023 // Move MBBI back to the beginning of the function.
1024 MBBI = MBB.begin();
1025
1026 // Work out frame sizes.
1027 determineFrameLayout(MF);
1028 unsigned FrameSize = MFI->getStackSize();
1029
1030 int NegFrameSize = -FrameSize;
1031
1032 // Get processor type.
1033 bool IsPPC64 = Subtarget.isPPC64();
1034 // Get operating system
1035 bool IsMachoABI = Subtarget.isMachoABI();
1036 // Check if the link register (LR) must be saved.
1037 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1038 bool MustSaveLR = FI->mustSaveLR();
1039 // Do we have a frame pointer for this function?
1040 bool HasFP = hasFP(MF) && FrameSize;
1041
1042 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1043 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1044
1045 if (IsPPC64) {
1046 if (MustSaveLR)
1047 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
1048
1049 if (HasFP)
1050 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1051 .addReg(PPC::X31)
1052 .addImm(FPOffset/4)
1053 .addReg(PPC::X1);
1054
1055 if (MustSaveLR)
1056 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
1057 .addReg(PPC::X0)
1058 .addImm(LROffset / 4)
1059 .addReg(PPC::X1);
1060 } else {
1061 if (MustSaveLR)
1062 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
1063
1064 if (HasFP)
1065 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1066 .addReg(PPC::R31)
1067 .addImm(FPOffset)
1068 .addReg(PPC::R1);
1069
1070 if (MustSaveLR)
1071 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
1072 .addReg(PPC::R0)
1073 .addImm(LROffset)
1074 .addReg(PPC::R1);
1075 }
1076
1077 // Skip if a leaf routine.
1078 if (!FrameSize) return;
1079
1080 // Get stack alignments.
1081 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1082 unsigned MaxAlign = MFI->getMaxAlignment();
1083
1084 if (needsFrameMoves) {
1085 // Mark effective beginning of when frame pointer becomes valid.
1086 FrameLabelId = MMI->NextLabelID();
1087 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
1088 }
1089
1090 // Adjust stack pointer: r1 += NegFrameSize.
1091 // If there is a preferred stack alignment, align R1 now
1092 if (!IsPPC64) {
1093 // PPC32.
1094 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1095 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1096 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1097
1098 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
1099 .addReg(PPC::R1)
1100 .addImm(0)
1101 .addImm(32 - Log2_32(MaxAlign))
1102 .addImm(31);
1103 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
1104 .addReg(PPC::R0, false, false, true)
1105 .addImm(NegFrameSize);
1106 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1107 .addReg(PPC::R1)
1108 .addReg(PPC::R1)
1109 .addReg(PPC::R0);
1110 } else if (isInt16(NegFrameSize)) {
1111 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
1112 .addReg(PPC::R1)
1113 .addImm(NegFrameSize)
1114 .addReg(PPC::R1);
1115 } else {
1116 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1117 .addImm(NegFrameSize >> 16);
1118 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1119 .addReg(PPC::R0, false, false, true)
1120 .addImm(NegFrameSize & 0xFFFF);
1121 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX))
1122 .addReg(PPC::R1)
1123 .addReg(PPC::R1)
1124 .addReg(PPC::R0);
1125 }
1126 } else { // PPC64.
1127 if (ALIGN_STACK && MaxAlign > TargetAlign) {
1128 assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
1129 assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
1130
1131 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
1132 .addReg(PPC::X1)
1133 .addImm(0)
1134 .addImm(64 - Log2_32(MaxAlign));
1135 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
1136 .addReg(PPC::X0)
1137 .addImm(NegFrameSize);
1138 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1139 .addReg(PPC::X1)
1140 .addReg(PPC::X1)
1141 .addReg(PPC::X0);
1142 } else if (isInt16(NegFrameSize)) {
1143 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
1144 .addReg(PPC::X1)
1145 .addImm(NegFrameSize / 4)
1146 .addReg(PPC::X1);
1147 } else {
1148 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1149 .addImm(NegFrameSize >> 16);
1150 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1151 .addReg(PPC::X0, false, false, true)
1152 .addImm(NegFrameSize & 0xFFFF);
1153 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX))
1154 .addReg(PPC::X1)
1155 .addReg(PPC::X1)
1156 .addReg(PPC::X0);
1157 }
1158 }
1159
1160 if (needsFrameMoves) {
1161 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
1162
1163 if (NegFrameSize) {
1164 // Show update of SP.
1165 MachineLocation SPDst(MachineLocation::VirtualFP);
1166 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
1167 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
1168 } else {
1169 MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
1170 Moves.push_back(MachineMove(FrameLabelId, SP, SP));
1171 }
1172
1173 if (HasFP) {
1174 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
1175 MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
1176 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1177 }
1178
1179 // Add callee saved registers to move list.
1180 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1181 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
1182 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
1183 unsigned Reg = CSI[I].getReg();
1184 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
1185 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
1186 MachineLocation CSSrc(Reg);
1187 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
1188 }
1189
1190 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
1191 MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
1192 Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
1193
1194 // Mark effective beginning of when frame pointer is ready.
1195 unsigned ReadyLabelId = MMI->NextLabelID();
1196 BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
1197
1198 MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
1199 (IsPPC64 ? PPC::X1 : PPC::R1));
1200 MachineLocation FPSrc(MachineLocation::VirtualFP);
1201 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
1202 }
1203
1204 // If there is a frame pointer, copy R1 into R31
1205 if (HasFP) {
1206 if (!IsPPC64) {
1207 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
1208 .addReg(PPC::R1)
1209 .addReg(PPC::R1);
1210 } else {
1211 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
1212 .addReg(PPC::X1)
1213 .addReg(PPC::X1);
1214 }
1215 }
1216 }
1217
1218 void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
1219 MachineBasicBlock &MBB) const {
1220 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1221 unsigned RetOpcode = MBBI->getOpcode();
1222 DebugLoc dl = DebugLoc::getUnknownLoc();
1223
1224 assert( (RetOpcode == PPC::BLR ||
1225 RetOpcode == PPC::TCRETURNri ||
1226 RetOpcode == PPC::TCRETURNdi ||
1227 RetOpcode == PPC::TCRETURNai ||
1228 RetOpcode == PPC::TCRETURNri8 ||
1229 RetOpcode == PPC::TCRETURNdi8 ||
1230 RetOpcode == PPC::TCRETURNai8) &&
1231 "Can only insert epilog into returning blocks");
1232
1233 // Get alignment info so we know how to restore r1
1234 const MachineFrameInfo *MFI = MF.getFrameInfo();
1235 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1236 unsigned MaxAlign = MFI->getMaxAlignment();
1237
1238 // Get the number of bytes allocated from the FrameInfo.
1239 int FrameSize = MFI->getStackSize();
1240
1241 // Get processor type.
1242 bool IsPPC64 = Subtarget.isPPC64();
1243 // Get operating system
1244 bool IsMachoABI = Subtarget.isMachoABI();
1245 // Check if the link register (LR) has been saved.
1246 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1247 bool MustSaveLR = FI->mustSaveLR();
1248 // Do we have a frame pointer for this function?
1249 bool HasFP = hasFP(MF) && FrameSize;
1250
1251 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
1252 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
1253
1254 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1255 RetOpcode == PPC::TCRETURNdi ||
1256 RetOpcode == PPC::TCRETURNai ||
1257 RetOpcode == PPC::TCRETURNri8 ||
1258 RetOpcode == PPC::TCRETURNdi8 ||
1259 RetOpcode == PPC::TCRETURNai8;
1260
1261 if (UsesTCRet) {
1262 int MaxTCRetDelta = FI->getTailCallSPDelta();
1263 MachineOperand &StackAdjust = MBBI->getOperand(1);
1264 assert(StackAdjust.isImm() && "Expecting immediate value.");
1265 // Adjust stack pointer.
1266 int StackAdj = StackAdjust.getImm();
1267 int Delta = StackAdj - MaxTCRetDelta;
1268 assert((Delta >= 0) && "Delta must be positive");
1269 if (MaxTCRetDelta>0)
1270 FrameSize += (StackAdj +Delta);
1271 else
1272 FrameSize += StackAdj;
1273 }
1274
1275 if (FrameSize) {
1276 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
1277 // on entry to the function. Add this offset back now.
1278 if (!IsPPC64) {
1279 // If this function contained a fastcc call and PerformTailCallOpt is
1280 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
1281 // call which invalidates the stack pointer value in SP(0). So we use the
1282 // value of R31 in this case.
1283 if (FI->hasFastCall() && isInt16(FrameSize)) {
1284 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1285 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1286 .addReg(PPC::R31).addImm(FrameSize);
1287 } else if(FI->hasFastCall()) {
1288 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
1289 .addImm(FrameSize >> 16);
1290 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
1291 .addReg(PPC::R0, false, false, true)
1292 .addImm(FrameSize & 0xFFFF);
1293 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
1294 .addReg(PPC::R1)
1295 .addReg(PPC::R31)
1296 .addReg(PPC::R0);
1297 } else if (isInt16(FrameSize) &&
1298 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
1299 !MFI->hasVarSizedObjects()) {
1300 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
1301 .addReg(PPC::R1).addImm(FrameSize);
1302 } else {
1303 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
1304 .addImm(0).addReg(PPC::R1);
1305 }
1306 } else {
1307 if (FI->hasFastCall() && isInt16(FrameSize)) {
1308 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
1309 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1310 .addReg(PPC::X31).addImm(FrameSize);
1311 } else if(FI->hasFastCall()) {
1312 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
1313 .addImm(FrameSize >> 16);
1314 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
1315 .addReg(PPC::X0, false, false, true)
1316 .addImm(FrameSize & 0xFFFF);
1317 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
1318 .addReg(PPC::X1)
1319 .addReg(PPC::X31)
1320 .addReg(PPC::X0);
1321 } else if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
1322 !MFI->hasVarSizedObjects()) {
1323 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
1324 .addReg(PPC::X1).addImm(FrameSize);
1325 } else {
1326 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
1327 .addImm(0).addReg(PPC::X1);
1328 }
1329 }
1330 }
1331
1332 if (IsPPC64) {
1333 if (MustSaveLR)
1334 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
1335 .addImm(LROffset/4).addReg(PPC::X1);
1336
1337 if (HasFP)
1338 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
1339 .addImm(FPOffset/4).addReg(PPC::X1);
1340
1341 if (MustSaveLR)
1342 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
1343 } else {
1344 if (MustSaveLR)
1345 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
1346 .addImm(LROffset).addReg(PPC::R1);
1347
1348 if (HasFP)
1349 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
1350 .addImm(FPOffset).addReg(PPC::R1);
1351
1352 if (MustSaveLR)
1353 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
1354 }
1355
1356 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
1357 // call optimization
1358 if (PerformTailCallOpt && RetOpcode == PPC::BLR &&
1359 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1360 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1361 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
1362 unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1;
1363 unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31;
1364 unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0;
1365 unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI;
1366 unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4;
1367 unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS;
1368 unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
1369
1370 if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
1371 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
1372 .addReg(StackReg).addImm(CallerAllocatedAmt);
1373 } else {
1374 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1375 .addImm(CallerAllocatedAmt >> 16);
1376 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1377 .addReg(TmpReg, false, false, true)
1378 .addImm(CallerAllocatedAmt & 0xFFFF);
1379 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
1380 .addReg(StackReg)
1381 .addReg(FPReg)
1382 .addReg(TmpReg);
1383 }
1384 } else if (RetOpcode == PPC::TCRETURNdi) {
1385 MBBI = prior(MBB.end());
1386 MachineOperand &JumpTarget = MBBI->getOperand(0);
1387 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1388 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1389 } else if (RetOpcode == PPC::TCRETURNri) {
1390 MBBI = prior(MBB.end());
1391 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1392 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1393 } else if (RetOpcode == PPC::TCRETURNai) {
1394 MBBI = prior(MBB.end());
1395 MachineOperand &JumpTarget = MBBI->getOperand(0);
1396 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1397 } else if (RetOpcode == PPC::TCRETURNdi8) {
1398 MBBI = prior(MBB.end());
1399 MachineOperand &JumpTarget = MBBI->getOperand(0);
1400 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1401 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1402 } else if (RetOpcode == PPC::TCRETURNri8) {
1403 MBBI = prior(MBB.end());
1404 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1405 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1406 } else if (RetOpcode == PPC::TCRETURNai8) {
1407 MBBI = prior(MBB.end());
1408 MachineOperand &JumpTarget = MBBI->getOperand(0);
1409 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1410 }
1411 }
1412
1413 unsigned PPCRegisterInfo::getRARegister() const {
1414 return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
1415 }
1416
1417 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1418 if (!Subtarget.isPPC64())
1419 return hasFP(MF) ? PPC::R31 : PPC::R1;
1420 else
1421 return hasFP(MF) ? PPC::X31 : PPC::X1;
1422 }
1423
1424 void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1425 const {
1426 // Initial state of the frame pointer is R1.
1427 MachineLocation Dst(MachineLocation::VirtualFP);
1428 MachineLocation Src(PPC::R1, 0);
1429 Moves.push_back(MachineMove(0, Dst, Src));
1430 }
1431
1432 unsigned PPCRegisterInfo::getEHExceptionRegister() const {
1433 return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
1434 }
1435
1436 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
1437 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
1438 }
1439
1440 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1441 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
1442 return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1443 }
1444
1445 #include "PPCGenRegisterInfo.inc"
1446
Fork for MSP430 backend development