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Hanle i8 returns
[llvm/msp430.git] / lib / Target / X86 / X86FloatingPoint.cpp
blob0f2fbcc986946a6becb6a2b6d2baba0c95986d8c
1 //===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the pass which converts floating point instructions from
11 // virtual registers into register stack instructions. This pass uses live
12 // variable information to indicate where the FPn registers are used and their
13 // lifetimes.
14 //
15 // This pass is hampered by the lack of decent CFG manipulation routines for
16 // machine code. In particular, this wants to be able to split critical edges
17 // as necessary, traverse the machine basic block CFG in depth-first order, and
18 // allow there to be multiple machine basic blocks for each LLVM basicblock
19 // (needed for critical edge splitting).
20 //
21 // In particular, this pass currently barfs on critical edges. Because of this,
22 // it requires the instruction selector to insert FP_REG_KILL instructions on
23 // the exits of any basic block that has critical edges going from it, or which
24 // branch to a critical basic block.
25 //
26 // FIXME: this is not implemented yet. The stackifier pass only works on local
27 // basic blocks.
28 //
29 //===----------------------------------------------------------------------===//
30
31 #define DEBUG_TYPE "x86-codegen"
32 #include "X86.h"
33 #include "X86InstrInfo.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetMachine.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/ADT/DepthFirstIterator.h"
43 #include "llvm/ADT/SmallPtrSet.h"
44 #include "llvm/ADT/SmallVector.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/STLExtras.h"
47 #include <algorithm>
48 using namespace llvm;
49
50 STATISTIC(NumFXCH, "Number of fxch instructions inserted");
51 STATISTIC(NumFP , "Number of floating point instructions");
52
53 namespace {
54 struct VISIBILITY_HIDDEN FPS : public MachineFunctionPass {
55 static char ID;
56 FPS() : MachineFunctionPass(&ID) {}
57
58 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addPreservedID(MachineLoopInfoID);
60 AU.addPreservedID(MachineDominatorsID);
61 MachineFunctionPass::getAnalysisUsage(AU);
62 }
63
64 virtual bool runOnMachineFunction(MachineFunction &MF);
65
66 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
67
68 private:
69 const TargetInstrInfo *TII; // Machine instruction info.
70 MachineBasicBlock *MBB; // Current basic block
71 unsigned Stack[8]; // FP<n> Registers in each stack slot...
72 unsigned RegMap[8]; // Track which stack slot contains each register
73 unsigned StackTop; // The current top of the FP stack.
74
75 void dumpStack() const {
76 cerr << "Stack contents:";
77 for (unsigned i = 0; i != StackTop; ++i) {
78 cerr << " FP" << Stack[i];
79 assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
80 }
81 cerr << "\n";
82 }
83 private:
84 /// isStackEmpty - Return true if the FP stack is empty.
85 bool isStackEmpty() const {
86 return StackTop == 0;
87 }
88
89 // getSlot - Return the stack slot number a particular register number is
90 // in.
91 unsigned getSlot(unsigned RegNo) const {
92 assert(RegNo < 8 && "Regno out of range!");
93 return RegMap[RegNo];
94 }
95
96 // getStackEntry - Return the X86::FP<n> register in register ST(i).
97 unsigned getStackEntry(unsigned STi) const {
98 assert(STi < StackTop && "Access past stack top!");
99 return Stack[StackTop-1-STi];
100 }
101
102 // getSTReg - Return the X86::ST(i) register which contains the specified
103 // FP<RegNo> register.
104 unsigned getSTReg(unsigned RegNo) const {
105 return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
106 }
107
108 // pushReg - Push the specified FP<n> register onto the stack.
109 void pushReg(unsigned Reg) {
110 assert(Reg < 8 && "Register number out of range!");
111 assert(StackTop < 8 && "Stack overflow!");
112 Stack[StackTop] = Reg;
113 RegMap[Reg] = StackTop++;
114 }
115
116 bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
117 void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) {
118 MachineInstr *MI = I;
119 DebugLoc dl = MI->getDebugLoc();
120 if (isAtTop(RegNo)) return;
121
122 unsigned STReg = getSTReg(RegNo);
123 unsigned RegOnTop = getStackEntry(0);
124
125 // Swap the slots the regs are in.
126 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
127
128 // Swap stack slot contents.
129 assert(RegMap[RegOnTop] < StackTop);
130 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
131
132 // Emit an fxch to update the runtime processors version of the state.
133 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
134 NumFXCH++;
135 }
136
137 void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
138 DebugLoc dl = I->getDebugLoc();
139 unsigned STReg = getSTReg(RegNo);
140 pushReg(AsReg); // New register on top of stack
141
142 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
143 }
144
145 // popStackAfter - Pop the current value off of the top of the FP stack
146 // after the specified instruction.
147 void popStackAfter(MachineBasicBlock::iterator &I);
148
149 // freeStackSlotAfter - Free the specified register from the register stack,
150 // so that it is no longer in a register. If the register is currently at
151 // the top of the stack, we just pop the current instruction, otherwise we
152 // store the current top-of-stack into the specified slot, then pop the top
153 // of stack.
154 void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg);
155
156 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
157
158 void handleZeroArgFP(MachineBasicBlock::iterator &I);
159 void handleOneArgFP(MachineBasicBlock::iterator &I);
160 void handleOneArgFPRW(MachineBasicBlock::iterator &I);
161 void handleTwoArgFP(MachineBasicBlock::iterator &I);
162 void handleCompareFP(MachineBasicBlock::iterator &I);
163 void handleCondMovFP(MachineBasicBlock::iterator &I);
164 void handleSpecialFP(MachineBasicBlock::iterator &I);
165 };
166 char FPS::ID = 0;
167 }
168
169 FunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); }
170
171 /// getFPReg - Return the X86::FPx register number for the specified operand.
172 /// For example, this returns 3 for X86::FP3.
173 static unsigned getFPReg(const MachineOperand &MO) {
174 assert(MO.isReg() && "Expected an FP register!");
175 unsigned Reg = MO.getReg();
176 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
177 return Reg - X86::FP0;
178 }
179
180
181 /// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
182 /// register references into FP stack references.
183 ///
184 bool FPS::runOnMachineFunction(MachineFunction &MF) {
185 // We only need to run this pass if there are any FP registers used in this
186 // function. If it is all integer, there is nothing for us to do!
187 bool FPIsUsed = false;
188
189 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
190 for (unsigned i = 0; i <= 6; ++i)
191 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
192 FPIsUsed = true;
193 break;
194 }
195
196 // Early exit.
197 if (!FPIsUsed) return false;
198
199 TII = MF.getTarget().getInstrInfo();
200 StackTop = 0;
201
202 // Process the function in depth first order so that we process at least one
203 // of the predecessors for every reachable block in the function.
204 SmallPtrSet<MachineBasicBlock*, 8> Processed;
205 MachineBasicBlock *Entry = MF.begin();
206
207 bool Changed = false;
208 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> >
209 I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed);
210 I != E; ++I)
211 Changed |= processBasicBlock(MF, **I);
212
213 return Changed;
214 }
215
216 /// processBasicBlock - Loop over all of the instructions in the basic block,
217 /// transforming FP instructions into their stack form.
218 ///
219 bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
220 bool Changed = false;
221 MBB = &BB;
222
223 for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
224 MachineInstr *MI = I;
225 unsigned Flags = MI->getDesc().TSFlags;
226
227 unsigned FPInstClass = Flags & X86II::FPTypeMask;
228 if (MI->getOpcode() == TargetInstrInfo::INLINEASM)
229 FPInstClass = X86II::SpecialFP;
230
231 if (FPInstClass == X86II::NotFP)
232 continue; // Efficiently ignore non-fp insts!
233
234 MachineInstr *PrevMI = 0;
235 if (I != BB.begin())
236 PrevMI = prior(I);
237
238 ++NumFP; // Keep track of # of pseudo instrs
239 DOUT << "\nFPInst:\t" << *MI;
240
241 // Get dead variables list now because the MI pointer may be deleted as part
242 // of processing!
243 SmallVector<unsigned, 8> DeadRegs;
244 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
245 const MachineOperand &MO = MI->getOperand(i);
246 if (MO.isReg() && MO.isDead())
247 DeadRegs.push_back(MO.getReg());
248 }
249
250 switch (FPInstClass) {
251 case X86II::ZeroArgFP: handleZeroArgFP(I); break;
252 case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0)
253 case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0))
254 case X86II::TwoArgFP: handleTwoArgFP(I); break;
255 case X86II::CompareFP: handleCompareFP(I); break;
256 case X86II::CondMovFP: handleCondMovFP(I); break;
257 case X86II::SpecialFP: handleSpecialFP(I); break;
258 default: assert(0 && "Unknown FP Type!");
259 }
260
261 // Check to see if any of the values defined by this instruction are dead
262 // after definition. If so, pop them.
263 for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
264 unsigned Reg = DeadRegs[i];
265 if (Reg >= X86::FP0 && Reg <= X86::FP6) {
266 DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
267 freeStackSlotAfter(I, Reg-X86::FP0);
268 }
269 }
270
271 // Print out all of the instructions expanded to if -debug
272 DEBUG(
273 MachineBasicBlock::iterator PrevI(PrevMI);
274 if (I == PrevI) {
275 cerr << "Just deleted pseudo instruction\n";
276 } else {
277 MachineBasicBlock::iterator Start = I;
278 // Rewind to first instruction newly inserted.
279 while (Start != BB.begin() && prior(Start) != PrevI) --Start;
280 cerr << "Inserted instructions:\n\t";
281 Start->print(*cerr.stream(), &MF.getTarget());
282 while (++Start != next(I)) {}
283 }
284 dumpStack();
285 );
286
287 Changed = true;
288 }
289
290 assert(isStackEmpty() && "Stack not empty at end of basic block?");
291 return Changed;
292 }
293
294 //===----------------------------------------------------------------------===//
295 // Efficient Lookup Table Support
296 //===----------------------------------------------------------------------===//
297
298 namespace {
299 struct TableEntry {
300 unsigned from;
301 unsigned to;
302 bool operator<(const TableEntry &TE) const { return from < TE.from; }
303 friend bool operator<(const TableEntry &TE, unsigned V) {
304 return TE.from < V;
305 }
306 friend bool operator<(unsigned V, const TableEntry &TE) {
307 return V < TE.from;
308 }
309 };
310 }
311
312 #ifndef NDEBUG
313 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
314 for (unsigned i = 0; i != NumEntries-1; ++i)
315 if (!(Table[i] < Table[i+1])) return false;
316 return true;
317 }
318 #endif
319
320 static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
321 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
322 if (I != Table+N && I->from == Opcode)
323 return I->to;
324 return -1;
325 }
326
327 #ifdef NDEBUG
328 #define ASSERT_SORTED(TABLE)
329 #else
330 #define ASSERT_SORTED(TABLE) \
331 { static bool TABLE##Checked = false; \
332 if (!TABLE##Checked) { \
333 assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \
334 "All lookup tables must be sorted for efficient access!"); \
335 TABLE##Checked = true; \
336 } \
337 }
338 #endif
339
340 //===----------------------------------------------------------------------===//
341 // Register File -> Register Stack Mapping Methods
342 //===----------------------------------------------------------------------===//
343
344 // OpcodeTable - Sorted map of register instructions to their stack version.
345 // The first element is an register file pseudo instruction, the second is the
346 // concrete X86 instruction which uses the register stack.
347 //
348 static const TableEntry OpcodeTable[] = {
349 { X86::ABS_Fp32 , X86::ABS_F },
350 { X86::ABS_Fp64 , X86::ABS_F },
351 { X86::ABS_Fp80 , X86::ABS_F },
352 { X86::ADD_Fp32m , X86::ADD_F32m },
353 { X86::ADD_Fp64m , X86::ADD_F64m },
354 { X86::ADD_Fp64m32 , X86::ADD_F32m },
355 { X86::ADD_Fp80m32 , X86::ADD_F32m },
356 { X86::ADD_Fp80m64 , X86::ADD_F64m },
357 { X86::ADD_FpI16m32 , X86::ADD_FI16m },
358 { X86::ADD_FpI16m64 , X86::ADD_FI16m },
359 { X86::ADD_FpI16m80 , X86::ADD_FI16m },
360 { X86::ADD_FpI32m32 , X86::ADD_FI32m },
361 { X86::ADD_FpI32m64 , X86::ADD_FI32m },
362 { X86::ADD_FpI32m80 , X86::ADD_FI32m },
363 { X86::CHS_Fp32 , X86::CHS_F },
364 { X86::CHS_Fp64 , X86::CHS_F },
365 { X86::CHS_Fp80 , X86::CHS_F },
366 { X86::CMOVBE_Fp32 , X86::CMOVBE_F },
367 { X86::CMOVBE_Fp64 , X86::CMOVBE_F },
368 { X86::CMOVBE_Fp80 , X86::CMOVBE_F },
369 { X86::CMOVB_Fp32 , X86::CMOVB_F },
370 { X86::CMOVB_Fp64 , X86::CMOVB_F },
371 { X86::CMOVB_Fp80 , X86::CMOVB_F },
372 { X86::CMOVE_Fp32 , X86::CMOVE_F },
373 { X86::CMOVE_Fp64 , X86::CMOVE_F },
374 { X86::CMOVE_Fp80 , X86::CMOVE_F },
375 { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F },
376 { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F },
377 { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F },
378 { X86::CMOVNB_Fp32 , X86::CMOVNB_F },
379 { X86::CMOVNB_Fp64 , X86::CMOVNB_F },
380 { X86::CMOVNB_Fp80 , X86::CMOVNB_F },
381 { X86::CMOVNE_Fp32 , X86::CMOVNE_F },
382 { X86::CMOVNE_Fp64 , X86::CMOVNE_F },
383 { X86::CMOVNE_Fp80 , X86::CMOVNE_F },
384 { X86::CMOVNP_Fp32 , X86::CMOVNP_F },
385 { X86::CMOVNP_Fp64 , X86::CMOVNP_F },
386 { X86::CMOVNP_Fp80 , X86::CMOVNP_F },
387 { X86::CMOVP_Fp32 , X86::CMOVP_F },
388 { X86::CMOVP_Fp64 , X86::CMOVP_F },
389 { X86::CMOVP_Fp80 , X86::CMOVP_F },
390 { X86::COS_Fp32 , X86::COS_F },
391 { X86::COS_Fp64 , X86::COS_F },
392 { X86::COS_Fp80 , X86::COS_F },
393 { X86::DIVR_Fp32m , X86::DIVR_F32m },
394 { X86::DIVR_Fp64m , X86::DIVR_F64m },
395 { X86::DIVR_Fp64m32 , X86::DIVR_F32m },
396 { X86::DIVR_Fp80m32 , X86::DIVR_F32m },
397 { X86::DIVR_Fp80m64 , X86::DIVR_F64m },
398 { X86::DIVR_FpI16m32, X86::DIVR_FI16m},
399 { X86::DIVR_FpI16m64, X86::DIVR_FI16m},
400 { X86::DIVR_FpI16m80, X86::DIVR_FI16m},
401 { X86::DIVR_FpI32m32, X86::DIVR_FI32m},
402 { X86::DIVR_FpI32m64, X86::DIVR_FI32m},
403 { X86::DIVR_FpI32m80, X86::DIVR_FI32m},
404 { X86::DIV_Fp32m , X86::DIV_F32m },
405 { X86::DIV_Fp64m , X86::DIV_F64m },
406 { X86::DIV_Fp64m32 , X86::DIV_F32m },
407 { X86::DIV_Fp80m32 , X86::DIV_F32m },
408 { X86::DIV_Fp80m64 , X86::DIV_F64m },
409 { X86::DIV_FpI16m32 , X86::DIV_FI16m },
410 { X86::DIV_FpI16m64 , X86::DIV_FI16m },
411 { X86::DIV_FpI16m80 , X86::DIV_FI16m },
412 { X86::DIV_FpI32m32 , X86::DIV_FI32m },
413 { X86::DIV_FpI32m64 , X86::DIV_FI32m },
414 { X86::DIV_FpI32m80 , X86::DIV_FI32m },
415 { X86::ILD_Fp16m32 , X86::ILD_F16m },
416 { X86::ILD_Fp16m64 , X86::ILD_F16m },
417 { X86::ILD_Fp16m80 , X86::ILD_F16m },
418 { X86::ILD_Fp32m32 , X86::ILD_F32m },
419 { X86::ILD_Fp32m64 , X86::ILD_F32m },
420 { X86::ILD_Fp32m80 , X86::ILD_F32m },
421 { X86::ILD_Fp64m32 , X86::ILD_F64m },
422 { X86::ILD_Fp64m64 , X86::ILD_F64m },
423 { X86::ILD_Fp64m80 , X86::ILD_F64m },
424 { X86::ISTT_Fp16m32 , X86::ISTT_FP16m},
425 { X86::ISTT_Fp16m64 , X86::ISTT_FP16m},
426 { X86::ISTT_Fp16m80 , X86::ISTT_FP16m},
427 { X86::ISTT_Fp32m32 , X86::ISTT_FP32m},
428 { X86::ISTT_Fp32m64 , X86::ISTT_FP32m},
429 { X86::ISTT_Fp32m80 , X86::ISTT_FP32m},
430 { X86::ISTT_Fp64m32 , X86::ISTT_FP64m},
431 { X86::ISTT_Fp64m64 , X86::ISTT_FP64m},
432 { X86::ISTT_Fp64m80 , X86::ISTT_FP64m},
433 { X86::IST_Fp16m32 , X86::IST_F16m },
434 { X86::IST_Fp16m64 , X86::IST_F16m },
435 { X86::IST_Fp16m80 , X86::IST_F16m },
436 { X86::IST_Fp32m32 , X86::IST_F32m },
437 { X86::IST_Fp32m64 , X86::IST_F32m },
438 { X86::IST_Fp32m80 , X86::IST_F32m },
439 { X86::IST_Fp64m32 , X86::IST_FP64m },
440 { X86::IST_Fp64m64 , X86::IST_FP64m },
441 { X86::IST_Fp64m80 , X86::IST_FP64m },
442 { X86::LD_Fp032 , X86::LD_F0 },
443 { X86::LD_Fp064 , X86::LD_F0 },
444 { X86::LD_Fp080 , X86::LD_F0 },
445 { X86::LD_Fp132 , X86::LD_F1 },
446 { X86::LD_Fp164 , X86::LD_F1 },
447 { X86::LD_Fp180 , X86::LD_F1 },
448 { X86::LD_Fp32m , X86::LD_F32m },
449 { X86::LD_Fp32m64 , X86::LD_F32m },
450 { X86::LD_Fp32m80 , X86::LD_F32m },
451 { X86::LD_Fp64m , X86::LD_F64m },
452 { X86::LD_Fp64m80 , X86::LD_F64m },
453 { X86::LD_Fp80m , X86::LD_F80m },
454 { X86::MUL_Fp32m , X86::MUL_F32m },
455 { X86::MUL_Fp64m , X86::MUL_F64m },
456 { X86::MUL_Fp64m32 , X86::MUL_F32m },
457 { X86::MUL_Fp80m32 , X86::MUL_F32m },
458 { X86::MUL_Fp80m64 , X86::MUL_F64m },
459 { X86::MUL_FpI16m32 , X86::MUL_FI16m },
460 { X86::MUL_FpI16m64 , X86::MUL_FI16m },
461 { X86::MUL_FpI16m80 , X86::MUL_FI16m },
462 { X86::MUL_FpI32m32 , X86::MUL_FI32m },
463 { X86::MUL_FpI32m64 , X86::MUL_FI32m },
464 { X86::MUL_FpI32m80 , X86::MUL_FI32m },
465 { X86::SIN_Fp32 , X86::SIN_F },
466 { X86::SIN_Fp64 , X86::SIN_F },
467 { X86::SIN_Fp80 , X86::SIN_F },
468 { X86::SQRT_Fp32 , X86::SQRT_F },
469 { X86::SQRT_Fp64 , X86::SQRT_F },
470 { X86::SQRT_Fp80 , X86::SQRT_F },
471 { X86::ST_Fp32m , X86::ST_F32m },
472 { X86::ST_Fp64m , X86::ST_F64m },
473 { X86::ST_Fp64m32 , X86::ST_F32m },
474 { X86::ST_Fp80m32 , X86::ST_F32m },
475 { X86::ST_Fp80m64 , X86::ST_F64m },
476 { X86::ST_FpP80m , X86::ST_FP80m },
477 { X86::SUBR_Fp32m , X86::SUBR_F32m },
478 { X86::SUBR_Fp64m , X86::SUBR_F64m },
479 { X86::SUBR_Fp64m32 , X86::SUBR_F32m },
480 { X86::SUBR_Fp80m32 , X86::SUBR_F32m },
481 { X86::SUBR_Fp80m64 , X86::SUBR_F64m },
482 { X86::SUBR_FpI16m32, X86::SUBR_FI16m},
483 { X86::SUBR_FpI16m64, X86::SUBR_FI16m},
484 { X86::SUBR_FpI16m80, X86::SUBR_FI16m},
485 { X86::SUBR_FpI32m32, X86::SUBR_FI32m},
486 { X86::SUBR_FpI32m64, X86::SUBR_FI32m},
487 { X86::SUBR_FpI32m80, X86::SUBR_FI32m},
488 { X86::SUB_Fp32m , X86::SUB_F32m },
489 { X86::SUB_Fp64m , X86::SUB_F64m },
490 { X86::SUB_Fp64m32 , X86::SUB_F32m },
491 { X86::SUB_Fp80m32 , X86::SUB_F32m },
492 { X86::SUB_Fp80m64 , X86::SUB_F64m },
493 { X86::SUB_FpI16m32 , X86::SUB_FI16m },
494 { X86::SUB_FpI16m64 , X86::SUB_FI16m },
495 { X86::SUB_FpI16m80 , X86::SUB_FI16m },
496 { X86::SUB_FpI32m32 , X86::SUB_FI32m },
497 { X86::SUB_FpI32m64 , X86::SUB_FI32m },
498 { X86::SUB_FpI32m80 , X86::SUB_FI32m },
499 { X86::TST_Fp32 , X86::TST_F },
500 { X86::TST_Fp64 , X86::TST_F },
501 { X86::TST_Fp80 , X86::TST_F },
502 { X86::UCOM_FpIr32 , X86::UCOM_FIr },
503 { X86::UCOM_FpIr64 , X86::UCOM_FIr },
504 { X86::UCOM_FpIr80 , X86::UCOM_FIr },
505 { X86::UCOM_Fpr32 , X86::UCOM_Fr },
506 { X86::UCOM_Fpr64 , X86::UCOM_Fr },
507 { X86::UCOM_Fpr80 , X86::UCOM_Fr },
508 };
509
510 static unsigned getConcreteOpcode(unsigned Opcode) {
511 ASSERT_SORTED(OpcodeTable);
512 int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode);
513 assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!");
514 return Opc;
515 }
516
517 //===----------------------------------------------------------------------===//
518 // Helper Methods
519 //===----------------------------------------------------------------------===//
520
521 // PopTable - Sorted map of instructions to their popping version. The first
522 // element is an instruction, the second is the version which pops.
523 //
524 static const TableEntry PopTable[] = {
525 { X86::ADD_FrST0 , X86::ADD_FPrST0 },
526
527 { X86::DIVR_FrST0, X86::DIVR_FPrST0 },
528 { X86::DIV_FrST0 , X86::DIV_FPrST0 },
529
530 { X86::IST_F16m , X86::IST_FP16m },
531 { X86::IST_F32m , X86::IST_FP32m },
532
533 { X86::MUL_FrST0 , X86::MUL_FPrST0 },
534
535 { X86::ST_F32m , X86::ST_FP32m },
536 { X86::ST_F64m , X86::ST_FP64m },
537 { X86::ST_Frr , X86::ST_FPrr },
538
539 { X86::SUBR_FrST0, X86::SUBR_FPrST0 },
540 { X86::SUB_FrST0 , X86::SUB_FPrST0 },
541
542 { X86::UCOM_FIr , X86::UCOM_FIPr },
543
544 { X86::UCOM_FPr , X86::UCOM_FPPr },
545 { X86::UCOM_Fr , X86::UCOM_FPr },
546 };
547
548 /// popStackAfter - Pop the current value off of the top of the FP stack after
549 /// the specified instruction. This attempts to be sneaky and combine the pop
550 /// into the instruction itself if possible. The iterator is left pointing to
551 /// the last instruction, be it a new pop instruction inserted, or the old
552 /// instruction if it was modified in place.
553 ///
554 void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
555 MachineInstr* MI = I;
556 DebugLoc dl = MI->getDebugLoc();
557 ASSERT_SORTED(PopTable);
558 assert(StackTop > 0 && "Cannot pop empty stack!");
559 RegMap[Stack[--StackTop]] = ~0; // Update state
560
561 // Check to see if there is a popping version of this instruction...
562 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
563 if (Opcode != -1) {
564 I->setDesc(TII->get(Opcode));
565 if (Opcode == X86::UCOM_FPPr)
566 I->RemoveOperand(0);
567 } else { // Insert an explicit pop
568 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
569 }
570 }
571
572 /// freeStackSlotAfter - Free the specified register from the register stack, so
573 /// that it is no longer in a register. If the register is currently at the top
574 /// of the stack, we just pop the current instruction, otherwise we store the
575 /// current top-of-stack into the specified slot, then pop the top of stack.
576 void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
577 if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy.
578 popStackAfter(I);
579 return;
580 }
581
582 // Otherwise, store the top of stack into the dead slot, killing the operand
583 // without having to add in an explicit xchg then pop.
584 //
585 unsigned STReg = getSTReg(FPRegNo);
586 unsigned OldSlot = getSlot(FPRegNo);
587 unsigned TopReg = Stack[StackTop-1];
588 Stack[OldSlot] = TopReg;
589 RegMap[TopReg] = OldSlot;
590 RegMap[FPRegNo] = ~0;
591 Stack[--StackTop] = ~0;
592 MachineInstr *MI = I;
593 DebugLoc dl = MI->getDebugLoc();
594 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg);
595 }
596
597
598 //===----------------------------------------------------------------------===//
599 // Instruction transformation implementation
600 //===----------------------------------------------------------------------===//
601
602 /// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
603 ///
604 void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
605 MachineInstr *MI = I;
606 unsigned DestReg = getFPReg(MI->getOperand(0));
607
608 // Change from the pseudo instruction to the concrete instruction.
609 MI->RemoveOperand(0); // Remove the explicit ST(0) operand
610 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
611
612 // Result gets pushed on the stack.
613 pushReg(DestReg);
614 }
615
616 /// handleOneArgFP - fst <mem>, ST(0)
617 ///
618 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
619 MachineInstr *MI = I;
620 unsigned NumOps = MI->getDesc().getNumOperands();
621 assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) &&
622 "Can only handle fst* & ftst instructions!");
623
624 // Is this the last use of the source register?
625 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
626 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
627
628 // FISTP64m is strange because there isn't a non-popping versions.
629 // If we have one _and_ we don't want to pop the operand, duplicate the value
630 // on the stack instead of moving it. This ensure that popping the value is
631 // always ok.
632 // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m.
633 //
634 if (!KillsSrc &&
635 (MI->getOpcode() == X86::IST_Fp64m32 ||
636 MI->getOpcode() == X86::ISTT_Fp16m32 ||
637 MI->getOpcode() == X86::ISTT_Fp32m32 ||
638 MI->getOpcode() == X86::ISTT_Fp64m32 ||
639 MI->getOpcode() == X86::IST_Fp64m64 ||
640 MI->getOpcode() == X86::ISTT_Fp16m64 ||
641 MI->getOpcode() == X86::ISTT_Fp32m64 ||
642 MI->getOpcode() == X86::ISTT_Fp64m64 ||
643 MI->getOpcode() == X86::IST_Fp64m80 ||
644 MI->getOpcode() == X86::ISTT_Fp16m80 ||
645 MI->getOpcode() == X86::ISTT_Fp32m80 ||
646 MI->getOpcode() == X86::ISTT_Fp64m80 ||
647 MI->getOpcode() == X86::ST_FpP80m)) {
648 duplicateToTop(Reg, 7 /*temp register*/, I);
649 } else {
650 moveToTop(Reg, I); // Move to the top of the stack...
651 }
652
653 // Convert from the pseudo instruction to the concrete instruction.
654 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
655 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
656
657 if (MI->getOpcode() == X86::IST_FP64m ||
658 MI->getOpcode() == X86::ISTT_FP16m ||
659 MI->getOpcode() == X86::ISTT_FP32m ||
660 MI->getOpcode() == X86::ISTT_FP64m ||
661 MI->getOpcode() == X86::ST_FP80m) {
662 assert(StackTop > 0 && "Stack empty??");
663 --StackTop;
664 } else if (KillsSrc) { // Last use of operand?
665 popStackAfter(I);
666 }
667 }
668
669
670 /// handleOneArgFPRW: Handle instructions that read from the top of stack and
671 /// replace the value with a newly computed value. These instructions may have
672 /// non-fp operands after their FP operands.
673 ///
674 /// Examples:
675 /// R1 = fchs R2
676 /// R1 = fadd R2, [mem]
677 ///
678 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
679 MachineInstr *MI = I;
680 #ifndef NDEBUG
681 unsigned NumOps = MI->getDesc().getNumOperands();
682 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
683 #endif
684
685 // Is this the last use of the source register?
686 unsigned Reg = getFPReg(MI->getOperand(1));
687 bool KillsSrc = MI->killsRegister(X86::FP0+Reg);
688
689 if (KillsSrc) {
690 // If this is the last use of the source register, just make sure it's on
691 // the top of the stack.
692 moveToTop(Reg, I);
693 assert(StackTop > 0 && "Stack cannot be empty!");
694 --StackTop;
695 pushReg(getFPReg(MI->getOperand(0)));
696 } else {
697 // If this is not the last use of the source register, _copy_ it to the top
698 // of the stack.
699 duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I);
700 }
701
702 // Change from the pseudo instruction to the concrete instruction.
703 MI->RemoveOperand(1); // Drop the source operand.
704 MI->RemoveOperand(0); // Drop the destination operand.
705 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
706 }
707
708
709 //===----------------------------------------------------------------------===//
710 // Define tables of various ways to map pseudo instructions
711 //
712
713 // ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
714 static const TableEntry ForwardST0Table[] = {
715 { X86::ADD_Fp32 , X86::ADD_FST0r },
716 { X86::ADD_Fp64 , X86::ADD_FST0r },
717 { X86::ADD_Fp80 , X86::ADD_FST0r },
718 { X86::DIV_Fp32 , X86::DIV_FST0r },
719 { X86::DIV_Fp64 , X86::DIV_FST0r },
720 { X86::DIV_Fp80 , X86::DIV_FST0r },
721 { X86::MUL_Fp32 , X86::MUL_FST0r },
722 { X86::MUL_Fp64 , X86::MUL_FST0r },
723 { X86::MUL_Fp80 , X86::MUL_FST0r },
724 { X86::SUB_Fp32 , X86::SUB_FST0r },
725 { X86::SUB_Fp64 , X86::SUB_FST0r },
726 { X86::SUB_Fp80 , X86::SUB_FST0r },
727 };
728
729 // ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
730 static const TableEntry ReverseST0Table[] = {
731 { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative
732 { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative
733 { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative
734 { X86::DIV_Fp32 , X86::DIVR_FST0r },
735 { X86::DIV_Fp64 , X86::DIVR_FST0r },
736 { X86::DIV_Fp80 , X86::DIVR_FST0r },
737 { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative
738 { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative
739 { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative
740 { X86::SUB_Fp32 , X86::SUBR_FST0r },
741 { X86::SUB_Fp64 , X86::SUBR_FST0r },
742 { X86::SUB_Fp80 , X86::SUBR_FST0r },
743 };
744
745 // ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
746 static const TableEntry ForwardSTiTable[] = {
747 { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative
748 { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative
749 { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative
750 { X86::DIV_Fp32 , X86::DIVR_FrST0 },
751 { X86::DIV_Fp64 , X86::DIVR_FrST0 },
752 { X86::DIV_Fp80 , X86::DIVR_FrST0 },
753 { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative
754 { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative
755 { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative
756 { X86::SUB_Fp32 , X86::SUBR_FrST0 },
757 { X86::SUB_Fp64 , X86::SUBR_FrST0 },
758 { X86::SUB_Fp80 , X86::SUBR_FrST0 },
759 };
760
761 // ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
762 static const TableEntry ReverseSTiTable[] = {
763 { X86::ADD_Fp32 , X86::ADD_FrST0 },
764 { X86::ADD_Fp64 , X86::ADD_FrST0 },
765 { X86::ADD_Fp80 , X86::ADD_FrST0 },
766 { X86::DIV_Fp32 , X86::DIV_FrST0 },
767 { X86::DIV_Fp64 , X86::DIV_FrST0 },
768 { X86::DIV_Fp80 , X86::DIV_FrST0 },
769 { X86::MUL_Fp32 , X86::MUL_FrST0 },
770 { X86::MUL_Fp64 , X86::MUL_FrST0 },
771 { X86::MUL_Fp80 , X86::MUL_FrST0 },
772 { X86::SUB_Fp32 , X86::SUB_FrST0 },
773 { X86::SUB_Fp64 , X86::SUB_FrST0 },
774 { X86::SUB_Fp80 , X86::SUB_FrST0 },
775 };
776
777
778 /// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
779 /// instructions which need to be simplified and possibly transformed.
780 ///
781 /// Result: ST(0) = fsub ST(0), ST(i)
782 /// ST(i) = fsub ST(0), ST(i)
783 /// ST(0) = fsubr ST(0), ST(i)
784 /// ST(i) = fsubr ST(0), ST(i)
785 ///
786 void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
787 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
788 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
789 MachineInstr *MI = I;
790
791 unsigned NumOperands = MI->getDesc().getNumOperands();
792 assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
793 unsigned Dest = getFPReg(MI->getOperand(0));
794 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
795 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
796 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
797 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
798 DebugLoc dl = MI->getDebugLoc();
799
800 unsigned TOS = getStackEntry(0);
801
802 // One of our operands must be on the top of the stack. If neither is yet, we
803 // need to move one.
804 if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
805 // We can choose to move either operand to the top of the stack. If one of
806 // the operands is killed by this instruction, we want that one so that we
807 // can update right on top of the old version.
808 if (KillsOp0) {
809 moveToTop(Op0, I); // Move dead operand to TOS.
810 TOS = Op0;
811 } else if (KillsOp1) {
812 moveToTop(Op1, I);
813 TOS = Op1;
814 } else {
815 // All of the operands are live after this instruction executes, so we
816 // cannot update on top of any operand. Because of this, we must
817 // duplicate one of the stack elements to the top. It doesn't matter
818 // which one we pick.
819 //
820 duplicateToTop(Op0, Dest, I);
821 Op0 = TOS = Dest;
822 KillsOp0 = true;
823 }
824 } else if (!KillsOp0 && !KillsOp1) {
825 // If we DO have one of our operands at the top of the stack, but we don't
826 // have a dead operand, we must duplicate one of the operands to a new slot
827 // on the stack.
828 duplicateToTop(Op0, Dest, I);
829 Op0 = TOS = Dest;
830 KillsOp0 = true;
831 }
832
833 // Now we know that one of our operands is on the top of the stack, and at
834 // least one of our operands is killed by this instruction.
835 assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) &&
836 "Stack conditions not set up right!");
837
838 // We decide which form to use based on what is on the top of the stack, and
839 // which operand is killed by this instruction.
840 const TableEntry *InstTable;
841 bool isForward = TOS == Op0;
842 bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
843 if (updateST0) {
844 if (isForward)
845 InstTable = ForwardST0Table;
846 else
847 InstTable = ReverseST0Table;
848 } else {
849 if (isForward)
850 InstTable = ForwardSTiTable;
851 else
852 InstTable = ReverseSTiTable;
853 }
854
855 int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table),
856 MI->getOpcode());
857 assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
858
859 // NotTOS - The register which is not on the top of stack...
860 unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
861
862 // Replace the old instruction with a new instruction
863 MBB->remove(I++);
864 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
865
866 // If both operands are killed, pop one off of the stack in addition to
867 // overwriting the other one.
868 if (KillsOp0 && KillsOp1 && Op0 != Op1) {
869 assert(!updateST0 && "Should have updated other operand!");
870 popStackAfter(I); // Pop the top of stack
871 }
872
873 // Update stack information so that we know the destination register is now on
874 // the stack.
875 unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
876 assert(UpdatedSlot < StackTop && Dest < 7);
877 Stack[UpdatedSlot] = Dest;
878 RegMap[Dest] = UpdatedSlot;
879 MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction
880 }
881
882 /// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP
883 /// register arguments and no explicit destinations.
884 ///
885 void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
886 ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
887 ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
888 MachineInstr *MI = I;
889
890 unsigned NumOperands = MI->getDesc().getNumOperands();
891 assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
892 unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
893 unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
894 bool KillsOp0 = MI->killsRegister(X86::FP0+Op0);
895 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
896
897 // Make sure the first operand is on the top of stack, the other one can be
898 // anywhere.
899 moveToTop(Op0, I);
900
901 // Change from the pseudo instruction to the concrete instruction.
902 MI->getOperand(0).setReg(getSTReg(Op1));
903 MI->RemoveOperand(1);
904 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
905
906 // If any of the operands are killed by this instruction, free them.
907 if (KillsOp0) freeStackSlotAfter(I, Op0);
908 if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1);
909 }
910
911 /// handleCondMovFP - Handle two address conditional move instructions. These
912 /// instructions move a st(i) register to st(0) iff a condition is true. These
913 /// instructions require that the first operand is at the top of the stack, but
914 /// otherwise don't modify the stack at all.
915 void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
916 MachineInstr *MI = I;
917
918 unsigned Op0 = getFPReg(MI->getOperand(0));
919 unsigned Op1 = getFPReg(MI->getOperand(2));
920 bool KillsOp1 = MI->killsRegister(X86::FP0+Op1);
921
922 // The first operand *must* be on the top of the stack.
923 moveToTop(Op0, I);
924
925 // Change the second operand to the stack register that the operand is in.
926 // Change from the pseudo instruction to the concrete instruction.
927 MI->RemoveOperand(0);
928 MI->RemoveOperand(1);
929 MI->getOperand(0).setReg(getSTReg(Op1));
930 MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode())));
931
932 // If we kill the second operand, make sure to pop it from the stack.
933 if (Op0 != Op1 && KillsOp1) {
934 // Get this value off of the register stack.
935 freeStackSlotAfter(I, Op1);
936 }
937 }
938
939
940 /// handleSpecialFP - Handle special instructions which behave unlike other
941 /// floating point instructions. This is primarily intended for use by pseudo
942 /// instructions.
943 ///
944 void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
945 MachineInstr *MI = I;
946 DebugLoc dl = MI->getDebugLoc();
947 switch (MI->getOpcode()) {
948 default: assert(0 && "Unknown SpecialFP instruction!");
949 case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
950 case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
951 case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
952 assert(StackTop == 0 && "Stack should be empty after a call!");
953 pushReg(getFPReg(MI->getOperand(0)));
954 break;
955 case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
956 case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
957 case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
958 // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
959 // The pattern we expect is:
960 // CALL
961 // FP1 = FpGET_ST0
962 // FP4 = FpGET_ST1
963 //
964 // At this point, we've pushed FP1 on the top of stack, so it should be
965 // present if it isn't dead. If it was dead, we already emitted a pop to
966 // remove it from the stack and StackTop = 0.
967
968 // Push FP4 as top of stack next.
969 pushReg(getFPReg(MI->getOperand(0)));
970
971 // If StackTop was 0 before we pushed our operand, then ST(0) must have been
972 // dead. In this case, the ST(1) value is the only thing that is live, so
973 // it should be on the TOS (after the pop that was emitted) and is. Just
974 // continue in this case.
975 if (StackTop == 1)
976 break;
977
978 // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
979 // elements so that our accounting is correct.
980 unsigned RegOnTop = getStackEntry(0);
981 unsigned RegNo = getStackEntry(1);
982
983 // Swap the slots the regs are in.
984 std::swap(RegMap[RegNo], RegMap[RegOnTop]);
985
986 // Swap stack slot contents.
987 assert(RegMap[RegOnTop] < StackTop);
988 std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
989 break;
990 }
991 case X86::FpSET_ST0_32:
992 case X86::FpSET_ST0_64:
993 case X86::FpSET_ST0_80:
994 assert((StackTop == 1 || StackTop == 2)
995 && "Stack should have one or two element on it to return!");
996 --StackTop; // "Forget" we have something on the top of stack!
997 break;
998 case X86::FpSET_ST1_32:
999 case X86::FpSET_ST1_64:
1000 case X86::FpSET_ST1_80:
1001 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1002 if (StackTop == 1) {
1003 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1004 NumFXCH++;
1005 StackTop = 0;
1006 break;
1007 }
1008 assert(StackTop == 2 && "Stack should have two element on it to return!");
1009 --StackTop; // "Forget" we have something on the top of stack!
1010 break;
1011 case X86::MOV_Fp3232:
1012 case X86::MOV_Fp3264:
1013 case X86::MOV_Fp6432:
1014 case X86::MOV_Fp6464:
1015 case X86::MOV_Fp3280:
1016 case X86::MOV_Fp6480:
1017 case X86::MOV_Fp8032:
1018 case X86::MOV_Fp8064:
1019 case X86::MOV_Fp8080: {
1020 const MachineOperand &MO1 = MI->getOperand(1);
1021 unsigned SrcReg = getFPReg(MO1);
1022
1023 const MachineOperand &MO0 = MI->getOperand(0);
1024 // These can be created due to inline asm. Two address pass can introduce
1025 // copies from RFP registers to virtual registers.
1026 if (MO0.getReg() == X86::ST0 && SrcReg == 0) {
1027 assert(MO1.isKill());
1028 // Treat %ST0<def> = MOV_Fp8080 %FP0<kill>
1029 // like FpSET_ST0_80 %FP0<kill>, %ST0<imp-def>
1030 assert((StackTop == 1 || StackTop == 2)
1031 && "Stack should have one or two element on it to return!");
1032 --StackTop; // "Forget" we have something on the top of stack!
1033 break;
1034 } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) {
1035 assert(MO1.isKill());
1036 // Treat %ST1<def> = MOV_Fp8080 %FP1<kill>
1037 // like FpSET_ST1_80 %FP0<kill>, %ST1<imp-def>
1038 // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them.
1039 if (StackTop == 1) {
1040 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1);
1041 NumFXCH++;
1042 StackTop = 0;
1043 break;
1044 }
1045 assert(StackTop == 2 && "Stack should have two element on it to return!");
1046 --StackTop; // "Forget" we have something on the top of stack!
1047 break;
1048 }
1049
1050 unsigned DestReg = getFPReg(MO0);
1051 if (MI->killsRegister(X86::FP0+SrcReg)) {
1052 // If the input operand is killed, we can just change the owner of the
1053 // incoming stack slot into the result.
1054 unsigned Slot = getSlot(SrcReg);
1055 assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
1056 Stack[Slot] = DestReg;
1057 RegMap[DestReg] = Slot;
1058
1059 } else {
1060 // For FMOV we just duplicate the specified value to a new stack slot.
1061 // This could be made better, but would require substantial changes.
1062 duplicateToTop(SrcReg, DestReg, I);
1063 }
1064 }
1065 break;
1066 case TargetInstrInfo::INLINEASM: {
1067 // The inline asm MachineInstr currently only *uses* FP registers for the
1068 // 'f' constraint. These should be turned into the current ST(x) register
1069 // in the machine instr. Also, any kills should be explicitly popped after
1070 // the inline asm.
1071 unsigned Kills[7];
1072 unsigned NumKills = 0;
1073 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1074 MachineOperand &Op = MI->getOperand(i);
1075 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1076 continue;
1077 assert(Op.isUse() && "Only handle inline asm uses right now");
1078
1079 unsigned FPReg = getFPReg(Op);
1080 Op.setReg(getSTReg(FPReg));
1081
1082 // If we kill this operand, make sure to pop it from the stack after the
1083 // asm. We just remember it for now, and pop them all off at the end in
1084 // a batch.
1085 if (Op.isKill())
1086 Kills[NumKills++] = FPReg;
1087 }
1088
1089 // If this asm kills any FP registers (is the last use of them) we must
1090 // explicitly emit pop instructions for them. Do this now after the asm has
1091 // executed so that the ST(x) numbers are not off (which would happen if we
1092 // did this inline with operand rewriting).
1093 //
1094 // Note: this might be a non-optimal pop sequence. We might be able to do
1095 // better by trying to pop in stack order or something.
1096 MachineBasicBlock::iterator InsertPt = MI;
1097 while (NumKills)
1098 freeStackSlotAfter(InsertPt, Kills[--NumKills]);
1099
1100 // Don't delete the inline asm!
1101 return;
1102 }
1103
1104 case X86::RET:
1105 case X86::RETI:
1106 // If RET has an FP register use operand, pass the first one in ST(0) and
1107 // the second one in ST(1).
1108 if (isStackEmpty()) return; // Quick check to see if any are possible.
1109
1110 // Find the register operands.
1111 unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U;
1112
1113 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1114 MachineOperand &Op = MI->getOperand(i);
1115 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1116 continue;
1117 // FP Register uses must be kills unless there are two uses of the same
1118 // register, in which case only one will be a kill.
1119 assert(Op.isUse() &&
1120 (Op.isKill() || // Marked kill.
1121 getFPReg(Op) == FirstFPRegOp || // Second instance.
1122 MI->killsRegister(Op.getReg())) && // Later use is marked kill.
1123 "Ret only defs operands, and values aren't live beyond it");
1124
1125 if (FirstFPRegOp == ~0U)
1126 FirstFPRegOp = getFPReg(Op);
1127 else {
1128 assert(SecondFPRegOp == ~0U && "More than two fp operands!");
1129 SecondFPRegOp = getFPReg(Op);
1130 }
1131
1132 // Remove the operand so that later passes don't see it.
1133 MI->RemoveOperand(i);
1134 --i, --e;
1135 }
1136
1137 // There are only four possibilities here:
1138 // 1) we are returning a single FP value. In this case, it has to be in
1139 // ST(0) already, so just declare success by removing the value from the
1140 // FP Stack.
1141 if (SecondFPRegOp == ~0U) {
1142 // Assert that the top of stack contains the right FP register.
1143 assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) &&
1144 "Top of stack not the right register for RET!");
1145
1146 // Ok, everything is good, mark the value as not being on the stack
1147 // anymore so that our assertion about the stack being empty at end of
1148 // block doesn't fire.
1149 StackTop = 0;
1150 return;
1151 }
1152
1153 // Otherwise, we are returning two values:
1154 // 2) If returning the same value for both, we only have one thing in the FP
1155 // stack. Consider: RET FP1, FP1
1156 if (StackTop == 1) {
1157 assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&&
1158 "Stack misconfiguration for RET!");
1159
1160 // Duplicate the TOS so that we return it twice. Just pick some other FPx
1161 // register to hold it.
1162 unsigned NewReg = (FirstFPRegOp+1)%7;
1163 duplicateToTop(FirstFPRegOp, NewReg, MI);
1164 FirstFPRegOp = NewReg;
1165 }
1166
1167 /// Okay we know we have two different FPx operands now:
1168 assert(StackTop == 2 && "Must have two values live!");
1169
1170 /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently
1171 /// in ST(1). In this case, emit an fxch.
1172 if (getStackEntry(0) == SecondFPRegOp) {
1173 assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live");
1174 moveToTop(FirstFPRegOp, MI);
1175 }
1176
1177 /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in
1178 /// ST(1). Just remove both from our understanding of the stack and return.
1179 assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live");
1180 assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live");
1181 StackTop = 0;
1182 return;
1183 }
1184
1185 I = MBB->erase(I); // Remove the pseudo instruction
1186 --I;
1187 }
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