lib/Target/ARM/ARMAddressingModes.h

   1 //===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the ARM addressing mode implementation stuff.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
  15 #define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
  16
  17 #include "llvm/CodeGen/SelectionDAGNodes.h"
  18 #include "llvm/Support/MathExtras.h"
  19 #include <cassert>
  20
  21 namespace llvm {
  22
  23 /// ARM_AM - ARM Addressing Mode Stuff
  24 namespace ARM_AM {
  25   enum ShiftOpc {
  26     no_shift = 0,
  27     asr,
  28     lsl,
  29     lsr,
  30     ror,
  31     rrx
  32   };
  33
  34   enum AddrOpc {
  35     add = '+', sub = '-'
  36   };
  37
  38   static inline const char *getShiftOpcStr(ShiftOpc Op) {
  39     switch (Op) {
  40     default: assert(0 && "Unknown shift opc!");
  41     case ARM_AM::asr: return "asr";
  42     case ARM_AM::lsl: return "lsl";
  43     case ARM_AM::lsr: return "lsr";
  44     case ARM_AM::ror: return "ror";
  45     case ARM_AM::rrx: return "rrx";
  46     }
  47   }
  48
  49   static inline ShiftOpc getShiftOpcForNode(SDValue N) {
  50     switch (N.getOpcode()) {
  51     default:          return ARM_AM::no_shift;
  52     case ISD::SHL:    return ARM_AM::lsl;
  53     case ISD::SRL:    return ARM_AM::lsr;
  54     case ISD::SRA:    return ARM_AM::asr;
  55     case ISD::ROTR:   return ARM_AM::ror;
  56     //case ISD::ROTL:  // Only if imm -> turn into ROTR.
  57     // Can't handle RRX here, because it would require folding a flag into
  58     // the addressing mode.  :(  This causes us to miss certain things.
  59     //case ARMISD::RRX: return ARM_AM::rrx;
  60     }
  61   }
  62
  63   enum AMSubMode {
  64     bad_am_submode = 0,
  65     ia,
  66     ib,
  67     da,
  68     db
  69   };
  70
  71   static inline const char *getAMSubModeStr(AMSubMode Mode) {
  72     switch (Mode) {
  73     default: assert(0 && "Unknown addressing sub-mode!");
  74     case ARM_AM::ia: return "ia";
  75     case ARM_AM::ib: return "ib";
  76     case ARM_AM::da: return "da";
  77     case ARM_AM::db: return "db";
  78     }
  79   }
  80
  81   static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
  82     switch (Mode) {
  83     default: assert(0 && "Unknown addressing sub-mode!");
  84     case ARM_AM::ia: return isLD ? "fd" : "ea";
  85     case ARM_AM::ib: return isLD ? "ed" : "fa";
  86     case ARM_AM::da: return isLD ? "fa" : "ed";
  87     case ARM_AM::db: return isLD ? "ea" : "fd";
  88     }
  89   }
  90
  91   /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
  92   ///
  93   static inline unsigned rotr32(unsigned Val, unsigned Amt) {
  94     assert(Amt < 32 && "Invalid rotate amount");
  95     return (Val >> Amt) | (Val << ((32-Amt)&31));
  96   }
  97
  98   /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
  99   ///
 100   static inline unsigned rotl32(unsigned Val, unsigned Amt) {
 101     assert(Amt < 32 && "Invalid rotate amount");
 102     return (Val << Amt) | (Val >> ((32-Amt)&31));
 103   }
 104
 105   //===--------------------------------------------------------------------===//
 106   // Addressing Mode #1: shift_operand with registers
 107   //===--------------------------------------------------------------------===//
 108   //
 109   // This 'addressing mode' is used for arithmetic instructions.  It can
 110   // represent things like:
 111   //   reg
 112   //   reg [asr|lsl|lsr|ror|rrx] reg
 113   //   reg [asr|lsl|lsr|ror|rrx] imm
 114   //
 115   // This is stored three operands [rega, regb, opc].  The first is the base
 116   // reg, the second is the shift amount (or reg0 if not present or imm).  The
 117   // third operand encodes the shift opcode and the imm if a reg isn't present.
 118   //
 119   static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
 120     return ShOp | (Imm << 3);
 121   }
 122   static inline unsigned getSORegOffset(unsigned Op) {
 123     return Op >> 3;
 124   }
 125   static inline ShiftOpc getSORegShOp(unsigned Op) {
 126     return (ShiftOpc)(Op & 7);
 127   }
 128
 129   /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
 130   /// the 8-bit imm value.
 131   static inline unsigned getSOImmValImm(unsigned Imm) {
 132     return Imm & 0xFF;
 133   }
 134   /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
 135   /// the rotate amount.
 136   static inline unsigned getSOImmValRot(unsigned Imm) {
 137     return (Imm >> 8) * 2;
 138   }
 139
 140   /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
 141   /// computing the rotate amount to use.  If this immediate value cannot be
 142   /// handled with a single shifter-op, determine a good rotate amount that will
 143   /// take a maximal chunk of bits out of the immediate.
 144   static inline unsigned getSOImmValRotate(unsigned Imm) {
 145     // 8-bit (or less) immediates are trivially shifter_operands with a rotate
 146     // of zero.
 147     if ((Imm & ~255U) == 0) return 0;
 148
 149     // Use CTZ to compute the rotate amount.
 150     unsigned TZ = CountTrailingZeros_32(Imm);
 151
 152     // Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
 153     // not 9.
 154     unsigned RotAmt = TZ & ~1;
 155
 156     // If we can handle this spread, return it.
 157     if ((rotr32(Imm, RotAmt) & ~255U) == 0)
 158       return (32-RotAmt)&31;  // HW rotates right, not left.
 159
 160     // For values like 0xF000000F, we should skip the first run of ones, then
 161     // retry the hunt.
 162     if (Imm & 1) {
 163       unsigned TrailingOnes = CountTrailingZeros_32(~Imm);
 164       if (TrailingOnes != 32) {  // Avoid overflow on 0xFFFFFFFF
 165         // Restart the search for a high-order bit after the initial seconds of
 166         // ones.
 167         unsigned TZ2 = CountTrailingZeros_32(Imm & ~((1 << TrailingOnes)-1));
 168
 169         // Rotate amount must be even.
 170         unsigned RotAmt2 = TZ2 & ~1;
 171
 172         // If this fits, use it.
 173         if (RotAmt2 != 32 && (rotr32(Imm, RotAmt2) & ~255U) == 0)
 174           return (32-RotAmt2)&31;  // HW rotates right, not left.
 175       }
 176     }
 177
 178     // Otherwise, we have no way to cover this span of bits with a single
 179     // shifter_op immediate.  Return a chunk of bits that will be useful to
 180     // handle.
 181     return (32-RotAmt)&31;  // HW rotates right, not left.
 182   }
 183
 184   /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
 185   /// into an shifter_operand immediate operand, return the 12-bit encoding for
 186   /// it.  If not, return -1.
 187   static inline int getSOImmVal(unsigned Arg) {
 188     // 8-bit (or less) immediates are trivially shifter_operands with a rotate
 189     // of zero.
 190     if ((Arg & ~255U) == 0) return Arg;
 191
 192     unsigned RotAmt = getSOImmValRotate(Arg);
 193
 194     // If this cannot be handled with a single shifter_op, bail out.
 195     if (rotr32(~255U, RotAmt) & Arg)
 196       return -1;
 197
 198     // Encode this correctly.
 199     return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
 200   }
 201
 202   /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
 203   /// or'ing together two SOImmVal's.
 204   static inline bool isSOImmTwoPartVal(unsigned V) {
 205     // If this can be handled with a single shifter_op, bail out.
 206     V = rotr32(~255U, getSOImmValRotate(V)) & V;
 207     if (V == 0)
 208       return false;
 209
 210     // If this can be handled with two shifter_op's, accept.
 211     V = rotr32(~255U, getSOImmValRotate(V)) & V;
 212     return V == 0;
 213   }
 214
 215   /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
 216   /// return the first chunk of it.
 217   static inline unsigned getSOImmTwoPartFirst(unsigned V) {
 218     return rotr32(255U, getSOImmValRotate(V)) & V;
 219   }
 220
 221   /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
 222   /// return the second chunk of it.
 223   static inline unsigned getSOImmTwoPartSecond(unsigned V) {
 224     // Mask out the first hunk.
 225     V = rotr32(~255U, getSOImmValRotate(V)) & V;
 226
 227     // Take what's left.
 228     assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
 229     return V;
 230   }
 231
 232   /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
 233   /// by a left shift. Returns the shift amount to use.
 234   static inline unsigned getThumbImmValShift(unsigned Imm) {
 235     // 8-bit (or less) immediates are trivially immediate operand with a shift
 236     // of zero.
 237     if ((Imm & ~255U) == 0) return 0;
 238
 239     // Use CTZ to compute the shift amount.
 240     return CountTrailingZeros_32(Imm);
 241   }
 242
 243   /// isThumbImmShiftedVal - Return true if the specified value can be obtained
 244   /// by left shifting a 8-bit immediate.
 245   static inline bool isThumbImmShiftedVal(unsigned V) {
 246     // If this can be handled with
 247     V = (~255U << getThumbImmValShift(V)) & V;
 248     return V == 0;
 249   }
 250
 251   /// getThumbImmNonShiftedVal - If V is a value that satisfies
 252   /// isThumbImmShiftedVal, return the non-shiftd value.
 253   static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
 254     return V >> getThumbImmValShift(V);
 255   }
 256
 257   //===--------------------------------------------------------------------===//
 258   // Addressing Mode #2
 259   //===--------------------------------------------------------------------===//
 260   //
 261   // This is used for most simple load/store instructions.
 262   //
 263   // addrmode2 := reg +/- reg shop imm
 264   // addrmode2 := reg +/- imm12
 265   //
 266   // The first operand is always a Reg.  The second operand is a reg if in
 267   // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
 268   // in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
 269   //
 270   // If this addressing mode is a frame index (before prolog/epilog insertion
 271   // and code rewriting), this operand will have the form:  FI#, reg0, <offs>
 272   // with no shift amount for the frame offset.
 273   //
 274   static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
 275     assert(Imm12 < (1 << 12) && "Imm too large!");
 276     bool isSub = Opc == sub;
 277     return Imm12 | ((int)isSub << 12) | (SO << 13);
 278   }
 279   static inline unsigned getAM2Offset(unsigned AM2Opc) {
 280     return AM2Opc & ((1 << 12)-1);
 281   }
 282   static inline AddrOpc getAM2Op(unsigned AM2Opc) {
 283     return ((AM2Opc >> 12) & 1) ? sub : add;
 284   }
 285   static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
 286     return (ShiftOpc)(AM2Opc >> 13);
 287   }
 288
 289
 290   //===--------------------------------------------------------------------===//
 291   // Addressing Mode #3
 292   //===--------------------------------------------------------------------===//
 293   //
 294   // This is used for sign-extending loads, and load/store-pair instructions.
 295   //
 296   // addrmode3 := reg +/- reg
 297   // addrmode3 := reg +/- imm8
 298   //
 299   // The first operand is always a Reg.  The second operand is a reg if in
 300   // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
 301   // in bit 8, the immediate in bits 0-7.
 302
 303   /// getAM3Opc - This function encodes the addrmode3 opc field.
 304   static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
 305     bool isSub = Opc == sub;
 306     return ((int)isSub << 8) | Offset;
 307   }
 308   static inline unsigned char getAM3Offset(unsigned AM3Opc) {
 309     return AM3Opc & 0xFF;
 310   }
 311   static inline AddrOpc getAM3Op(unsigned AM3Opc) {
 312     return ((AM3Opc >> 8) & 1) ? sub : add;
 313   }
 314
 315   //===--------------------------------------------------------------------===//
 316   // Addressing Mode #4
 317   //===--------------------------------------------------------------------===//
 318   //
 319   // This is used for load / store multiple instructions.
 320   //
 321   // addrmode4 := reg, <mode>
 322   //
 323   // The four modes are:
 324   //    IA - Increment after
 325   //    IB - Increment before
 326   //    DA - Decrement after
 327   //    DB - Decrement before
 328   //
 329   // If the 4th bit (writeback)is set, then the base register is updated after
 330   // the memory transfer.
 331
 332   static inline AMSubMode getAM4SubMode(unsigned Mode) {
 333     return (AMSubMode)(Mode & 0x7);
 334   }
 335
 336   static inline unsigned getAM4ModeImm(AMSubMode SubMode, bool WB = false) {
 337     return (int)SubMode | ((int)WB << 3);
 338   }
 339
 340   static inline bool getAM4WBFlag(unsigned Mode) {
 341     return (Mode >> 3) & 1;
 342   }
 343
 344   //===--------------------------------------------------------------------===//
 345   // Addressing Mode #5
 346   //===--------------------------------------------------------------------===//
 347   //
 348   // This is used for coprocessor instructions, such as FP load/stores.
 349   //
 350   // addrmode5 := reg +/- imm8*4
 351   //
 352   // The first operand is always a Reg.  The third field encodes the operation
 353   // in bit 8, the immediate in bits 0-7.
 354   //
 355   // This can also be used for FP load/store multiple ops. The third field encodes
 356   // writeback mode in bit 8, the number of registers (or 2 times the number of
 357   // registers for DPR ops) in bits 0-7. In addition, bit 9-11 encodes one of the
 358   // following two sub-modes:
 359   //
 360   //    IA - Increment after
 361   //    DB - Decrement before
 362
 363   /// getAM5Opc - This function encodes the addrmode5 opc field.
 364   static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
 365     bool isSub = Opc == sub;
 366     return ((int)isSub << 8) | Offset;
 367   }
 368   static inline unsigned char getAM5Offset(unsigned AM5Opc) {
 369     return AM5Opc & 0xFF;
 370   }
 371   static inline AddrOpc getAM5Op(unsigned AM5Opc) {
 372     return ((AM5Opc >> 8) & 1) ? sub : add;
 373   }
 374
 375   /// getAM5Opc - This function encodes the addrmode5 opc field for FLDM and
 376   /// FSTM instructions.
 377   static inline unsigned getAM5Opc(AMSubMode SubMode, bool WB,
 378                                    unsigned char Offset) {
 379     assert((SubMode == ia || SubMode == db) &&
 380            "Illegal addressing mode 5 sub-mode!");
 381     return ((int)SubMode << 9) | ((int)WB << 8) | Offset;
 382   }
 383   static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
 384     return (AMSubMode)((AM5Opc >> 9) & 0x7);
 385   }
 386   static inline bool getAM5WBFlag(unsigned AM5Opc) {
 387     return ((AM5Opc >> 8) & 1);
 388   }
 389
 390 } // end namespace ARM_AM
 391 } // end namespace llvm
 392
 393 #endif
 394