lib/Target/ARM/ARMInstrInfo.h

   1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the ARM implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ARMINSTRUCTIONINFO_H
  15 #define ARMINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "ARMRegisterInfo.h"
  19 #include "ARM.h"
  20
  21 namespace llvm {
  22   class ARMSubtarget;
  23
  24 /// ARMII - This namespace holds all of the target specific flags that
  25 /// instruction info tracks.
  26 ///
  27 namespace ARMII {
  28   enum {
  29     //===------------------------------------------------------------------===//
  30     // Instruction Flags.
  31
  32     //===------------------------------------------------------------------===//
  33     // This four-bit field describes the addressing mode used.
  34
  35     AddrModeMask  = 0xf,
  36     AddrModeNone  = 0,
  37     AddrMode1     = 1,
  38     AddrMode2     = 2,
  39     AddrMode3     = 3,
  40     AddrMode4     = 4,
  41     AddrMode5     = 5,
  42     AddrModeT1    = 6,
  43     AddrModeT2    = 7,
  44     AddrModeT4    = 8,
  45     AddrModeTs    = 9,  // i8 * 4 for pc and sp relative data
  46
  47     // Size* - Flags to keep track of the size of an instruction.
  48     SizeShift     = 4,
  49     SizeMask      = 7 << SizeShift,
  50     SizeSpecial   = 1,   // 0 byte pseudo or special case.
  51     Size8Bytes    = 2,
  52     Size4Bytes    = 3,
  53     Size2Bytes    = 4,
  54
  55     // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
  56     // and store ops
  57     IndexModeShift = 7,
  58     IndexModeMask  = 3 << IndexModeShift,
  59     IndexModePre   = 1,
  60     IndexModePost  = 2,
  61
  62     //===------------------------------------------------------------------===//
  63     // Misc flags.
  64
  65     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
  66     // it doesn't have a Rn operand.
  67     UnaryDP       = 1 << 9,
  68
  69     //===------------------------------------------------------------------===//
  70     // Instruction encoding formats.
  71     //
  72     FormShift     = 10,
  73     FormMask      = 0x1f << FormShift,
  74
  75     // Pseudo instructions
  76     Pseudo        = 0  << FormShift,
  77
  78     // Multiply instructions
  79     MulFrm        = 1  << FormShift,
  80
  81     // Branch instructions
  82     BrFrm         = 2  << FormShift,
  83     BrMiscFrm     = 3  << FormShift,
  84
  85     // Data Processing instructions
  86     DPFrm         = 4  << FormShift,
  87     DPSoRegFrm    = 5  << FormShift,
  88
  89     // Load and Store
  90     LdFrm         = 6  << FormShift,
  91     StFrm         = 7  << FormShift,
  92     LdMiscFrm     = 8  << FormShift,
  93     StMiscFrm     = 9  << FormShift,
  94     LdStMulFrm    = 10 << FormShift,
  95
  96     // Miscellaneous arithmetic instructions
  97     ArithMiscFrm  = 11 << FormShift,
  98
  99     // Extend instructions
 100     ExtFrm        = 12 << FormShift,
 101
 102     // VFP formats
 103     VFPUnaryFrm   = 13 << FormShift,
 104     VFPBinaryFrm  = 14 << FormShift,
 105     VFPConv1Frm   = 15 << FormShift,
 106     VFPConv2Frm   = 16 << FormShift,
 107     VFPConv3Frm   = 17 << FormShift,
 108     VFPConv4Frm   = 18 << FormShift,
 109     VFPConv5Frm   = 19 << FormShift,
 110     VFPLdStFrm    = 20 << FormShift,
 111     VFPLdStMulFrm = 21 << FormShift,
 112     VFPMiscFrm    = 22 << FormShift,
 113
 114     // Thumb format
 115     ThumbFrm      = 23 << FormShift,
 116
 117     //===------------------------------------------------------------------===//
 118     // Field shifts - such shifts are used to set field while generating
 119     // machine instructions.
 120     M_BitShift     = 5,
 121     ShiftImmShift  = 5,
 122     ShiftShift     = 7,
 123     N_BitShift     = 7,
 124     ImmHiShift     = 8,
 125     SoRotImmShift  = 8,
 126     RegRsShift     = 8,
 127     ExtRotImmShift = 10,
 128     RegRdLoShift   = 12,
 129     RegRdShift     = 12,
 130     RegRdHiShift   = 16,
 131     RegRnShift     = 16,
 132     S_BitShift     = 20,
 133     W_BitShift     = 21,
 134     AM3_I_BitShift = 22,
 135     D_BitShift     = 22,
 136     U_BitShift     = 23,
 137     P_BitShift     = 24,
 138     I_BitShift     = 25,
 139     CondShift      = 28
 140   };
 141 }
 142
 143 class ARMInstrInfo : public TargetInstrInfoImpl {
 144   const ARMRegisterInfo RI;
 145 public:
 146   explicit ARMInstrInfo(const ARMSubtarget &STI);
 147
 148   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 149   /// such, whenever a client has an instance of instruction info, it should
 150   /// always be able to get register info as well (through this method).
 151   ///
 152   virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
 153
 154   /// Return true if the instruction is a register to register move and return
 155   /// the source and dest operands and their sub-register indices by reference.
 156   virtual bool isMoveInstr(const MachineInstr &MI,
 157                            unsigned &SrcReg, unsigned &DstReg,
 158                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
 159
 160   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
 161                                        int &FrameIndex) const;
 162   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
 163                                       int &FrameIndex) const;
 164
 165   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 166                      unsigned DestReg, const MachineInstr *Orig) const;
 167
 168   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
 169                                               MachineBasicBlock::iterator &MBBI,
 170                                               LiveVariables *LV) const;
 171
 172   // Branch analysis.
 173   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 174                              MachineBasicBlock *&FBB,
 175                              SmallVectorImpl<MachineOperand> &Cond,
 176                              bool AllowModify) const;
 177   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 178   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 179                                 MachineBasicBlock *FBB,
 180                             const SmallVectorImpl<MachineOperand> &Cond) const;
 181   virtual bool copyRegToReg(MachineBasicBlock &MBB,
 182                             MachineBasicBlock::iterator I,
 183                             unsigned DestReg, unsigned SrcReg,
 184                             const TargetRegisterClass *DestRC,
 185                             const TargetRegisterClass *SrcRC) const;
 186   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 187                                    MachineBasicBlock::iterator MBBI,
 188                                    unsigned SrcReg, bool isKill, int FrameIndex,
 189                                    const TargetRegisterClass *RC) const;
 190
 191   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
 192                               SmallVectorImpl<MachineOperand> &Addr,
 193                               const TargetRegisterClass *RC,
 194                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
 195
 196   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 197                                     MachineBasicBlock::iterator MBBI,
 198                                     unsigned DestReg, int FrameIndex,
 199                                     const TargetRegisterClass *RC) const;
 200
 201   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 202                                SmallVectorImpl<MachineOperand> &Addr,
 203                                const TargetRegisterClass *RC,
 204                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
 205   virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
 206                                          MachineBasicBlock::iterator MI,
 207                                  const std::vector<CalleeSavedInfo> &CSI) const;
 208   virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
 209                                            MachineBasicBlock::iterator MI,
 210                                  const std::vector<CalleeSavedInfo> &CSI) const;
 211
 212   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 213                                               MachineInstr* MI,
 214                                            const SmallVectorImpl<unsigned> &Ops,
 215                                               int FrameIndex) const;
 216
 217   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 218                                               MachineInstr* MI,
 219                                            const SmallVectorImpl<unsigned> &Ops,
 220                                               MachineInstr* LoadMI) const {
 221     return 0;
 222   }
 223
 224   virtual bool canFoldMemoryOperand(const MachineInstr *MI,
 225                                     const SmallVectorImpl<unsigned> &Ops) const;
 226
 227   virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
 228   virtual
 229   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 230
 231   // Predication support.
 232   virtual bool isPredicated(const MachineInstr *MI) const;
 233
 234   ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
 235     int PIdx = MI->findFirstPredOperandIdx();
 236     return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
 237                       : ARMCC::AL;
 238   }
 239
 240   virtual
 241   bool PredicateInstruction(MachineInstr *MI,
 242                             const SmallVectorImpl<MachineOperand> &Pred) const;
 243
 244   virtual
 245   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
 246                          const SmallVectorImpl<MachineOperand> &Pred2) const;
 247
 248   virtual bool DefinesPredicate(MachineInstr *MI,
 249                                 std::vector<MachineOperand> &Pred) const;
 250
 251   /// GetInstSize - Returns the size of the specified MachineInstr.
 252   ///
 253   virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
 254 };
 255
 256 }
 257
 258 #endif