In some rare cases, the register allocator can spill registers but end up not utilizi...

[llvm/msp430.git] / test / CodeGen / X86 / shift-i256.ll

; RUN: llvm-as < %s | llc -march=x86
; RUN: llvm-as < %s | llc -march=x86-64

define void @t(i256 %x, i256 %a, i256* nocapture %r) nounwind readnone {
entry:
        %0 = ashr i256 %x, %a
        store i256 %0, i256* %r
        ret void
}