lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/GCStrategy.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetAsmInfo.h"
  23 #include "llvm/Transforms/Scalar.h"
  24 #include "llvm/Support/CommandLine.h"
  25 #include "llvm/Support/raw_ostream.h"
  26 using namespace llvm;
  27
  28 namespace llvm {
  29   bool EnableFastISel;
  30 }
  31
  32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  33     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  35     cl::desc("Print LLVM IR input to isel pass"));
  36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  37     cl::desc("Dump emitter generated instructions as assembly"));
  38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  39     cl::desc("Dump garbage collector data"));
  40
  41 // When this works it will be on by default.
  42 static cl::opt<bool>
  43 DisablePostRAScheduler("disable-post-RA-scheduler",
  44                        cl::desc("Disable scheduling after register allocation"),
  45                        cl::init(true));
  46
  47 // Enable or disable FastISel. Both options are needed, because
  48 // FastISel is enabled by default with -fast, and we wish to be
  49 // able to enable or disable fast-isel independently from -fast.
  50 static cl::opt<cl::boolOrDefault>
  51 EnableFastISelOption("fast-isel", cl::Hidden,
  52   cl::desc("Enable the experimental \"fast\" instruction selector"));
  53
  54 FileModel::Model
  55 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  56                                        raw_ostream &Out,
  57                                        CodeGenFileType FileType,
  58                                        CodeGenOpt::Level OptLevel) {
  59   // Add common CodeGen passes.
  60   if (addCommonCodeGenPasses(PM, OptLevel))
  61     return FileModel::Error;
  62
  63   // Fold redundant debug labels.
  64   PM.add(createDebugLabelFoldingPass());
  65
  66   if (PrintMachineCode)
  67     PM.add(createMachineFunctionPrinterPass(cerr));
  68
  69   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
  70     PM.add(createMachineFunctionPrinterPass(cerr));
  71
  72   if (OptLevel != CodeGenOpt::None)
  73     PM.add(createCodePlacementOptPass());
  74
  75   switch (FileType) {
  76   default:
  77     break;
  78   case TargetMachine::AssemblyFile:
  79     if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
  80       return FileModel::Error;
  81     return FileModel::AsmFile;
  82   case TargetMachine::ObjectFile:
  83     if (getMachOWriterInfo())
  84       return FileModel::MachOFile;
  85     else if (getELFWriterInfo())
  86       return FileModel::ElfFile;
  87   }
  88
  89   return FileModel::Error;
  90 }
  91
  92 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
  93 /// be split up (e.g., to add an object writer pass), this method can be used to
  94 /// finish up adding passes to emit the file, if necessary.
  95 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
  96                                                   MachineCodeEmitter *MCE,
  97                                                   CodeGenOpt::Level OptLevel) {
  98   if (MCE)
  99     addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
 100
 101   PM.add(createGCInfoDeleter());
 102
 103   // Delete machine code for this function
 104   PM.add(createMachineCodeDeleter());
 105
 106   return false; // success!
 107 }
 108
 109 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 110 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 111 /// actually outputting the machine code and resolving things like the address
 112 /// of functions.  This method should returns true if machine code emission is
 113 /// not supported.
 114 ///
 115 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 116                                                    MachineCodeEmitter &MCE,
 117                                                    CodeGenOpt::Level OptLevel) {
 118   // Add common CodeGen passes.
 119   if (addCommonCodeGenPasses(PM, OptLevel))
 120     return true;
 121
 122   if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
 123     PM.add(createMachineFunctionPrinterPass(cerr));
 124
 125   addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
 126
 127   PM.add(createGCInfoDeleter());
 128
 129   // Delete machine code for this function
 130   PM.add(createMachineCodeDeleter());
 131
 132   return false; // success!
 133 }
 134
 135 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
 136 /// emitting to assembly files or machine code output.
 137 ///
 138 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
 139                                                CodeGenOpt::Level OptLevel) {
 140   // Standard LLVM-Level Passes.
 141
 142   // Run loop strength reduction before anything else.
 143   if (OptLevel != CodeGenOpt::None) {
 144     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 145     if (PrintLSR)
 146       PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
 147   }
 148
 149   PM.add(createGCLoweringPass());
 150
 151   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
 152     PM.add(createLowerInvokePass(getTargetLowering()));
 153
 154   // Make sure that no unreachable blocks are instruction selected.
 155   PM.add(createUnreachableBlockEliminationPass());
 156
 157   if (OptLevel != CodeGenOpt::None)
 158     PM.add(createCodeGenPreparePass(getTargetLowering()));
 159
 160   PM.add(createStackProtectorPass(getTargetLowering()));
 161
 162   if (PrintISelInput)
 163     PM.add(createPrintFunctionPass("\n\n"
 164                                    "*** Final LLVM Code input to ISel ***\n",
 165                                    &errs()));
 166
 167   // Standard Lower-Level Passes.
 168
 169   // Enable FastISel with -fast, but allow that to be overridden.
 170   if (EnableFastISelOption == cl::BOU_TRUE ||
 171       (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
 172     EnableFastISel = true;
 173
 174   // Ask the target for an isel.
 175   if (addInstSelector(PM, OptLevel))
 176     return true;
 177
 178   // Print the instruction selected machine code...
 179   if (PrintMachineCode)
 180     PM.add(createMachineFunctionPrinterPass(cerr));
 181
 182   if (OptLevel != CodeGenOpt::None) {
 183     PM.add(createMachineLICMPass());
 184     PM.add(createMachineSinkingPass());
 185   }
 186
 187   // Run pre-ra passes.
 188   if (addPreRegAlloc(PM, OptLevel) && PrintMachineCode)
 189     PM.add(createMachineFunctionPrinterPass(cerr));
 190
 191   // Perform register allocation.
 192   PM.add(createRegisterAllocator());
 193
 194   // Perform stack slot coloring.
 195   if (OptLevel != CodeGenOpt::None)
 196     PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
 197
 198   if (PrintMachineCode)  // Print the register-allocated code
 199     PM.add(createMachineFunctionPrinterPass(cerr));
 200
 201   // Run post-ra passes.
 202   if (addPostRegAlloc(PM, OptLevel) && PrintMachineCode)
 203     PM.add(createMachineFunctionPrinterPass(cerr));
 204
 205   if (PrintMachineCode)
 206     PM.add(createMachineFunctionPrinterPass(cerr));
 207
 208   PM.add(createLowerSubregsPass());
 209
 210   if (PrintMachineCode)  // Print the subreg lowered code
 211     PM.add(createMachineFunctionPrinterPass(cerr));
 212
 213   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 214   PM.add(createPrologEpilogCodeInserter());
 215
 216   if (PrintMachineCode)
 217     PM.add(createMachineFunctionPrinterPass(cerr));
 218
 219   // Second pass scheduler.
 220   if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
 221     PM.add(createPostRAScheduler());
 222
 223     if (PrintMachineCode)
 224       PM.add(createMachineFunctionPrinterPass(cerr));
 225   }
 226
 227   // Branch folding must be run after regalloc and prolog/epilog insertion.
 228   if (OptLevel != CodeGenOpt::None)
 229     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 230
 231   if (PrintMachineCode)
 232     PM.add(createMachineFunctionPrinterPass(cerr));
 233
 234   PM.add(createGCMachineCodeAnalysisPass());
 235
 236   if (PrintMachineCode)
 237     PM.add(createMachineFunctionPrinterPass(cerr));
 238
 239   if (PrintGCInfo)
 240     PM.add(createGCInfoPrinter(*cerr));
 241
 242   return false;
 243 }