lib/CodeGen/LowerSubregs.cpp

   1 //===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a MachineFunction pass which runs after register
  11 // allocation that turns subreg insert/extract instructions into register
  12 // copies, as needed. This ensures correct codegen even if the coalescer
  13 // isn't able to remove all subreg instructions.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #define DEBUG_TYPE "lowersubregs"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Function.h"
  20 #include "llvm/CodeGen/MachineFunctionPass.h"
  21 #include "llvm/CodeGen/MachineInstr.h"
  22 #include "llvm/CodeGen/MachineRegisterInfo.h"
  23 #include "llvm/Target/TargetRegisterInfo.h"
  24 #include "llvm/Target/TargetInstrInfo.h"
  25 #include "llvm/Target/TargetMachine.h"
  26 #include "llvm/Support/Debug.h"
  27 #include "llvm/Support/Compiler.h"
  28 using namespace llvm;
  29
  30 namespace {
  31   struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
  32    : public MachineFunctionPass {
  33     static char ID; // Pass identification, replacement for typeid
  34     LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
  35
  36     const char *getPassName() const {
  37       return "Subregister lowering instruction pass";
  38     }
  39
  40     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
  41       AU.addPreservedID(MachineLoopInfoID);
  42       AU.addPreservedID(MachineDominatorsID);
  43       MachineFunctionPass::getAnalysisUsage(AU);
  44     }
  45
  46     /// runOnMachineFunction - pass entry point
  47     bool runOnMachineFunction(MachineFunction&);
  48
  49     bool LowerExtract(MachineInstr *MI);
  50     bool LowerInsert(MachineInstr *MI);
  51     bool LowerSubregToReg(MachineInstr *MI);
  52
  53     void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
  54                           const TargetRegisterInfo &TRI);
  55     void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
  56                           const TargetRegisterInfo &TRI);
  57   };
  58
  59   char LowerSubregsInstructionPass::ID = 0;
  60 }
  61
  62 FunctionPass *llvm::createLowerSubregsPass() {
  63   return new LowerSubregsInstructionPass();
  64 }
  65
  66 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
  67 /// and the lowered replacement instructions immediately precede it.
  68 /// Mark the replacement instructions with the dead flag.
  69 void
  70 LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
  71                                               unsigned DstReg,
  72                                               const TargetRegisterInfo &TRI) {
  73   for (MachineBasicBlock::iterator MII =
  74         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  75     if (MII->addRegisterDead(DstReg, &TRI))
  76       break;
  77     assert(MII != MI->getParent()->begin() &&
  78            "copyRegToReg output doesn't reference destination register!");
  79   }
  80 }
  81
  82 /// TransferKillFlag - MI is a pseudo-instruction with SrcReg killed,
  83 /// and the lowered replacement instructions immediately precede it.
  84 /// Mark the replacement instructions with the kill flag.
  85 void
  86 LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
  87                                               unsigned SrcReg,
  88                                               const TargetRegisterInfo &TRI) {
  89   for (MachineBasicBlock::iterator MII =
  90         prior(MachineBasicBlock::iterator(MI)); ; --MII) {
  91     if (MII->addRegisterKilled(SrcReg, &TRI))
  92       break;
  93     assert(MII != MI->getParent()->begin() &&
  94            "copyRegToReg output doesn't reference source register!");
  95   }
  96 }
  97
  98 bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
  99   MachineBasicBlock *MBB = MI->getParent();
 100   MachineFunction &MF = *MBB->getParent();
 101   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 102   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 103
 104   assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
 105          MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
 106          MI->getOperand(2).isImm() && "Malformed extract_subreg");
 107
 108   unsigned DstReg   = MI->getOperand(0).getReg();
 109   unsigned SuperReg = MI->getOperand(1).getReg();
 110   unsigned SubIdx   = MI->getOperand(2).getImm();
 111   unsigned SrcReg   = TRI.getSubReg(SuperReg, SubIdx);
 112
 113   assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
 114          "Extract supperg source must be a physical register");
 115   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 116          "Extract destination must be in a physical register");
 117
 118   DOUT << "subreg: CONVERTING: " << *MI;
 119
 120   if (SrcReg == DstReg) {
 121     // No need to insert an identify copy instruction.
 122     DOUT << "subreg: eliminated!";
 123     // Find the kill of the destination register's live range, and insert
 124     // a kill of the source register at that point.
 125     if (MI->getOperand(1).isKill() && !MI->getOperand(0).isDead())
 126       for (MachineBasicBlock::iterator MII =
 127              next(MachineBasicBlock::iterator(MI));
 128            MII != MBB->end(); ++MII)
 129         if (MII->killsRegister(DstReg, &TRI)) {
 130           MII->addRegisterKilled(SuperReg, &TRI, /*AddIfNotFound=*/true);
 131           break;
 132         }
 133   } else {
 134     // Insert copy
 135     const TargetRegisterClass *TRC = TRI.getPhysicalRegisterRegClass(DstReg);
 136     assert(TRC == TRI.getPhysicalRegisterRegClass(SrcReg) &&
 137             "Extract subreg and Dst must be of same register class");
 138     TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
 139     // Transfer the kill/dead flags, if needed.
 140     if (MI->getOperand(0).isDead())
 141       TransferDeadFlag(MI, DstReg, TRI);
 142     if (MI->getOperand(1).isKill())
 143       TransferKillFlag(MI, SrcReg, TRI);
 144
 145 #ifndef NDEBUG
 146     MachineBasicBlock::iterator dMI = MI;
 147     DOUT << "subreg: " << *(--dMI);
 148 #endif
 149   }
 150
 151   DOUT << "\n";
 152   MBB->erase(MI);
 153   return true;
 154 }
 155
 156 bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
 157   MachineBasicBlock *MBB = MI->getParent();
 158   MachineFunction &MF = *MBB->getParent();
 159   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 160   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 161   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 162          MI->getOperand(1).isImm() &&
 163          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 164           MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
 165
 166   unsigned DstReg  = MI->getOperand(0).getReg();
 167   unsigned InsReg  = MI->getOperand(2).getReg();
 168   unsigned InsSIdx = MI->getOperand(2).getSubReg();
 169   unsigned SubIdx  = MI->getOperand(3).getImm();
 170
 171   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 172   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 173
 174   assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
 175          "Insert destination must be in a physical register");
 176   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 177          "Inserted value must be in a physical register");
 178
 179   DOUT << "subreg: CONVERTING: " << *MI;
 180
 181   if (DstSubReg == InsReg && InsSIdx == 0) {
 182     // No need to insert an identify copy instruction.
 183     // Watch out for case like this:
 184     // %RAX<def> = ...
 185     // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
 186     // The first def is defining RAX, not EAX so the top bits were not
 187     // zero extended.
 188     DOUT << "subreg: eliminated!";
 189   } else {
 190     // Insert sub-register copy
 191     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 192     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 193     TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 194     // Transfer the kill/dead flags, if needed.
 195     if (MI->getOperand(0).isDead())
 196       TransferDeadFlag(MI, DstSubReg, TRI);
 197     if (MI->getOperand(2).isKill())
 198       TransferKillFlag(MI, InsReg, TRI);
 199
 200 #ifndef NDEBUG
 201     MachineBasicBlock::iterator dMI = MI;
 202     DOUT << "subreg: " << *(--dMI);
 203 #endif
 204   }
 205
 206   DOUT << "\n";
 207   MBB->erase(MI);
 208   return true;
 209 }
 210
 211 bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
 212   MachineBasicBlock *MBB = MI->getParent();
 213   MachineFunction &MF = *MBB->getParent();
 214   const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
 215   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
 216   assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
 217          (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
 218          (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
 219           MI->getOperand(3).isImm() && "Invalid insert_subreg");
 220
 221   unsigned DstReg = MI->getOperand(0).getReg();
 222 #ifndef NDEBUG
 223   unsigned SrcReg = MI->getOperand(1).getReg();
 224 #endif
 225   unsigned InsReg = MI->getOperand(2).getReg();
 226   unsigned SubIdx = MI->getOperand(3).getImm();
 227
 228   assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
 229   assert(SubIdx != 0 && "Invalid index for insert_subreg");
 230   unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
 231
 232   assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
 233          "Insert superreg source must be in a physical register");
 234   assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
 235          "Inserted value must be in a physical register");
 236
 237   DOUT << "subreg: CONVERTING: " << *MI;
 238
 239   if (DstSubReg == InsReg) {
 240     // No need to insert an identify copy instruction.
 241     DOUT << "subreg: eliminated!";
 242   } else {
 243     // Insert sub-register copy
 244     const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
 245     const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
 246     TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
 247     // Transfer the kill/dead flags, if needed.
 248     if (MI->getOperand(0).isDead())
 249       TransferDeadFlag(MI, DstSubReg, TRI);
 250     if (MI->getOperand(1).isKill())
 251       TransferKillFlag(MI, InsReg, TRI);
 252
 253 #ifndef NDEBUG
 254     MachineBasicBlock::iterator dMI = MI;
 255     DOUT << "subreg: " << *(--dMI);
 256 #endif
 257   }
 258
 259   DOUT << "\n";
 260   MBB->erase(MI);
 261   return true;
 262 }
 263
 264 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 265 /// copies.
 266 ///
 267 bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
 268   DOUT << "Machine Function\n";
 269
 270   bool MadeChange = false;
 271
 272   DOUT << "********** LOWERING SUBREG INSTRS **********\n";
 273   DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
 274
 275   for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
 276        mbbi != mbbe; ++mbbi) {
 277     for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
 278          mi != me;) {
 279       MachineInstr *MI = mi++;
 280
 281       if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
 282         MadeChange |= LowerExtract(MI);
 283       } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
 284         MadeChange |= LowerInsert(MI);
 285       } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
 286         MadeChange |= LowerSubregToReg(MI);
 287       }
 288     }
 289   }
 290
 291   return MadeChange;
 292 }