lib/CodeGen/SelectionDAG/FastISel.cpp

   1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the implementation of the FastISel class.
  11 //
  12 // "Fast" instruction selection is designed to emit very poor code quickly.
  13 // Also, it is not designed to be able to do much lowering, so most illegal
  14 // types (e.g. i64 on 32-bit targets) and operations are not supported.  It is
  15 // also not intended to be able to do much optimization, except in a few cases
  16 // where doing optimizations reduces overall compile time.  For example, folding
  17 // constants into immediate fields is often done, because it's cheap and it
  18 // reduces the number of instructions later phases have to examine.
  19 //
  20 // "Fast" instruction selection is able to fail gracefully and transfer
  21 // control to the SelectionDAG selector for operations that it doesn't
  22 // support.  In many cases, this allows us to avoid duplicating a lot of
  23 // the complicated lowering logic that SelectionDAG currently has.
  24 //
  25 // The intended use for "fast" instruction selection is "-O0" mode
  26 // compilation, where the quality of the generated code is irrelevant when
  27 // weighed against the speed at which the code can be generated.  Also,
  28 // at -O0, the LLVM optimizers are not running, and this makes the
  29 // compile time of codegen a much higher portion of the overall compile
  30 // time.  Despite its limitations, "fast" instruction selection is able to
  31 // handle enough code on its own to provide noticeable overall speedups
  32 // in -O0 compiles.
  33 //
  34 // Basic operations are supported in a target-independent way, by reading
  35 // the same instruction descriptions that the SelectionDAG selector reads,
  36 // and identifying simple arithmetic operations that can be directly selected
  37 // from simple operators.  More complicated operations currently require
  38 // target-specific code.
  39 //
  40 //===----------------------------------------------------------------------===//
  41
  42 #include "llvm/Function.h"
  43 #include "llvm/GlobalVariable.h"
  44 #include "llvm/Instructions.h"
  45 #include "llvm/IntrinsicInst.h"
  46 #include "llvm/CodeGen/FastISel.h"
  47 #include "llvm/CodeGen/MachineInstrBuilder.h"
  48 #include "llvm/CodeGen/MachineModuleInfo.h"
  49 #include "llvm/CodeGen/MachineRegisterInfo.h"
  50 #include "llvm/CodeGen/DebugLoc.h"
  51 #include "llvm/CodeGen/DwarfWriter.h"
  52 #include "llvm/Analysis/DebugInfo.h"
  53 #include "llvm/Target/TargetData.h"
  54 #include "llvm/Target/TargetInstrInfo.h"
  55 #include "llvm/Target/TargetLowering.h"
  56 #include "llvm/Target/TargetMachine.h"
  57 #include "SelectionDAGBuild.h"
  58 using namespace llvm;
  59
  60 unsigned FastISel::getRegForValue(Value *V) {
  61   MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
  62   // Don't handle non-simple values in FastISel.
  63   if (!RealVT.isSimple())
  64     return 0;
  65
  66   // Ignore illegal types. We must do this before looking up the value
  67   // in ValueMap because Arguments are given virtual registers regardless
  68   // of whether FastISel can handle them.
  69   MVT::SimpleValueType VT = RealVT.getSimpleVT();
  70   if (!TLI.isTypeLegal(VT)) {
  71     // Promote MVT::i1 to a legal type though, because it's common and easy.
  72     if (VT == MVT::i1)
  73       VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
  74     else
  75       return 0;
  76   }
  77
  78   // Look up the value to see if we already have a register for it. We
  79   // cache values defined by Instructions across blocks, and other values
  80   // only locally. This is because Instructions already have the SSA
  81   // def-dominatess-use requirement enforced.
  82   if (ValueMap.count(V))
  83     return ValueMap[V];
  84   unsigned Reg = LocalValueMap[V];
  85   if (Reg != 0)
  86     return Reg;
  87
  88   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
  89     if (CI->getValue().getActiveBits() <= 64)
  90       Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
  91   } else if (isa<AllocaInst>(V)) {
  92     Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
  93   } else if (isa<ConstantPointerNull>(V)) {
  94     // Translate this as an integer zero so that it can be
  95     // local-CSE'd with actual integer zeros.
  96     Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
  97   } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
  98     Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
  99
 100     if (!Reg) {
 101       const APFloat &Flt = CF->getValueAPF();
 102       MVT IntVT = TLI.getPointerTy();
 103
 104       uint64_t x[2];
 105       uint32_t IntBitWidth = IntVT.getSizeInBits();
 106       bool isExact;
 107       (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
 108                                 APFloat::rmTowardZero, &isExact);
 109       if (isExact) {
 110         APInt IntVal(IntBitWidth, 2, x);
 111
 112         unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
 113         if (IntegerReg != 0)
 114           Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
 115       }
 116     }
 117   } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
 118     if (!SelectOperator(CE, CE->getOpcode())) return 0;
 119     Reg = LocalValueMap[CE];
 120   } else if (isa<UndefValue>(V)) {
 121     Reg = createResultReg(TLI.getRegClassFor(VT));
 122     BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
 123   }
 124
 125   // If target-independent code couldn't handle the value, give target-specific
 126   // code a try.
 127   if (!Reg && isa<Constant>(V))
 128     Reg = TargetMaterializeConstant(cast<Constant>(V));
 129
 130   // Don't cache constant materializations in the general ValueMap.
 131   // To do so would require tracking what uses they dominate.
 132   if (Reg != 0)
 133     LocalValueMap[V] = Reg;
 134   return Reg;
 135 }
 136
 137 unsigned FastISel::lookUpRegForValue(Value *V) {
 138   // Look up the value to see if we already have a register for it. We
 139   // cache values defined by Instructions across blocks, and other values
 140   // only locally. This is because Instructions already have the SSA
 141   // def-dominatess-use requirement enforced.
 142   if (ValueMap.count(V))
 143     return ValueMap[V];
 144   return LocalValueMap[V];
 145 }
 146
 147 /// UpdateValueMap - Update the value map to include the new mapping for this
 148 /// instruction, or insert an extra copy to get the result in a previous
 149 /// determined register.
 150 /// NOTE: This is only necessary because we might select a block that uses
 151 /// a value before we select the block that defines the value.  It might be
 152 /// possible to fix this by selecting blocks in reverse postorder.
 153 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
 154   if (!isa<Instruction>(I)) {
 155     LocalValueMap[I] = Reg;
 156     return Reg;
 157   }
 158
 159   unsigned &AssignedReg = ValueMap[I];
 160   if (AssignedReg == 0)
 161     AssignedReg = Reg;
 162   else if (Reg != AssignedReg) {
 163     const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
 164     TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
 165                      Reg, RegClass, RegClass);
 166   }
 167   return AssignedReg;
 168 }
 169
 170 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
 171   unsigned IdxN = getRegForValue(Idx);
 172   if (IdxN == 0)
 173     // Unhandled operand. Halt "fast" selection and bail.
 174     return 0;
 175
 176   // If the index is smaller or larger than intptr_t, truncate or extend it.
 177   MVT PtrVT = TLI.getPointerTy();
 178   MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
 179   if (IdxVT.bitsLT(PtrVT))
 180     IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
 181                       ISD::SIGN_EXTEND, IdxN);
 182   else if (IdxVT.bitsGT(PtrVT))
 183     IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
 184                       ISD::TRUNCATE, IdxN);
 185   return IdxN;
 186 }
 187
 188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
 189 /// which has an opcode which directly corresponds to the given ISD opcode.
 190 ///
 191 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
 192   MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
 193   if (VT == MVT::Other || !VT.isSimple())
 194     // Unhandled type. Halt "fast" selection and bail.
 195     return false;
 196
 197   // We only handle legal types. For example, on x86-32 the instruction
 198   // selector contains all of the 64-bit instructions from x86-64,
 199   // under the assumption that i64 won't be used if the target doesn't
 200   // support it.
 201   if (!TLI.isTypeLegal(VT)) {
 202     // MVT::i1 is special. Allow AND, OR, or XOR because they
 203     // don't require additional zeroing, which makes them easy.
 204     if (VT == MVT::i1 &&
 205         (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
 206          ISDOpcode == ISD::XOR))
 207       VT = TLI.getTypeToTransformTo(VT);
 208     else
 209       return false;
 210   }
 211
 212   unsigned Op0 = getRegForValue(I->getOperand(0));
 213   if (Op0 == 0)
 214     // Unhandled operand. Halt "fast" selection and bail.
 215     return false;
 216
 217   // Check if the second operand is a constant and handle it appropriately.
 218   if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
 219     unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
 220                                      ISDOpcode, Op0, CI->getZExtValue());
 221     if (ResultReg != 0) {
 222       // We successfully emitted code for the given LLVM Instruction.
 223       UpdateValueMap(I, ResultReg);
 224       return true;
 225     }
 226   }
 227
 228   // Check if the second operand is a constant float.
 229   if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
 230     unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
 231                                      ISDOpcode, Op0, CF);
 232     if (ResultReg != 0) {
 233       // We successfully emitted code for the given LLVM Instruction.
 234       UpdateValueMap(I, ResultReg);
 235       return true;
 236     }
 237   }
 238
 239   unsigned Op1 = getRegForValue(I->getOperand(1));
 240   if (Op1 == 0)
 241     // Unhandled operand. Halt "fast" selection and bail.
 242     return false;
 243
 244   // Now we have both operands in registers. Emit the instruction.
 245   unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
 246                                    ISDOpcode, Op0, Op1);
 247   if (ResultReg == 0)
 248     // Target-specific code wasn't able to find a machine opcode for
 249     // the given ISD opcode and type. Halt "fast" selection and bail.
 250     return false;
 251
 252   // We successfully emitted code for the given LLVM Instruction.
 253   UpdateValueMap(I, ResultReg);
 254   return true;
 255 }
 256
 257 bool FastISel::SelectGetElementPtr(User *I) {
 258   unsigned N = getRegForValue(I->getOperand(0));
 259   if (N == 0)
 260     // Unhandled operand. Halt "fast" selection and bail.
 261     return false;
 262
 263   const Type *Ty = I->getOperand(0)->getType();
 264   MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
 265   for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
 266        OI != E; ++OI) {
 267     Value *Idx = *OI;
 268     if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
 269       unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
 270       if (Field) {
 271         // N = N + Offset
 272         uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
 273         // FIXME: This can be optimized by combining the add with a
 274         // subsequent one.
 275         N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
 276         if (N == 0)
 277           // Unhandled operand. Halt "fast" selection and bail.
 278           return false;
 279       }
 280       Ty = StTy->getElementType(Field);
 281     } else {
 282       Ty = cast<SequentialType>(Ty)->getElementType();
 283
 284       // If this is a constant subscript, handle it quickly.
 285       if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
 286         if (CI->getZExtValue() == 0) continue;
 287         uint64_t Offs =
 288           TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
 289         N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
 290         if (N == 0)
 291           // Unhandled operand. Halt "fast" selection and bail.
 292           return false;
 293         continue;
 294       }
 295
 296       // N = N + Idx * ElementSize;
 297       uint64_t ElementSize = TD.getTypeAllocSize(Ty);
 298       unsigned IdxN = getRegForGEPIndex(Idx);
 299       if (IdxN == 0)
 300         // Unhandled operand. Halt "fast" selection and bail.
 301         return false;
 302
 303       if (ElementSize != 1) {
 304         IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
 305         if (IdxN == 0)
 306           // Unhandled operand. Halt "fast" selection and bail.
 307           return false;
 308       }
 309       N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
 310       if (N == 0)
 311         // Unhandled operand. Halt "fast" selection and bail.
 312         return false;
 313     }
 314   }
 315
 316   // We successfully emitted code for the given LLVM Instruction.
 317   UpdateValueMap(I, N);
 318   return true;
 319 }
 320
 321 bool FastISel::SelectCall(User *I) {
 322   Function *F = cast<CallInst>(I)->getCalledFunction();
 323   if (!F) return false;
 324
 325   unsigned IID = F->getIntrinsicID();
 326   switch (IID) {
 327   default: break;
 328   case Intrinsic::dbg_stoppoint: {
 329     DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
 330     if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
 331       DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
 332       unsigned Line = SPI->getLine();
 333       unsigned Col = SPI->getColumn();
 334       unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col);
 335       setCurDebugLoc(DebugLoc::get(Idx));
 336     }
 337     return true;
 338   }
 339   case Intrinsic::dbg_region_start: {
 340     DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
 341     if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) &&
 342         DW && DW->ShouldEmitDwarfDebug()) {
 343       unsigned ID =
 344         DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
 345       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 346       BuildMI(MBB, DL, II).addImm(ID);
 347     }
 348     return true;
 349   }
 350   case Intrinsic::dbg_region_end: {
 351     DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
 352     if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) &&
 353         DW && DW->ShouldEmitDwarfDebug()) {
 354      unsigned ID = 0;
 355      DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
 356      if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
 357         // This is end of an inlined function.
 358         const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 359         ID = DW->RecordInlinedFnEnd(Subprogram);
 360         if (ID)
 361           // Returned ID is 0 if this is unbalanced "end of inlined
 362           // scope". This could happen if optimizer eats dbg intrinsics
 363           // or "beginning of inlined scope" is not recoginized due to
 364           // missing location info. In such cases, do ignore this region.end.
 365           BuildMI(MBB, DL, II).addImm(ID);
 366       } else {
 367         const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 368         ID =  DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
 369         BuildMI(MBB, DL, II).addImm(ID);
 370       }
 371     }
 372     return true;
 373   }
 374   case Intrinsic::dbg_func_start: {
 375     DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
 376     Value *SP = FSI->getSubprogram();
 377     if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None))
 378       return true;
 379
 380     // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
 381     // (most?) gdb expects.
 382     DebugLoc PrevLoc = DL;
 383     DISubprogram Subprogram(cast<GlobalVariable>(SP));
 384     DICompileUnit CompileUnit = Subprogram.getCompileUnit();
 385
 386     if (!Subprogram.describes(MF.getFunction())) {
 387       // This is a beginning of an inlined function.
 388
 389       // If llvm.dbg.func.start is seen in a new block before any
 390       // llvm.dbg.stoppoint intrinsic then the location info is unknown.
 391       // FIXME : Why DebugLoc is reset at the beginning of each block ?
 392       if (PrevLoc.isUnknown())
 393         return true;
 394       // Record the source line.
 395       unsigned Line = Subprogram.getLineNumber();
 396       setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
 397                                               CompileUnit.getGV(), Line, 0)));
 398
 399       if (DW && DW->ShouldEmitDwarfDebug()) {
 400         DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
 401         unsigned LabelID = DW->RecordInlinedFnStart(Subprogram,
 402                                           DICompileUnit(PrevLocTpl.CompileUnit),
 403                                           PrevLocTpl.Line,
 404                                           PrevLocTpl.Col);
 405         const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
 406         BuildMI(MBB, DL, II).addImm(LabelID);
 407       }
 408     } else {
 409       // Record the source line.
 410       unsigned Line = Subprogram.getLineNumber();
 411       MF.setDefaultDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
 412                                               CompileUnit.getGV(), Line, 0)));
 413       if (DW && DW->ShouldEmitDwarfDebug()) {
 414         // llvm.dbg.func_start also defines beginning of function scope.
 415         DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
 416       }
 417     }
 418
 419     return true;
 420   }
 421   case Intrinsic::dbg_declare: {
 422     DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
 423     Value *Variable = DI->getVariable();
 424     if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) &&
 425         DW && DW->ShouldEmitDwarfDebug()) {
 426       // Determine the address of the declared object.
 427       Value *Address = DI->getAddress();
 428       if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
 429         Address = BCI->getOperand(0);
 430       AllocaInst *AI = dyn_cast<AllocaInst>(Address);
 431       // Don't handle byval struct arguments or VLAs, for example.
 432       if (!AI) break;
 433       DenseMap<const AllocaInst*, int>::iterator SI =
 434         StaticAllocaMap.find(AI);
 435       if (SI == StaticAllocaMap.end()) break; // VLAs.
 436       int FI = SI->second;
 437
 438       // Determine the debug globalvariable.
 439       GlobalValue *GV = cast<GlobalVariable>(Variable);
 440
 441       // Build the DECLARE instruction.
 442       const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
 443       MachineInstr *DeclareMI
 444         = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
 445       DIVariable DV(cast<GlobalVariable>(GV));
 446       if (!DV.isNull()) {
 447         // This is a local variable
 448         DW->RecordVariableScope(DV, DeclareMI);
 449       }
 450     }
 451     return true;
 452   }
 453   case Intrinsic::eh_exception: {
 454     MVT VT = TLI.getValueType(I->getType());
 455     switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
 456     default: break;
 457     case TargetLowering::Expand: {
 458       if (!MBB->isLandingPad()) {
 459         // FIXME: Mark exception register as live in.  Hack for PR1508.
 460         unsigned Reg = TLI.getExceptionAddressRegister();
 461         if (Reg) MBB->addLiveIn(Reg);
 462       }
 463       unsigned Reg = TLI.getExceptionAddressRegister();
 464       const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 465       unsigned ResultReg = createResultReg(RC);
 466       bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 467                                            Reg, RC, RC);
 468       assert(InsertedCopy && "Can't copy address registers!");
 469       InsertedCopy = InsertedCopy;
 470       UpdateValueMap(I, ResultReg);
 471       return true;
 472     }
 473     }
 474     break;
 475   }
 476   case Intrinsic::eh_selector_i32:
 477   case Intrinsic::eh_selector_i64: {
 478     MVT VT = TLI.getValueType(I->getType());
 479     switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
 480     default: break;
 481     case TargetLowering::Expand: {
 482       MVT VT = (IID == Intrinsic::eh_selector_i32 ?
 483                            MVT::i32 : MVT::i64);
 484
 485       if (MMI) {
 486         if (MBB->isLandingPad())
 487           AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
 488         else {
 489 #ifndef NDEBUG
 490           CatchInfoLost.insert(cast<CallInst>(I));
 491 #endif
 492           // FIXME: Mark exception selector register as live in.  Hack for PR1508.
 493           unsigned Reg = TLI.getExceptionSelectorRegister();
 494           if (Reg) MBB->addLiveIn(Reg);
 495         }
 496
 497         unsigned Reg = TLI.getExceptionSelectorRegister();
 498         const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
 499         unsigned ResultReg = createResultReg(RC);
 500         bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 501                                              Reg, RC, RC);
 502         assert(InsertedCopy && "Can't copy address registers!");
 503         InsertedCopy = InsertedCopy;
 504         UpdateValueMap(I, ResultReg);
 505       } else {
 506         unsigned ResultReg =
 507           getRegForValue(Constant::getNullValue(I->getType()));
 508         UpdateValueMap(I, ResultReg);
 509       }
 510       return true;
 511     }
 512     }
 513     break;
 514   }
 515   }
 516   return false;
 517 }
 518
 519 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
 520   MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 521   MVT DstVT = TLI.getValueType(I->getType());
 522
 523   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
 524       DstVT == MVT::Other || !DstVT.isSimple())
 525     // Unhandled type. Halt "fast" selection and bail.
 526     return false;
 527
 528   // Check if the destination type is legal. Or as a special case,
 529   // it may be i1 if we're doing a truncate because that's
 530   // easy and somewhat common.
 531   if (!TLI.isTypeLegal(DstVT))
 532     if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
 533       // Unhandled type. Halt "fast" selection and bail.
 534       return false;
 535
 536   // Check if the source operand is legal. Or as a special case,
 537   // it may be i1 if we're doing zero-extension because that's
 538   // easy and somewhat common.
 539   if (!TLI.isTypeLegal(SrcVT))
 540     if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
 541       // Unhandled type. Halt "fast" selection and bail.
 542       return false;
 543
 544   unsigned InputReg = getRegForValue(I->getOperand(0));
 545   if (!InputReg)
 546     // Unhandled operand.  Halt "fast" selection and bail.
 547     return false;
 548
 549   // If the operand is i1, arrange for the high bits in the register to be zero.
 550   if (SrcVT == MVT::i1) {
 551    SrcVT = TLI.getTypeToTransformTo(SrcVT);
 552    InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
 553    if (!InputReg)
 554      return false;
 555   }
 556   // If the result is i1, truncate to the target's type for i1 first.
 557   if (DstVT == MVT::i1)
 558     DstVT = TLI.getTypeToTransformTo(DstVT);
 559
 560   unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
 561                                   DstVT.getSimpleVT(),
 562                                   Opcode,
 563                                   InputReg);
 564   if (!ResultReg)
 565     return false;
 566
 567   UpdateValueMap(I, ResultReg);
 568   return true;
 569 }
 570
 571 bool FastISel::SelectBitCast(User *I) {
 572   // If the bitcast doesn't change the type, just use the operand value.
 573   if (I->getType() == I->getOperand(0)->getType()) {
 574     unsigned Reg = getRegForValue(I->getOperand(0));
 575     if (Reg == 0)
 576       return false;
 577     UpdateValueMap(I, Reg);
 578     return true;
 579   }
 580
 581   // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
 582   MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 583   MVT DstVT = TLI.getValueType(I->getType());
 584
 585   if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
 586       DstVT == MVT::Other || !DstVT.isSimple() ||
 587       !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
 588     // Unhandled type. Halt "fast" selection and bail.
 589     return false;
 590
 591   unsigned Op0 = getRegForValue(I->getOperand(0));
 592   if (Op0 == 0)
 593     // Unhandled operand. Halt "fast" selection and bail.
 594     return false;
 595
 596   // First, try to perform the bitcast by inserting a reg-reg copy.
 597   unsigned ResultReg = 0;
 598   if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
 599     TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
 600     TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
 601     ResultReg = createResultReg(DstClass);
 602
 603     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 604                                          Op0, DstClass, SrcClass);
 605     if (!InsertedCopy)
 606       ResultReg = 0;
 607   }
 608
 609   // If the reg-reg copy failed, select a BIT_CONVERT opcode.
 610   if (!ResultReg)
 611     ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
 612                            ISD::BIT_CONVERT, Op0);
 613
 614   if (!ResultReg)
 615     return false;
 616
 617   UpdateValueMap(I, ResultReg);
 618   return true;
 619 }
 620
 621 bool
 622 FastISel::SelectInstruction(Instruction *I) {
 623   return SelectOperator(I, I->getOpcode());
 624 }
 625
 626 /// FastEmitBranch - Emit an unconditional branch to the given block,
 627 /// unless it is the immediate (fall-through) successor, and update
 628 /// the CFG.
 629 void
 630 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
 631   MachineFunction::iterator NextMBB =
 632      next(MachineFunction::iterator(MBB));
 633
 634   if (MBB->isLayoutSuccessor(MSucc)) {
 635     // The unconditional fall-through case, which needs no instructions.
 636   } else {
 637     // The unconditional branch case.
 638     TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
 639   }
 640   MBB->addSuccessor(MSucc);
 641 }
 642
 643 bool
 644 FastISel::SelectOperator(User *I, unsigned Opcode) {
 645   switch (Opcode) {
 646   case Instruction::Add: {
 647     ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
 648     return SelectBinaryOp(I, Opc);
 649   }
 650   case Instruction::Sub: {
 651     ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
 652     return SelectBinaryOp(I, Opc);
 653   }
 654   case Instruction::Mul: {
 655     ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
 656     return SelectBinaryOp(I, Opc);
 657   }
 658   case Instruction::SDiv:
 659     return SelectBinaryOp(I, ISD::SDIV);
 660   case Instruction::UDiv:
 661     return SelectBinaryOp(I, ISD::UDIV);
 662   case Instruction::FDiv:
 663     return SelectBinaryOp(I, ISD::FDIV);
 664   case Instruction::SRem:
 665     return SelectBinaryOp(I, ISD::SREM);
 666   case Instruction::URem:
 667     return SelectBinaryOp(I, ISD::UREM);
 668   case Instruction::FRem:
 669     return SelectBinaryOp(I, ISD::FREM);
 670   case Instruction::Shl:
 671     return SelectBinaryOp(I, ISD::SHL);
 672   case Instruction::LShr:
 673     return SelectBinaryOp(I, ISD::SRL);
 674   case Instruction::AShr:
 675     return SelectBinaryOp(I, ISD::SRA);
 676   case Instruction::And:
 677     return SelectBinaryOp(I, ISD::AND);
 678   case Instruction::Or:
 679     return SelectBinaryOp(I, ISD::OR);
 680   case Instruction::Xor:
 681     return SelectBinaryOp(I, ISD::XOR);
 682
 683   case Instruction::GetElementPtr:
 684     return SelectGetElementPtr(I);
 685
 686   case Instruction::Br: {
 687     BranchInst *BI = cast<BranchInst>(I);
 688
 689     if (BI->isUnconditional()) {
 690       BasicBlock *LLVMSucc = BI->getSuccessor(0);
 691       MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
 692       FastEmitBranch(MSucc);
 693       return true;
 694     }
 695
 696     // Conditional branches are not handed yet.
 697     // Halt "fast" selection and bail.
 698     return false;
 699   }
 700
 701   case Instruction::Unreachable:
 702     // Nothing to emit.
 703     return true;
 704
 705   case Instruction::PHI:
 706     // PHI nodes are already emitted.
 707     return true;
 708
 709   case Instruction::Alloca:
 710     // FunctionLowering has the static-sized case covered.
 711     if (StaticAllocaMap.count(cast<AllocaInst>(I)))
 712       return true;
 713
 714     // Dynamic-sized alloca is not handled yet.
 715     return false;
 716
 717   case Instruction::Call:
 718     return SelectCall(I);
 719
 720   case Instruction::BitCast:
 721     return SelectBitCast(I);
 722
 723   case Instruction::FPToSI:
 724     return SelectCast(I, ISD::FP_TO_SINT);
 725   case Instruction::ZExt:
 726     return SelectCast(I, ISD::ZERO_EXTEND);
 727   case Instruction::SExt:
 728     return SelectCast(I, ISD::SIGN_EXTEND);
 729   case Instruction::Trunc:
 730     return SelectCast(I, ISD::TRUNCATE);
 731   case Instruction::SIToFP:
 732     return SelectCast(I, ISD::SINT_TO_FP);
 733
 734   case Instruction::IntToPtr: // Deliberate fall-through.
 735   case Instruction::PtrToInt: {
 736     MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
 737     MVT DstVT = TLI.getValueType(I->getType());
 738     if (DstVT.bitsGT(SrcVT))
 739       return SelectCast(I, ISD::ZERO_EXTEND);
 740     if (DstVT.bitsLT(SrcVT))
 741       return SelectCast(I, ISD::TRUNCATE);
 742     unsigned Reg = getRegForValue(I->getOperand(0));
 743     if (Reg == 0) return false;
 744     UpdateValueMap(I, Reg);
 745     return true;
 746   }
 747
 748   default:
 749     // Unhandled instruction. Halt "fast" selection and bail.
 750     return false;
 751   }
 752 }
 753
 754 FastISel::FastISel(MachineFunction &mf,
 755                    MachineModuleInfo *mmi,
 756                    DwarfWriter *dw,
 757                    DenseMap<const Value *, unsigned> &vm,
 758                    DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
 759                    DenseMap<const AllocaInst *, int> &am
 760 #ifndef NDEBUG
 761                    , SmallSet<Instruction*, 8> &cil
 762 #endif
 763                    )
 764   : MBB(0),
 765     ValueMap(vm),
 766     MBBMap(bm),
 767     StaticAllocaMap(am),
 768 #ifndef NDEBUG
 769     CatchInfoLost(cil),
 770 #endif
 771     MF(mf),
 772     MMI(mmi),
 773     DW(dw),
 774     MRI(MF.getRegInfo()),
 775     MFI(*MF.getFrameInfo()),
 776     MCP(*MF.getConstantPool()),
 777     TM(MF.getTarget()),
 778     TD(*TM.getTargetData()),
 779     TII(*TM.getInstrInfo()),
 780     TLI(*TM.getTargetLowering()) {
 781 }
 782
 783 FastISel::~FastISel() {}
 784
 785 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
 786                              ISD::NodeType) {
 787   return 0;
 788 }
 789
 790 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
 791                               ISD::NodeType, unsigned /*Op0*/) {
 792   return 0;
 793 }
 794
 795 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
 796                                ISD::NodeType, unsigned /*Op0*/,
 797                                unsigned /*Op0*/) {
 798   return 0;
 799 }
 800
 801 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
 802                               ISD::NodeType, uint64_t /*Imm*/) {
 803   return 0;
 804 }
 805
 806 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
 807                               ISD::NodeType, ConstantFP * /*FPImm*/) {
 808   return 0;
 809 }
 810
 811 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
 812                                ISD::NodeType, unsigned /*Op0*/,
 813                                uint64_t /*Imm*/) {
 814   return 0;
 815 }
 816
 817 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
 818                                ISD::NodeType, unsigned /*Op0*/,
 819                                ConstantFP * /*FPImm*/) {
 820   return 0;
 821 }
 822
 823 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
 824                                 ISD::NodeType,
 825                                 unsigned /*Op0*/, unsigned /*Op1*/,
 826                                 uint64_t /*Imm*/) {
 827   return 0;
 828 }
 829
 830 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
 831 /// to emit an instruction with an immediate operand using FastEmit_ri.
 832 /// If that fails, it materializes the immediate into a register and try
 833 /// FastEmit_rr instead.
 834 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
 835                                 unsigned Op0, uint64_t Imm,
 836                                 MVT::SimpleValueType ImmType) {
 837   // First check if immediate type is legal. If not, we can't use the ri form.
 838   unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
 839   if (ResultReg != 0)
 840     return ResultReg;
 841   unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
 842   if (MaterialReg == 0)
 843     return 0;
 844   return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 845 }
 846
 847 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
 848 /// to emit an instruction with a floating-point immediate operand using
 849 /// FastEmit_rf. If that fails, it materializes the immediate into a register
 850 /// and try FastEmit_rr instead.
 851 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
 852                                 unsigned Op0, ConstantFP *FPImm,
 853                                 MVT::SimpleValueType ImmType) {
 854   // First check if immediate type is legal. If not, we can't use the rf form.
 855   unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
 856   if (ResultReg != 0)
 857     return ResultReg;
 858
 859   // Materialize the constant in a register.
 860   unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
 861   if (MaterialReg == 0) {
 862     // If the target doesn't have a way to directly enter a floating-point
 863     // value into a register, use an alternate approach.
 864     // TODO: The current approach only supports floating-point constants
 865     // that can be constructed by conversion from integer values. This should
 866     // be replaced by code that creates a load from a constant-pool entry,
 867     // which will require some target-specific work.
 868     const APFloat &Flt = FPImm->getValueAPF();
 869     MVT IntVT = TLI.getPointerTy();
 870
 871     uint64_t x[2];
 872     uint32_t IntBitWidth = IntVT.getSizeInBits();
 873     bool isExact;
 874     (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
 875                              APFloat::rmTowardZero, &isExact);
 876     if (!isExact)
 877       return 0;
 878     APInt IntVal(IntBitWidth, 2, x);
 879
 880     unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
 881                                      ISD::Constant, IntVal.getZExtValue());
 882     if (IntegerReg == 0)
 883       return 0;
 884     MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
 885                              ISD::SINT_TO_FP, IntegerReg);
 886     if (MaterialReg == 0)
 887       return 0;
 888   }
 889   return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 890 }
 891
 892 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
 893   return MRI.createVirtualRegister(RC);
 894 }
 895
 896 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
 897                                  const TargetRegisterClass* RC) {
 898   unsigned ResultReg = createResultReg(RC);
 899   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 900
 901   BuildMI(MBB, DL, II, ResultReg);
 902   return ResultReg;
 903 }
 904
 905 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
 906                                   const TargetRegisterClass *RC,
 907                                   unsigned Op0) {
 908   unsigned ResultReg = createResultReg(RC);
 909   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 910
 911   if (II.getNumDefs() >= 1)
 912     BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
 913   else {
 914     BuildMI(MBB, DL, II).addReg(Op0);
 915     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 916                                          II.ImplicitDefs[0], RC, RC);
 917     if (!InsertedCopy)
 918       ResultReg = 0;
 919   }
 920
 921   return ResultReg;
 922 }
 923
 924 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
 925                                    const TargetRegisterClass *RC,
 926                                    unsigned Op0, unsigned Op1) {
 927   unsigned ResultReg = createResultReg(RC);
 928   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 929
 930   if (II.getNumDefs() >= 1)
 931     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
 932   else {
 933     BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
 934     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 935                                          II.ImplicitDefs[0], RC, RC);
 936     if (!InsertedCopy)
 937       ResultReg = 0;
 938   }
 939   return ResultReg;
 940 }
 941
 942 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
 943                                    const TargetRegisterClass *RC,
 944                                    unsigned Op0, uint64_t Imm) {
 945   unsigned ResultReg = createResultReg(RC);
 946   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 947
 948   if (II.getNumDefs() >= 1)
 949     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
 950   else {
 951     BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
 952     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 953                                          II.ImplicitDefs[0], RC, RC);
 954     if (!InsertedCopy)
 955       ResultReg = 0;
 956   }
 957   return ResultReg;
 958 }
 959
 960 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
 961                                    const TargetRegisterClass *RC,
 962                                    unsigned Op0, ConstantFP *FPImm) {
 963   unsigned ResultReg = createResultReg(RC);
 964   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 965
 966   if (II.getNumDefs() >= 1)
 967     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
 968   else {
 969     BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
 970     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 971                                          II.ImplicitDefs[0], RC, RC);
 972     if (!InsertedCopy)
 973       ResultReg = 0;
 974   }
 975   return ResultReg;
 976 }
 977
 978 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
 979                                     const TargetRegisterClass *RC,
 980                                     unsigned Op0, unsigned Op1, uint64_t Imm) {
 981   unsigned ResultReg = createResultReg(RC);
 982   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
 983
 984   if (II.getNumDefs() >= 1)
 985     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
 986   else {
 987     BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
 988     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
 989                                          II.ImplicitDefs[0], RC, RC);
 990     if (!InsertedCopy)
 991       ResultReg = 0;
 992   }
 993   return ResultReg;
 994 }
 995
 996 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
 997                                   const TargetRegisterClass *RC,
 998                                   uint64_t Imm) {
 999   unsigned ResultReg = createResultReg(RC);
1000   const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1001
1002   if (II.getNumDefs() >= 1)
1003     BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1004   else {
1005     BuildMI(MBB, DL, II).addImm(Imm);
1006     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1007                                          II.ImplicitDefs[0], RC, RC);
1008     if (!InsertedCopy)
1009       ResultReg = 0;
1010   }
1011   return ResultReg;
1012 }
1013
1014 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
1015                                               unsigned Op0, uint32_t Idx) {
1016   const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1017
1018   unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1019   const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1020
1021   if (II.getNumDefs() >= 1)
1022     BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1023   else {
1024     BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1025     bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1026                                          II.ImplicitDefs[0], RC, RC);
1027     if (!InsertedCopy)
1028       ResultReg = 0;
1029   }
1030   return ResultReg;
1031 }
1032
1033 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1034 /// with all but the least significant bit set to zero.
1035 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
1036   return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
1037 }