lib/Target/ARM/ARM.h

   1 //===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the entry points for global functions defined in the LLVM
  11 // ARM back-end.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef TARGET_ARM_H
  16 #define TARGET_ARM_H
  17
  18 #include "llvm/Target/TargetMachine.h"
  19 #include <cassert>
  20
  21 namespace llvm {
  22
  23 class ARMTargetMachine;
  24 class FunctionPass;
  25 class MachineCodeEmitter;
  26 class raw_ostream;
  27
  28 // Enums corresponding to ARM condition codes
  29 namespace ARMCC {
  30   // The CondCodes constants map directly to the 4-bit encoding of the
  31   // condition field for predicated instructions.
  32   enum CondCodes {
  33     EQ,
  34     NE,
  35     HS,
  36     LO,
  37     MI,
  38     PL,
  39     VS,
  40     VC,
  41     HI,
  42     LS,
  43     GE,
  44     LT,
  45     GT,
  46     LE,
  47     AL
  48   };
  49
  50   inline static CondCodes getOppositeCondition(CondCodes CC){
  51     switch (CC) {
  52     default: assert(0 && "Unknown condition code");
  53     case EQ: return NE;
  54     case NE: return EQ;
  55     case HS: return LO;
  56     case LO: return HS;
  57     case MI: return PL;
  58     case PL: return MI;
  59     case VS: return VC;
  60     case VC: return VS;
  61     case HI: return LS;
  62     case LS: return HI;
  63     case GE: return LT;
  64     case LT: return GE;
  65     case GT: return LE;
  66     case LE: return GT;
  67     }
  68   }
  69 }
  70
  71 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
  72   switch (CC) {
  73   default: assert(0 && "Unknown condition code");
  74   case ARMCC::EQ:  return "eq";
  75   case ARMCC::NE:  return "ne";
  76   case ARMCC::HS:  return "hs";
  77   case ARMCC::LO:  return "lo";
  78   case ARMCC::MI:  return "mi";
  79   case ARMCC::PL:  return "pl";
  80   case ARMCC::VS:  return "vs";
  81   case ARMCC::VC:  return "vc";
  82   case ARMCC::HI:  return "hi";
  83   case ARMCC::LS:  return "ls";
  84   case ARMCC::GE:  return "ge";
  85   case ARMCC::LT:  return "lt";
  86   case ARMCC::GT:  return "gt";
  87   case ARMCC::LE:  return "le";
  88   case ARMCC::AL:  return "al";
  89   }
  90 }
  91
  92 FunctionPass *createARMISelDag(ARMTargetMachine &TM);
  93 FunctionPass *createARMCodePrinterPass(raw_ostream &O,
  94                                        ARMTargetMachine &TM,
  95                                        CodeGenOpt::Level OptLevel,
  96                                        bool Verbose);
  97 FunctionPass *createARMCodeEmitterPass(ARMTargetMachine &TM,
  98                                        MachineCodeEmitter &MCE);
  99 FunctionPass *createARMLoadStoreOptimizationPass();
 100 FunctionPass *createARMConstantIslandPass();
 101
 102 } // end namespace llvm;
 103
 104 // Defines symbolic names for ARM registers.  This defines a mapping from
 105 // register name to register number.
 106 //
 107 #include "ARMGenRegisterNames.inc"
 108
 109 // Defines symbolic names for the ARM instructions.
 110 //
 111 #include "ARMGenInstrNames.inc"
 112
 113
 114 #endif