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Merge branch 'master' into msp430
[llvm/msp430.git] / lib / Target / ARM / ARMISelLowering.cpp
blobd3cf6675f2961caa9bb90a00f4a212a95123e21e
1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ARM.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Instruction.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/VectorExtras.h"
39 #include "llvm/Support/MathExtras.h"
40 using namespace llvm;
41
42 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
43 CCValAssign::LocInfo &LocInfo,
44 ISD::ArgFlagsTy &ArgFlags,
45 CCState &State);
46 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
49 CCState &State);
50 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
53 CCState &State);
54 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
55 CCValAssign::LocInfo &LocInfo,
56 ISD::ArgFlagsTy &ArgFlags,
57 CCState &State);
58
59 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
60 : TargetLowering(TM), ARMPCLabelIndex(0) {
61 Subtarget = &TM.getSubtarget<ARMSubtarget>();
62
63 if (Subtarget->isTargetDarwin()) {
64 // Uses VFP for Thumb libfuncs if available.
65 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
66 // Single-precision floating-point arithmetic.
67 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
68 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
69 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
70 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
71
72 // Double-precision floating-point arithmetic.
73 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
74 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
75 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
76 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
77
78 // Single-precision comparisons.
79 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
80 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
81 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
82 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
83 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
84 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
85 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
86 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
87
88 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
89 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
90 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
96
97 // Double-precision comparisons.
98 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
99 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
100 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
101 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
102 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
103 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
104 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
105 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
106
107 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
108 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
109 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
110 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
111 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
112 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
113 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
114 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
115
116 // Floating-point to integer conversions.
117 // i64 conversions are done via library routines even when generating VFP
118 // instructions, so use the same ones.
119 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
120 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
121 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
122 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
123
124 // Conversions between floating types.
125 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
126 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
127
128 // Integer to floating-point conversions.
129 // i64 conversions are done via library routines even when generating VFP
130 // instructions, so use the same ones.
131 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
132 // e.g., __floatunsidf vs. __floatunssidfvfp.
133 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
134 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
135 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
136 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
137 }
138 }
139
140 if (Subtarget->isThumb())
141 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
142 else
143 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
144 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
145 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
146 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
147
148 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
149 }
150 computeRegisterProperties();
151
152 // ARM does not have f32 extending load.
153 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
154
155 // ARM does not have i1 sign extending load.
156 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
157
158 // ARM supports all 4 flavors of integer indexed load / store.
159 for (unsigned im = (unsigned)ISD::PRE_INC;
160 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
161 setIndexedLoadAction(im, MVT::i1, Legal);
162 setIndexedLoadAction(im, MVT::i8, Legal);
163 setIndexedLoadAction(im, MVT::i16, Legal);
164 setIndexedLoadAction(im, MVT::i32, Legal);
165 setIndexedStoreAction(im, MVT::i1, Legal);
166 setIndexedStoreAction(im, MVT::i8, Legal);
167 setIndexedStoreAction(im, MVT::i16, Legal);
168 setIndexedStoreAction(im, MVT::i32, Legal);
169 }
170
171 // i64 operation support.
172 if (Subtarget->isThumb()) {
173 setOperationAction(ISD::MUL, MVT::i64, Expand);
174 setOperationAction(ISD::MULHU, MVT::i32, Expand);
175 setOperationAction(ISD::MULHS, MVT::i32, Expand);
176 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
177 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
178 } else {
179 setOperationAction(ISD::MUL, MVT::i64, Expand);
180 setOperationAction(ISD::MULHU, MVT::i32, Expand);
181 if (!Subtarget->hasV6Ops())
182 setOperationAction(ISD::MULHS, MVT::i32, Expand);
183 }
184 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
185 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
186 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
187 setOperationAction(ISD::SRL, MVT::i64, Custom);
188 setOperationAction(ISD::SRA, MVT::i64, Custom);
189
190 // ARM does not have ROTL.
191 setOperationAction(ISD::ROTL, MVT::i32, Expand);
192 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
193 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
194 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
195 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
196
197 // Only ARMv6 has BSWAP.
198 if (!Subtarget->hasV6Ops())
199 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
200
201 // These are expanded into libcalls.
202 setOperationAction(ISD::SDIV, MVT::i32, Expand);
203 setOperationAction(ISD::UDIV, MVT::i32, Expand);
204 setOperationAction(ISD::SREM, MVT::i32, Expand);
205 setOperationAction(ISD::UREM, MVT::i32, Expand);
206 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
207 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
208
209 // Support label based line numbers.
210 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
211 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
212
213 setOperationAction(ISD::RET, MVT::Other, Custom);
214 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
216 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
217 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
218
219 // Use the default implementation.
220 setOperationAction(ISD::VASTART, MVT::Other, Custom);
221 setOperationAction(ISD::VAARG, MVT::Other, Expand);
222 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
223 setOperationAction(ISD::VAEND, MVT::Other, Expand);
224 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
225 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
227 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
228
229 if (!Subtarget->hasV6Ops()) {
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
232 }
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
234
235 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
236 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
237 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
238
239 // We want to custom lower some of our intrinsics.
240 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
241
242 setOperationAction(ISD::SETCC, MVT::i32, Expand);
243 setOperationAction(ISD::SETCC, MVT::f32, Expand);
244 setOperationAction(ISD::SETCC, MVT::f64, Expand);
245 setOperationAction(ISD::SELECT, MVT::i32, Expand);
246 setOperationAction(ISD::SELECT, MVT::f32, Expand);
247 setOperationAction(ISD::SELECT, MVT::f64, Expand);
248 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
249 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
250 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
251
252 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
253 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
254 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
255 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
256 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
257
258 // We don't support sin/cos/fmod/copysign/pow
259 setOperationAction(ISD::FSIN, MVT::f64, Expand);
260 setOperationAction(ISD::FSIN, MVT::f32, Expand);
261 setOperationAction(ISD::FCOS, MVT::f32, Expand);
262 setOperationAction(ISD::FCOS, MVT::f64, Expand);
263 setOperationAction(ISD::FREM, MVT::f64, Expand);
264 setOperationAction(ISD::FREM, MVT::f32, Expand);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
266 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
267 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
268 }
269 setOperationAction(ISD::FPOW, MVT::f64, Expand);
270 setOperationAction(ISD::FPOW, MVT::f32, Expand);
271
272 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
273 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
274 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
275 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
276 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
278 }
279
280 // We have target-specific dag combine patterns for the following nodes:
281 // ARMISD::FMRRD - No need to call setTargetDAGCombine
282 setTargetDAGCombine(ISD::ADD);
283 setTargetDAGCombine(ISD::SUB);
284
285 setStackPointerRegisterToSaveRestore(ARM::SP);
286 setSchedulingPreference(SchedulingForRegPressure);
287 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
288 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
289
290 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
291 benefitFromCodePlacementOpt = true;
292 }
293
294 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
295 switch (Opcode) {
296 default: return 0;
297 case ARMISD::Wrapper: return "ARMISD::Wrapper";
298 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
299 case ARMISD::CALL: return "ARMISD::CALL";
300 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
301 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
302 case ARMISD::tCALL: return "ARMISD::tCALL";
303 case ARMISD::BRCOND: return "ARMISD::BRCOND";
304 case ARMISD::BR_JT: return "ARMISD::BR_JT";
305 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
306 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
307 case ARMISD::CMP: return "ARMISD::CMP";
308 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
309 case ARMISD::CMPFP: return "ARMISD::CMPFP";
310 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
311 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
312 case ARMISD::CMOV: return "ARMISD::CMOV";
313 case ARMISD::CNEG: return "ARMISD::CNEG";
314
315 case ARMISD::FTOSI: return "ARMISD::FTOSI";
316 case ARMISD::FTOUI: return "ARMISD::FTOUI";
317 case ARMISD::SITOF: return "ARMISD::SITOF";
318 case ARMISD::UITOF: return "ARMISD::UITOF";
319
320 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
321 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
322 case ARMISD::RRX: return "ARMISD::RRX";
323
324 case ARMISD::FMRRD: return "ARMISD::FMRRD";
325 case ARMISD::FMDRR: return "ARMISD::FMDRR";
326
327 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
328 }
329 }
330
331 //===----------------------------------------------------------------------===//
332 // Lowering Code
333 //===----------------------------------------------------------------------===//
334
335 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
336 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
337 switch (CC) {
338 default: assert(0 && "Unknown condition code!");
339 case ISD::SETNE: return ARMCC::NE;
340 case ISD::SETEQ: return ARMCC::EQ;
341 case ISD::SETGT: return ARMCC::GT;
342 case ISD::SETGE: return ARMCC::GE;
343 case ISD::SETLT: return ARMCC::LT;
344 case ISD::SETLE: return ARMCC::LE;
345 case ISD::SETUGT: return ARMCC::HI;
346 case ISD::SETUGE: return ARMCC::HS;
347 case ISD::SETULT: return ARMCC::LO;
348 case ISD::SETULE: return ARMCC::LS;
349 }
350 }
351
352 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
353 /// returns true if the operands should be inverted to form the proper
354 /// comparison.
355 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
356 ARMCC::CondCodes &CondCode2) {
357 bool Invert = false;
358 CondCode2 = ARMCC::AL;
359 switch (CC) {
360 default: assert(0 && "Unknown FP condition!");
361 case ISD::SETEQ:
362 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
363 case ISD::SETGT:
364 case ISD::SETOGT: CondCode = ARMCC::GT; break;
365 case ISD::SETGE:
366 case ISD::SETOGE: CondCode = ARMCC::GE; break;
367 case ISD::SETOLT: CondCode = ARMCC::MI; break;
368 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
369 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
370 case ISD::SETO: CondCode = ARMCC::VC; break;
371 case ISD::SETUO: CondCode = ARMCC::VS; break;
372 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
373 case ISD::SETUGT: CondCode = ARMCC::HI; break;
374 case ISD::SETUGE: CondCode = ARMCC::PL; break;
375 case ISD::SETLT:
376 case ISD::SETULT: CondCode = ARMCC::LT; break;
377 case ISD::SETLE:
378 case ISD::SETULE: CondCode = ARMCC::LE; break;
379 case ISD::SETNE:
380 case ISD::SETUNE: CondCode = ARMCC::NE; break;
381 }
382 return Invert;
383 }
384
385 //===----------------------------------------------------------------------===//
386 // Calling Convention Implementation
387 //
388 // The lower operations present on calling convention works on this order:
389 // LowerCALL (virt regs --> phys regs, virt regs --> stack)
390 // LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
391 // LowerRET (virt regs --> phys regs)
392 // LowerCALL (phys regs --> virt regs)
393 //
394 //===----------------------------------------------------------------------===//
395
396 #include "ARMGenCallingConv.inc"
397
398 // APCS f64 is in register pairs, possibly split to stack
399 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
400 CCValAssign::LocInfo &LocInfo,
401 ISD::ArgFlagsTy &ArgFlags,
402 CCState &State) {
403 static const unsigned HiRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
404 static const unsigned LoRegList[] = { ARM::R1,
405 ARM::R2,
406 ARM::R3,
407 ARM::NoRegister };
408
409 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4);
410 if (Reg == 0)
411 return false; // we didn't handle it
412
413 unsigned i;
414 for (i = 0; i < 4; ++i)
415 if (HiRegList[i] == Reg)
416 break;
417
418 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
419 if (LoRegList[i] != ARM::NoRegister)
420 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
421 MVT::i32, LocInfo));
422 else
423 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
424 State.AllocateStack(4, 4),
425 MVT::i32, LocInfo));
426 return true; // we handled it
427 }
428
429 // AAPCS f64 is in aligned register pairs
430 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
431 CCValAssign::LocInfo &LocInfo,
432 ISD::ArgFlagsTy &ArgFlags,
433 CCState &State) {
434 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
435 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
436
437 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
438 if (Reg == 0)
439 return false; // we didn't handle it
440
441 unsigned i;
442 for (i = 0; i < 2; ++i)
443 if (HiRegList[i] == Reg)
444 break;
445
446 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
447 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
448 MVT::i32, LocInfo));
449 return true; // we handled it
450 }
451
452 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
453 CCValAssign::LocInfo &LocInfo,
454 ISD::ArgFlagsTy &ArgFlags,
455 CCState &State) {
456 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
457 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
458
459 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
460 if (Reg == 0)
461 return false; // we didn't handle it
462
463 unsigned i;
464 for (i = 0; i < 2; ++i)
465 if (HiRegList[i] == Reg)
466 break;
467
468 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
469 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
470 MVT::i32, LocInfo));
471 return true; // we handled it
472 }
473
474 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
475 CCValAssign::LocInfo &LocInfo,
476 ISD::ArgFlagsTy &ArgFlags,
477 CCState &State) {
478 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
479 State);
480 }
481
482 /// LowerCallResult - Lower the result values of an ISD::CALL into the
483 /// appropriate copies out of appropriate physical registers. This assumes that
484 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
485 /// being lowered. The returns a SDNode with the same number of values as the
486 /// ISD::CALL.
487 SDNode *ARMTargetLowering::
488 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
489 unsigned CallingConv, SelectionDAG &DAG) {
490
491 DebugLoc dl = TheCall->getDebugLoc();
492 // Assign locations to each value returned by this call.
493 SmallVector<CCValAssign, 16> RVLocs;
494 bool isVarArg = TheCall->isVarArg();
495 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
496 CCInfo.AnalyzeCallResult(TheCall, RetCC_ARM);
497
498 SmallVector<SDValue, 8> ResultVals;
499
500 // Copy all of the result registers out of their specified physreg.
501 for (unsigned i = 0; i != RVLocs.size(); ++i) {
502 CCValAssign VA = RVLocs[i];
503
504 SDValue Val;
505 if (VA.needsCustom()) {
506 // Handle f64 as custom.
507 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
508 InFlag);
509 Chain = Lo.getValue(1);
510 InFlag = Lo.getValue(2);
511 VA = RVLocs[++i]; // skip ahead to next loc
512 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
513 InFlag);
514 Chain = Hi.getValue(1);
515 InFlag = Hi.getValue(2);
516 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
517 } else {
518 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
519 InFlag);
520 Chain = Val.getValue(1);
521 InFlag = Val.getValue(2);
522 }
523
524 switch (VA.getLocInfo()) {
525 default: assert(0 && "Unknown loc info!");
526 case CCValAssign::Full: break;
527 case CCValAssign::BCvt:
528 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
529 break;
530 }
531
532 ResultVals.push_back(Val);
533 }
534
535 // Merge everything together with a MERGE_VALUES node.
536 ResultVals.push_back(Chain);
537 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
538 &ResultVals[0], ResultVals.size()).getNode();
539 }
540
541 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
542 /// by "Src" to address "Dst" of size "Size". Alignment information is
543 /// specified by the specific parameter attribute. The copy will be passed as
544 /// a byval function parameter.
545 /// Sometimes what we are copying is the end of a larger object, the part that
546 /// does not fit in registers.
547 static SDValue
548 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
549 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
550 DebugLoc dl) {
551 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
552 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
553 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
554 }
555
556 /// LowerMemOpCallTo - Store the argument to the stack.
557 SDValue
558 ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
559 const SDValue &StackPtr,
560 const CCValAssign &VA, SDValue Chain,
561 SDValue Arg, ISD::ArgFlagsTy Flags) {
562 DebugLoc dl = TheCall->getDebugLoc();
563 unsigned LocMemOffset = VA.getLocMemOffset();
564 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
565 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
566 if (Flags.isByVal()) {
567 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
568 }
569 return DAG.getStore(Chain, dl, Arg, PtrOff,
570 PseudoSourceValue::getStack(), LocMemOffset);
571 }
572
573 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
574 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
575 /// nodes.
576 SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
577 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
578 MVT RetVT = TheCall->getRetValType(0);
579 SDValue Chain = TheCall->getChain();
580 unsigned CC = TheCall->getCallingConv();
581 assert((CC == CallingConv::C ||
582 CC == CallingConv::Fast) && "unknown calling convention");
583 bool isVarArg = TheCall->isVarArg();
584 SDValue Callee = TheCall->getCallee();
585 DebugLoc dl = TheCall->getDebugLoc();
586
587 // Analyze operands of the call, assigning locations to each operand.
588 SmallVector<CCValAssign, 16> ArgLocs;
589 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
590 CCInfo.AnalyzeCallOperands(TheCall, CC_ARM);
591
592 // Get a count of how many bytes are to be pushed on the stack.
593 unsigned NumBytes = CCInfo.getNextStackOffset();
594
595 // Adjust the stack pointer for the new arguments...
596 // These operations are automatically eliminated by the prolog/epilog pass
597 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
598
599 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
600
601 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
602 SmallVector<SDValue, 8> MemOpChains;
603
604 // Walk the register/memloc assignments, inserting copies/loads. In the case
605 // of tail call optimization, arguments are handled later.
606 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
607 i != e;
608 ++i, ++realArgIdx) {
609 CCValAssign &VA = ArgLocs[i];
610 SDValue Arg = TheCall->getArg(realArgIdx);
611 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx);
612
613 // Promote the value if needed.
614 switch (VA.getLocInfo()) {
615 default: assert(0 && "Unknown loc info!");
616 case CCValAssign::Full: break;
617 case CCValAssign::SExt:
618 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
619 break;
620 case CCValAssign::ZExt:
621 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
622 break;
623 case CCValAssign::AExt:
624 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
625 break;
626 case CCValAssign::BCvt:
627 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
628 break;
629 }
630
631 // f64 is passed in i32 pairs and must be combined
632 if (VA.needsCustom()) {
633 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
634 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
635 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
636 VA = ArgLocs[++i]; // skip ahead to next loc
637 if (VA.isRegLoc())
638 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(1)));
639 else {
640 assert(VA.isMemLoc());
641 if (StackPtr.getNode() == 0)
642 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
643
644 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
645 Chain, fmrrd.getValue(1),
646 Flags));
647 }
648 } else if (VA.isRegLoc()) {
649 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
650 } else {
651 assert(VA.isMemLoc());
652 if (StackPtr.getNode() == 0)
653 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
654
655 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
656 Chain, Arg, Flags));
657 }
658 }
659
660 if (!MemOpChains.empty())
661 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
662 &MemOpChains[0], MemOpChains.size());
663
664 // Build a sequence of copy-to-reg nodes chained together with token chain
665 // and flag operands which copy the outgoing args into the appropriate regs.
666 SDValue InFlag;
667 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
668 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
669 RegsToPass[i].second, InFlag);
670 InFlag = Chain.getValue(1);
671 }
672
673 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
674 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
675 // node so that legalize doesn't hack it.
676 bool isDirect = false;
677 bool isARMFunc = false;
678 bool isLocalARMFunc = false;
679 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
680 GlobalValue *GV = G->getGlobal();
681 isDirect = true;
682 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
683 GV->hasLinkOnceLinkage());
684 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
685 getTargetMachine().getRelocationModel() != Reloc::Static;
686 isARMFunc = !Subtarget->isThumb() || isStub;
687 // ARM call to a local ARM function is predicable.
688 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
689 // tBX takes a register source operand.
690 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
691 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
692 ARMCP::CPStub, 4);
693 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
694 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
695 Callee = DAG.getLoad(getPointerTy(), dl,
696 DAG.getEntryNode(), CPAddr, NULL, 0);
697 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
698 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
699 getPointerTy(), Callee, PICLabel);
700 } else
701 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
702 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
703 isDirect = true;
704 bool isStub = Subtarget->isTargetDarwin() &&
705 getTargetMachine().getRelocationModel() != Reloc::Static;
706 isARMFunc = !Subtarget->isThumb() || isStub;
707 // tBX takes a register source operand.
708 const char *Sym = S->getSymbol();
709 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
710 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
711 ARMCP::CPStub, 4);
712 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
713 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
714 Callee = DAG.getLoad(getPointerTy(), dl,
715 DAG.getEntryNode(), CPAddr, NULL, 0);
716 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
717 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
718 getPointerTy(), Callee, PICLabel);
719 } else
720 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
721 }
722
723 // FIXME: handle tail calls differently.
724 unsigned CallOpc;
725 if (Subtarget->isThumb()) {
726 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
727 CallOpc = ARMISD::CALL_NOLINK;
728 else
729 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
730 } else {
731 CallOpc = (isDirect || Subtarget->hasV5TOps())
732 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
733 : ARMISD::CALL_NOLINK;
734 }
735 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
736 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
737 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
738 InFlag = Chain.getValue(1);
739 }
740
741 std::vector<SDValue> Ops;
742 Ops.push_back(Chain);
743 Ops.push_back(Callee);
744
745 // Add argument registers to the end of the list so that they are known live
746 // into the call.
747 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
748 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
749 RegsToPass[i].second.getValueType()));
750
751 if (InFlag.getNode())
752 Ops.push_back(InFlag);
753 // Returns a chain and a flag for retval copy to use.
754 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
755 &Ops[0], Ops.size());
756 InFlag = Chain.getValue(1);
757
758 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
759 DAG.getIntPtrConstant(0, true), InFlag);
760 if (RetVT != MVT::Other)
761 InFlag = Chain.getValue(1);
762
763 // Handle result values, copying them out of physregs into vregs that we
764 // return.
765 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
766 Op.getResNo());
767 }
768
769 SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
770 // The chain is always operand #0
771 SDValue Chain = Op.getOperand(0);
772 DebugLoc dl = Op.getDebugLoc();
773
774 // CCValAssign - represent the assignment of the return value to a location.
775 SmallVector<CCValAssign, 16> RVLocs;
776 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
777 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
778
779 // CCState - Info about the registers and stack slots.
780 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
781
782 // Analyze return values of ISD::RET.
783 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_ARM);
784
785 // If this is the first return lowered for this function, add
786 // the regs to the liveout set for the function.
787 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
788 for (unsigned i = 0; i != RVLocs.size(); ++i)
789 if (RVLocs[i].isRegLoc())
790 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
791 }
792
793 SDValue Flag;
794
795 // Copy the result values into the output registers.
796 for (unsigned i = 0, realRVLocIdx = 0;
797 i != RVLocs.size();
798 ++i, ++realRVLocIdx) {
799 CCValAssign &VA = RVLocs[i];
800 assert(VA.isRegLoc() && "Can only return in registers!");
801
802 // ISD::RET => ret chain, (regnum1,val1), ...
803 // So i*2+1 index only the regnums
804 SDValue Arg = Op.getOperand(realRVLocIdx*2+1);
805
806 switch (VA.getLocInfo()) {
807 default: assert(0 && "Unknown loc info!");
808 case CCValAssign::Full: break;
809 case CCValAssign::BCvt:
810 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
811 break;
812 }
813
814 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
815 // available.
816 if (VA.needsCustom()) {
817 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
818 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
819 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
820 Flag = Chain.getValue(1);
821 VA = RVLocs[++i]; // skip ahead to next loc
822 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
823 Flag);
824 } else
825 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
826
827 // Guarantee that all emitted copies are
828 // stuck together, avoiding something bad.
829 Flag = Chain.getValue(1);
830 }
831
832 SDValue result;
833 if (Flag.getNode())
834 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
835 else // Return Void
836 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
837
838 return result;
839 }
840
841 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
842 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
843 // one of the above mentioned nodes. It has to be wrapped because otherwise
844 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
845 // be used to form addressing mode. These wrapped nodes will be selected
846 // into MOVi.
847 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
848 MVT PtrVT = Op.getValueType();
849 // FIXME there is no actual debug info here
850 DebugLoc dl = Op.getDebugLoc();
851 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
852 SDValue Res;
853 if (CP->isMachineConstantPoolEntry())
854 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
855 CP->getAlignment());
856 else
857 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
858 CP->getAlignment());
859 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
860 }
861
862 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
863 SDValue
864 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
865 SelectionDAG &DAG) {
866 DebugLoc dl = GA->getDebugLoc();
867 MVT PtrVT = getPointerTy();
868 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
869 ARMConstantPoolValue *CPV =
870 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
871 PCAdj, "tlsgd", true);
872 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
873 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
874 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
875 SDValue Chain = Argument.getValue(1);
876
877 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
878 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
879
880 // call __tls_get_addr.
881 ArgListTy Args;
882 ArgListEntry Entry;
883 Entry.Node = Argument;
884 Entry.Ty = (const Type *) Type::Int32Ty;
885 Args.push_back(Entry);
886 // FIXME: is there useful debug info available here?
887 std::pair<SDValue, SDValue> CallResult =
888 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
889 CallingConv::C, false,
890 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
891 return CallResult.first;
892 }
893
894 // Lower ISD::GlobalTLSAddress using the "initial exec" or
895 // "local exec" model.
896 SDValue
897 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
898 SelectionDAG &DAG) {
899 GlobalValue *GV = GA->getGlobal();
900 DebugLoc dl = GA->getDebugLoc();
901 SDValue Offset;
902 SDValue Chain = DAG.getEntryNode();
903 MVT PtrVT = getPointerTy();
904 // Get the Thread Pointer
905 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
906
907 if (GV->isDeclaration()){
908 // initial exec model
909 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
910 ARMConstantPoolValue *CPV =
911 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
912 PCAdj, "gottpoff", true);
913 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
914 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
915 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
916 Chain = Offset.getValue(1);
917
918 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
919 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
920
921 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
922 } else {
923 // local exec model
924 ARMConstantPoolValue *CPV =
925 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
926 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
927 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
928 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
929 }
930
931 // The address of the thread local variable is the add of the thread
932 // pointer with the offset of the variable.
933 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
934 }
935
936 SDValue
937 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
938 // TODO: implement the "local dynamic" model
939 assert(Subtarget->isTargetELF() &&
940 "TLS not implemented for non-ELF targets");
941 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
942 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
943 // otherwise use the "Local Exec" TLS Model
944 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
945 return LowerToTLSGeneralDynamicModel(GA, DAG);
946 else
947 return LowerToTLSExecModels(GA, DAG);
948 }
949
950 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
951 SelectionDAG &DAG) {
952 MVT PtrVT = getPointerTy();
953 DebugLoc dl = Op.getDebugLoc();
954 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
955 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
956 if (RelocM == Reloc::PIC_) {
957 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
958 ARMConstantPoolValue *CPV =
959 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
960 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
961 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
962 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
963 CPAddr, NULL, 0);
964 SDValue Chain = Result.getValue(1);
965 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
966 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
967 if (!UseGOTOFF)
968 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
969 return Result;
970 } else {
971 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
972 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
973 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
974 }
975 }
976
977 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
978 /// even in non-static mode.
979 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
980 // If symbol visibility is hidden, the extra load is not needed if
981 // the symbol is definitely defined in the current translation unit.
982 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
983 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
984 return false;
985 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
986 }
987
988 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
989 SelectionDAG &DAG) {
990 MVT PtrVT = getPointerTy();
991 DebugLoc dl = Op.getDebugLoc();
992 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
993 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
994 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
995 SDValue CPAddr;
996 if (RelocM == Reloc::Static)
997 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
998 else {
999 unsigned PCAdj = (RelocM != Reloc::PIC_)
1000 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1001 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1002 : ARMCP::CPValue;
1003 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1004 Kind, PCAdj);
1005 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1006 }
1007 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1008
1009 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1010 SDValue Chain = Result.getValue(1);
1011
1012 if (RelocM == Reloc::PIC_) {
1013 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1014 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1015 }
1016 if (IsIndirect)
1017 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1018
1019 return Result;
1020 }
1021
1022 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1023 SelectionDAG &DAG){
1024 assert(Subtarget->isTargetELF() &&
1025 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1026 MVT PtrVT = getPointerTy();
1027 DebugLoc dl = Op.getDebugLoc();
1028 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1029 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1030 ARMPCLabelIndex,
1031 ARMCP::CPValue, PCAdj);
1032 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1033 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1034 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1035 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1036 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1037 }
1038
1039 SDValue
1040 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1041 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1042 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1043 DebugLoc dl = Op.getDebugLoc();
1044 switch (IntNo) {
1045 default: return SDValue(); // Don't custom lower most intrinsics.
1046 case Intrinsic::arm_thread_pointer:
1047 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1048 case Intrinsic::eh_sjlj_setjmp:
1049 SDValue Res = DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32,
1050 Op.getOperand(1));
1051 return Res;
1052 }
1053 }
1054
1055 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1056 unsigned VarArgsFrameIndex) {
1057 // vastart just stores the address of the VarArgsFrameIndex slot into the
1058 // memory location argument.
1059 DebugLoc dl = Op.getDebugLoc();
1060 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1061 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1062 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1063 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1064 }
1065
1066 SDValue
1067 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1068 MachineFunction &MF = DAG.getMachineFunction();
1069 MachineFrameInfo *MFI = MF.getFrameInfo();
1070
1071 SDValue Root = Op.getOperand(0);
1072 DebugLoc dl = Op.getDebugLoc();
1073 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1074 unsigned CC = MF.getFunction()->getCallingConv();
1075 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1076
1077 // Assign locations to all of the incoming arguments.
1078 SmallVector<CCValAssign, 16> ArgLocs;
1079 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1080 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_ARM);
1081
1082 SmallVector<SDValue, 16> ArgValues;
1083
1084 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1085 CCValAssign &VA = ArgLocs[i];
1086
1087 // Arguments stored in registers.
1088 if (VA.isRegLoc()) {
1089 MVT RegVT = VA.getLocVT();
1090 TargetRegisterClass *RC;
1091 if (AFI->isThumbFunction())
1092 RC = ARM::tGPRRegisterClass;
1093 else
1094 RC = ARM::GPRRegisterClass;
1095
1096 if (RegVT == MVT::f64) {
1097 // f64 is passed in pairs of GPRs and must be combined.
1098 RegVT = MVT::i32;
1099 } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32)))
1100 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
1101
1102 // Transform the arguments stored in physical registers into virtual ones.
1103 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1104 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
1105
1106 // f64 is passed in i32 pairs and must be combined.
1107 if (VA.needsCustom()) {
1108 SDValue ArgValue2;
1109
1110 VA = ArgLocs[++i]; // skip ahead to next loc
1111 if (VA.isMemLoc()) {
1112 // must be APCS to split like this
1113 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1114 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1115
1116 // Create load node to retrieve arguments from the stack.
1117 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1118 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1119 } else {
1120 Reg = MF.addLiveIn(VA.getLocReg(), RC);
1121 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1122 }
1123
1124 ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64,
1125 ArgValue, ArgValue2);
1126 }
1127
1128 // If this is an 8 or 16-bit value, it is really passed promoted
1129 // to 32 bits. Insert an assert[sz]ext to capture this, then
1130 // truncate to the right size.
1131 switch (VA.getLocInfo()) {
1132 default: assert(0 && "Unknown loc info!");
1133 case CCValAssign::Full: break;
1134 case CCValAssign::BCvt:
1135 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1136 break;
1137 case CCValAssign::SExt:
1138 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1139 DAG.getValueType(VA.getValVT()));
1140 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1141 break;
1142 case CCValAssign::ZExt:
1143 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1144 DAG.getValueType(VA.getValVT()));
1145 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1146 break;
1147 }
1148
1149 ArgValues.push_back(ArgValue);
1150
1151 } else { // VA.isRegLoc()
1152
1153 // sanity check
1154 assert(VA.isMemLoc());
1155 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1156
1157 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1158 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1159
1160 // Create load nodes to retrieve arguments from the stack.
1161 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1162 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
1163 }
1164 }
1165
1166 // varargs
1167 if (isVarArg) {
1168 static const unsigned GPRArgRegs[] = {
1169 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1170 };
1171
1172 unsigned NumGPRs = CCInfo.getFirstUnallocated
1173 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1174
1175 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1176 unsigned VARegSize = (4 - NumGPRs) * 4;
1177 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1178 unsigned ArgOffset = 0;
1179 if (VARegSaveSize) {
1180 // If this function is vararg, store any remaining integer argument regs
1181 // to their spots on the stack so that they may be loaded by deferencing
1182 // the result of va_next.
1183 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1184 ArgOffset = CCInfo.getNextStackOffset();
1185 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1186 VARegSaveSize - VARegSize);
1187 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1188
1189 SmallVector<SDValue, 4> MemOps;
1190 for (; NumGPRs < 4; ++NumGPRs) {
1191 TargetRegisterClass *RC;
1192 if (AFI->isThumbFunction())
1193 RC = ARM::tGPRRegisterClass;
1194 else
1195 RC = ARM::GPRRegisterClass;
1196
1197 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1198 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1199 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1200 MemOps.push_back(Store);
1201 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1202 DAG.getConstant(4, getPointerTy()));
1203 }
1204 if (!MemOps.empty())
1205 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1206 &MemOps[0], MemOps.size());
1207 } else
1208 // This will point to the next argument passed via stack.
1209 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1210 }
1211
1212 ArgValues.push_back(Root);
1213
1214 // Return the new list of results.
1215 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1216 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1217 }
1218
1219 /// isFloatingPointZero - Return true if this is +0.0.
1220 static bool isFloatingPointZero(SDValue Op) {
1221 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1222 return CFP->getValueAPF().isPosZero();
1223 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1224 // Maybe this has already been legalized into the constant pool?
1225 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1226 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1227 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1228 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1229 return CFP->getValueAPF().isPosZero();
1230 }
1231 }
1232 return false;
1233 }
1234
1235 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1236 return ( isThumb && (C & ~255U) == 0) ||
1237 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1238 }
1239
1240 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1241 /// the given operands.
1242 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1243 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb,
1244 DebugLoc dl) {
1245 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1246 unsigned C = RHSC->getZExtValue();
1247 if (!isLegalCmpImmediate(C, isThumb)) {
1248 // Constant does not fit, try adjusting it by one?
1249 switch (CC) {
1250 default: break;
1251 case ISD::SETLT:
1252 case ISD::SETGE:
1253 if (isLegalCmpImmediate(C-1, isThumb)) {
1254 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1255 RHS = DAG.getConstant(C-1, MVT::i32);
1256 }
1257 break;
1258 case ISD::SETULT:
1259 case ISD::SETUGE:
1260 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1261 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1262 RHS = DAG.getConstant(C-1, MVT::i32);
1263 }
1264 break;
1265 case ISD::SETLE:
1266 case ISD::SETGT:
1267 if (isLegalCmpImmediate(C+1, isThumb)) {
1268 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1269 RHS = DAG.getConstant(C+1, MVT::i32);
1270 }
1271 break;
1272 case ISD::SETULE:
1273 case ISD::SETUGT:
1274 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1275 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1276 RHS = DAG.getConstant(C+1, MVT::i32);
1277 }
1278 break;
1279 }
1280 }
1281 }
1282
1283 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1284 ARMISD::NodeType CompareType;
1285 switch (CondCode) {
1286 default:
1287 CompareType = ARMISD::CMP;
1288 break;
1289 case ARMCC::EQ:
1290 case ARMCC::NE:
1291 case ARMCC::MI:
1292 case ARMCC::PL:
1293 // Uses only N and Z Flags
1294 CompareType = ARMISD::CMPNZ;
1295 break;
1296 }
1297 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1298 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1299 }
1300
1301 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1302 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1303 DebugLoc dl) {
1304 SDValue Cmp;
1305 if (!isFloatingPointZero(RHS))
1306 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1307 else
1308 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1309 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1310 }
1311
1312 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1313 const ARMSubtarget *ST) {
1314 MVT VT = Op.getValueType();
1315 SDValue LHS = Op.getOperand(0);
1316 SDValue RHS = Op.getOperand(1);
1317 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1318 SDValue TrueVal = Op.getOperand(2);
1319 SDValue FalseVal = Op.getOperand(3);
1320 DebugLoc dl = Op.getDebugLoc();
1321
1322 if (LHS.getValueType() == MVT::i32) {
1323 SDValue ARMCC;
1324 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1325 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1326 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1327 }
1328
1329 ARMCC::CondCodes CondCode, CondCode2;
1330 if (FPCCToARMCC(CC, CondCode, CondCode2))
1331 std::swap(TrueVal, FalseVal);
1332
1333 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1334 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1335 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1336 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1337 ARMCC, CCR, Cmp);
1338 if (CondCode2 != ARMCC::AL) {
1339 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1340 // FIXME: Needs another CMP because flag can have but one use.
1341 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1342 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1343 Result, TrueVal, ARMCC2, CCR, Cmp2);
1344 }
1345 return Result;
1346 }
1347
1348 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1349 const ARMSubtarget *ST) {
1350 SDValue Chain = Op.getOperand(0);
1351 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1352 SDValue LHS = Op.getOperand(2);
1353 SDValue RHS = Op.getOperand(3);
1354 SDValue Dest = Op.getOperand(4);
1355 DebugLoc dl = Op.getDebugLoc();
1356
1357 if (LHS.getValueType() == MVT::i32) {
1358 SDValue ARMCC;
1359 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1360 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl);
1361 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1362 Chain, Dest, ARMCC, CCR,Cmp);
1363 }
1364
1365 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1366 ARMCC::CondCodes CondCode, CondCode2;
1367 if (FPCCToARMCC(CC, CondCode, CondCode2))
1368 // Swap the LHS/RHS of the comparison if needed.
1369 std::swap(LHS, RHS);
1370
1371 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1372 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1373 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1374 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1375 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1376 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1377 if (CondCode2 != ARMCC::AL) {
1378 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1379 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1380 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1381 }
1382 return Res;
1383 }
1384
1385 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1386 SDValue Chain = Op.getOperand(0);
1387 SDValue Table = Op.getOperand(1);
1388 SDValue Index = Op.getOperand(2);
1389 DebugLoc dl = Op.getDebugLoc();
1390
1391 MVT PTy = getPointerTy();
1392 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1393 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1394 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1395 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1396 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1397 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1398 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1399 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1400 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl,
1401 Chain, Addr, NULL, 0);
1402 Chain = Addr.getValue(1);
1403 if (isPIC)
1404 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1405 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1406 }
1407
1408 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1409 DebugLoc dl = Op.getDebugLoc();
1410 unsigned Opc =
1411 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1412 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1413 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1414 }
1415
1416 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1417 MVT VT = Op.getValueType();
1418 DebugLoc dl = Op.getDebugLoc();
1419 unsigned Opc =
1420 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1421
1422 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1423 return DAG.getNode(Opc, dl, VT, Op);
1424 }
1425
1426 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1427 // Implement fcopysign with a fabs and a conditional fneg.
1428 SDValue Tmp0 = Op.getOperand(0);
1429 SDValue Tmp1 = Op.getOperand(1);
1430 DebugLoc dl = Op.getDebugLoc();
1431 MVT VT = Op.getValueType();
1432 MVT SrcVT = Tmp1.getValueType();
1433 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1434 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1435 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1436 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1437 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1438 }
1439
1440 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1441 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1442 MFI->setFrameAddressIsTaken(true);
1443 MVT VT = Op.getValueType();
1444 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1445 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1446 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->useThumbBacktraces())
1447 ? ARM::R7 : ARM::R11;
1448 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1449 while (Depth--)
1450 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1451 return FrameAddr;
1452 }
1453
1454 SDValue
1455 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1456 SDValue Chain,
1457 SDValue Dst, SDValue Src,
1458 SDValue Size, unsigned Align,
1459 bool AlwaysInline,
1460 const Value *DstSV, uint64_t DstSVOff,
1461 const Value *SrcSV, uint64_t SrcSVOff){
1462 // Do repeated 4-byte loads and stores. To be improved.
1463 // This requires 4-byte alignment.
1464 if ((Align & 3) != 0)
1465 return SDValue();
1466 // This requires the copy size to be a constant, preferrably
1467 // within a subtarget-specific limit.
1468 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1469 if (!ConstantSize)
1470 return SDValue();
1471 uint64_t SizeVal = ConstantSize->getZExtValue();
1472 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1473 return SDValue();
1474
1475 unsigned BytesLeft = SizeVal & 3;
1476 unsigned NumMemOps = SizeVal >> 2;
1477 unsigned EmittedNumMemOps = 0;
1478 MVT VT = MVT::i32;
1479 unsigned VTSize = 4;
1480 unsigned i = 0;
1481 const unsigned MAX_LOADS_IN_LDM = 6;
1482 SDValue TFOps[MAX_LOADS_IN_LDM];
1483 SDValue Loads[MAX_LOADS_IN_LDM];
1484 uint64_t SrcOff = 0, DstOff = 0;
1485
1486 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1487 // same number of stores. The loads and stores will get combined into
1488 // ldm/stm later on.
1489 while (EmittedNumMemOps < NumMemOps) {
1490 for (i = 0;
1491 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1492 Loads[i] = DAG.getLoad(VT, dl, Chain,
1493 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1494 DAG.getConstant(SrcOff, MVT::i32)),
1495 SrcSV, SrcSVOff + SrcOff);
1496 TFOps[i] = Loads[i].getValue(1);
1497 SrcOff += VTSize;
1498 }
1499 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1500
1501 for (i = 0;
1502 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1503 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1504 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1505 DAG.getConstant(DstOff, MVT::i32)),
1506 DstSV, DstSVOff + DstOff);
1507 DstOff += VTSize;
1508 }
1509 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1510
1511 EmittedNumMemOps += i;
1512 }
1513
1514 if (BytesLeft == 0)
1515 return Chain;
1516
1517 // Issue loads / stores for the trailing (1 - 3) bytes.
1518 unsigned BytesLeftSave = BytesLeft;
1519 i = 0;
1520 while (BytesLeft) {
1521 if (BytesLeft >= 2) {
1522 VT = MVT::i16;
1523 VTSize = 2;
1524 } else {
1525 VT = MVT::i8;
1526 VTSize = 1;
1527 }
1528
1529 Loads[i] = DAG.getLoad(VT, dl, Chain,
1530 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1531 DAG.getConstant(SrcOff, MVT::i32)),
1532 SrcSV, SrcSVOff + SrcOff);
1533 TFOps[i] = Loads[i].getValue(1);
1534 ++i;
1535 SrcOff += VTSize;
1536 BytesLeft -= VTSize;
1537 }
1538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1539
1540 i = 0;
1541 BytesLeft = BytesLeftSave;
1542 while (BytesLeft) {
1543 if (BytesLeft >= 2) {
1544 VT = MVT::i16;
1545 VTSize = 2;
1546 } else {
1547 VT = MVT::i8;
1548 VTSize = 1;
1549 }
1550
1551 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1552 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1553 DAG.getConstant(DstOff, MVT::i32)),
1554 DstSV, DstSVOff + DstOff);
1555 ++i;
1556 DstOff += VTSize;
1557 BytesLeft -= VTSize;
1558 }
1559 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1560 }
1561
1562 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1563 SDValue Op = N->getOperand(0);
1564 DebugLoc dl = N->getDebugLoc();
1565 if (N->getValueType(0) == MVT::f64) {
1566 // Turn i64->f64 into FMDRR.
1567 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1568 DAG.getConstant(0, MVT::i32));
1569 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
1570 DAG.getConstant(1, MVT::i32));
1571 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
1572 }
1573
1574 // Turn f64->i64 into FMRRD.
1575 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
1576 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
1577
1578 // Merge the pieces into a single i64 value.
1579 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
1580 }
1581
1582 static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1583 assert(N->getValueType(0) == MVT::i64 &&
1584 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1585 "Unknown shift to lower!");
1586
1587 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1588 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1589 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
1590 return SDValue();
1591
1592 // If we are in thumb mode, we don't have RRX.
1593 if (ST->isThumb()) return SDValue();
1594
1595 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1596 DebugLoc dl = N->getDebugLoc();
1597 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1598 DAG.getConstant(0, MVT::i32));
1599 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
1600 DAG.getConstant(1, MVT::i32));
1601
1602 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1603 // captures the result into a carry flag.
1604 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1605 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1606
1607 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1608 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
1609
1610 // Merge the pieces into a single i64 value.
1611 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1612 }
1613
1614 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
1615 switch (Op.getOpcode()) {
1616 default: assert(0 && "Don't know how to custom lower this!"); abort();
1617 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1618 case ISD::GlobalAddress:
1619 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1620 LowerGlobalAddressELF(Op, DAG);
1621 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1622 case ISD::CALL: return LowerCALL(Op, DAG);
1623 case ISD::RET: return LowerRET(Op, DAG);
1624 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1625 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1626 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1627 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1628 case ISD::SINT_TO_FP:
1629 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1630 case ISD::FP_TO_SINT:
1631 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1632 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1633 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1634 case ISD::RETURNADDR: break;
1635 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1636 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1637 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1638 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
1639 case ISD::SRL:
1640 case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget);
1641 }
1642 return SDValue();
1643 }
1644
1645 /// ReplaceNodeResults - Replace the results of node with an illegal result
1646 /// type with new values built out of custom code.
1647 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
1648 SmallVectorImpl<SDValue>&Results,
1649 SelectionDAG &DAG) {
1650 switch (N->getOpcode()) {
1651 default:
1652 assert(0 && "Don't know how to custom expand this!");
1653 return;
1654 case ISD::BIT_CONVERT:
1655 Results.push_back(ExpandBIT_CONVERT(N, DAG));
1656 return;
1657 case ISD::SRL:
1658 case ISD::SRA: {
1659 SDValue Res = ExpandSRx(N, DAG, Subtarget);
1660 if (Res.getNode())
1661 Results.push_back(Res);
1662 return;
1663 }
1664 }
1665 }
1666
1667 //===----------------------------------------------------------------------===//
1668 // ARM Scheduler Hooks
1669 //===----------------------------------------------------------------------===//
1670
1671 MachineBasicBlock *
1672 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1673 MachineBasicBlock *BB) const {
1674 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1675 DebugLoc dl = MI->getDebugLoc();
1676 switch (MI->getOpcode()) {
1677 default: assert(false && "Unexpected instr type to insert");
1678 case ARM::tMOVCCr: {
1679 // To "insert" a SELECT_CC instruction, we actually have to insert the
1680 // diamond control-flow pattern. The incoming instruction knows the
1681 // destination vreg to set, the condition code register to branch on, the
1682 // true/false values to select between, and a branch opcode to use.
1683 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1684 MachineFunction::iterator It = BB;
1685 ++It;
1686
1687 // thisMBB:
1688 // ...
1689 // TrueVal = ...
1690 // cmpTY ccX, r1, r2
1691 // bCC copy1MBB
1692 // fallthrough --> copy0MBB
1693 MachineBasicBlock *thisMBB = BB;
1694 MachineFunction *F = BB->getParent();
1695 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1696 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1697 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1698 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1699 F->insert(It, copy0MBB);
1700 F->insert(It, sinkMBB);
1701 // Update machine-CFG edges by first adding all successors of the current
1702 // block to the new block which will contain the Phi node for the select.
1703 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1704 e = BB->succ_end(); i != e; ++i)
1705 sinkMBB->addSuccessor(*i);
1706 // Next, remove all successors of the current block, and add the true
1707 // and fallthrough blocks as its successors.
1708 while(!BB->succ_empty())
1709 BB->removeSuccessor(BB->succ_begin());
1710 BB->addSuccessor(copy0MBB);
1711 BB->addSuccessor(sinkMBB);
1712
1713 // copy0MBB:
1714 // %FalseValue = ...
1715 // # fallthrough to sinkMBB
1716 BB = copy0MBB;
1717
1718 // Update machine-CFG edges
1719 BB->addSuccessor(sinkMBB);
1720
1721 // sinkMBB:
1722 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1723 // ...
1724 BB = sinkMBB;
1725 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1726 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1727 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1728
1729 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1730 return BB;
1731 }
1732 }
1733 }
1734
1735 //===----------------------------------------------------------------------===//
1736 // ARM Optimization Hooks
1737 //===----------------------------------------------------------------------===//
1738
1739 static
1740 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
1741 TargetLowering::DAGCombinerInfo &DCI) {
1742 SelectionDAG &DAG = DCI.DAG;
1743 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1744 MVT VT = N->getValueType(0);
1745 unsigned Opc = N->getOpcode();
1746 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
1747 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
1748 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
1749 ISD::CondCode CC = ISD::SETCC_INVALID;
1750
1751 if (isSlctCC) {
1752 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
1753 } else {
1754 SDValue CCOp = Slct.getOperand(0);
1755 if (CCOp.getOpcode() == ISD::SETCC)
1756 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
1757 }
1758
1759 bool DoXform = false;
1760 bool InvCC = false;
1761 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
1762 "Bad input!");
1763
1764 if (LHS.getOpcode() == ISD::Constant &&
1765 cast<ConstantSDNode>(LHS)->isNullValue()) {
1766 DoXform = true;
1767 } else if (CC != ISD::SETCC_INVALID &&
1768 RHS.getOpcode() == ISD::Constant &&
1769 cast<ConstantSDNode>(RHS)->isNullValue()) {
1770 std::swap(LHS, RHS);
1771 SDValue Op0 = Slct.getOperand(0);
1772 MVT OpVT = isSlctCC ? Op0.getValueType() :
1773 Op0.getOperand(0).getValueType();
1774 bool isInt = OpVT.isInteger();
1775 CC = ISD::getSetCCInverse(CC, isInt);
1776
1777 if (!TLI.isCondCodeLegal(CC, OpVT))
1778 return SDValue(); // Inverse operator isn't legal.
1779
1780 DoXform = true;
1781 InvCC = true;
1782 }
1783
1784 if (DoXform) {
1785 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
1786 if (isSlctCC)
1787 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
1788 Slct.getOperand(0), Slct.getOperand(1), CC);
1789 SDValue CCOp = Slct.getOperand(0);
1790 if (InvCC)
1791 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
1792 CCOp.getOperand(0), CCOp.getOperand(1), CC);
1793 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
1794 CCOp, OtherOp, Result);
1795 }
1796 return SDValue();
1797 }
1798
1799 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
1800 static SDValue PerformADDCombine(SDNode *N,
1801 TargetLowering::DAGCombinerInfo &DCI) {
1802 // added by evan in r37685 with no testcase.
1803 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1804
1805 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1806 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1807 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
1808 if (Result.getNode()) return Result;
1809 }
1810 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1811 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1812 if (Result.getNode()) return Result;
1813 }
1814
1815 return SDValue();
1816 }
1817
1818 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
1819 static SDValue PerformSUBCombine(SDNode *N,
1820 TargetLowering::DAGCombinerInfo &DCI) {
1821 // added by evan in r37685 with no testcase.
1822 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1823
1824 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1825 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1826 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
1827 if (Result.getNode()) return Result;
1828 }
1829
1830 return SDValue();
1831 }
1832
1833
1834 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1835 static SDValue PerformFMRRDCombine(SDNode *N,
1836 TargetLowering::DAGCombinerInfo &DCI) {
1837 // fmrrd(fmdrr x, y) -> x,y
1838 SDValue InDouble = N->getOperand(0);
1839 if (InDouble.getOpcode() == ARMISD::FMDRR)
1840 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1841 return SDValue();
1842 }
1843
1844 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
1845 DAGCombinerInfo &DCI) const {
1846 switch (N->getOpcode()) {
1847 default: break;
1848 case ISD::ADD: return PerformADDCombine(N, DCI);
1849 case ISD::SUB: return PerformSUBCombine(N, DCI);
1850 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1851 }
1852
1853 return SDValue();
1854 }
1855
1856 /// isLegalAddressImmediate - Return true if the integer value can be used
1857 /// as the offset of the target addressing mode for load / store of the
1858 /// given type.
1859 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1860 const ARMSubtarget *Subtarget) {
1861 if (V == 0)
1862 return true;
1863
1864 if (!VT.isSimple())
1865 return false;
1866
1867 if (Subtarget->isThumb()) {
1868 if (V < 0)
1869 return false;
1870
1871 unsigned Scale = 1;
1872 switch (VT.getSimpleVT()) {
1873 default: return false;
1874 case MVT::i1:
1875 case MVT::i8:
1876 // Scale == 1;
1877 break;
1878 case MVT::i16:
1879 // Scale == 2;
1880 Scale = 2;
1881 break;
1882 case MVT::i32:
1883 // Scale == 4;
1884 Scale = 4;
1885 break;
1886 }
1887
1888 if ((V & (Scale - 1)) != 0)
1889 return false;
1890 V /= Scale;
1891 return V == (V & ((1LL << 5) - 1));
1892 }
1893
1894 if (V < 0)
1895 V = - V;
1896 switch (VT.getSimpleVT()) {
1897 default: return false;
1898 case MVT::i1:
1899 case MVT::i8:
1900 case MVT::i32:
1901 // +- imm12
1902 return V == (V & ((1LL << 12) - 1));
1903 case MVT::i16:
1904 // +- imm8
1905 return V == (V & ((1LL << 8) - 1));
1906 case MVT::f32:
1907 case MVT::f64:
1908 if (!Subtarget->hasVFP2())
1909 return false;
1910 if ((V & 3) != 0)
1911 return false;
1912 V >>= 2;
1913 return V == (V & ((1LL << 8) - 1));
1914 }
1915 }
1916
1917 /// isLegalAddressingMode - Return true if the addressing mode represented
1918 /// by AM is legal for this target, for a load/store of the specified type.
1919 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1920 const Type *Ty) const {
1921 MVT VT = getValueType(Ty, true);
1922 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
1923 return false;
1924
1925 // Can never fold addr of global into load/store.
1926 if (AM.BaseGV)
1927 return false;
1928
1929 switch (AM.Scale) {
1930 case 0: // no scale reg, must be "r+i" or "r", or "i".
1931 break;
1932 case 1:
1933 if (Subtarget->isThumb())
1934 return false;
1935 // FALL THROUGH.
1936 default:
1937 // ARM doesn't support any R+R*scale+imm addr modes.
1938 if (AM.BaseOffs)
1939 return false;
1940
1941 if (!VT.isSimple())
1942 return false;
1943
1944 int Scale = AM.Scale;
1945 switch (VT.getSimpleVT()) {
1946 default: return false;
1947 case MVT::i1:
1948 case MVT::i8:
1949 case MVT::i32:
1950 case MVT::i64:
1951 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1952 // ldrd / strd are used, then its address mode is same as i16.
1953 // r + r
1954 if (Scale < 0) Scale = -Scale;
1955 if (Scale == 1)
1956 return true;
1957 // r + r << imm
1958 return isPowerOf2_32(Scale & ~1);
1959 case MVT::i16:
1960 // r + r
1961 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1962 return true;
1963 return false;
1964
1965 case MVT::isVoid:
1966 // Note, we allow "void" uses (basically, uses that aren't loads or
1967 // stores), because arm allows folding a scale into many arithmetic
1968 // operations. This should be made more precise and revisited later.
1969
1970 // Allow r << imm, but the imm has to be a multiple of two.
1971 if (AM.Scale & 1) return false;
1972 return isPowerOf2_32(AM.Scale);
1973 }
1974 break;
1975 }
1976 return true;
1977 }
1978
1979 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1980 bool isSEXTLoad, SDValue &Base,
1981 SDValue &Offset, bool &isInc,
1982 SelectionDAG &DAG) {
1983 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1984 return false;
1985
1986 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1987 // AddressingMode 3
1988 Base = Ptr->getOperand(0);
1989 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1990 int RHSC = (int)RHS->getZExtValue();
1991 if (RHSC < 0 && RHSC > -256) {
1992 isInc = false;
1993 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1994 return true;
1995 }
1996 }
1997 isInc = (Ptr->getOpcode() == ISD::ADD);
1998 Offset = Ptr->getOperand(1);
1999 return true;
2000 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
2001 // AddressingMode 2
2002 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
2003 int RHSC = (int)RHS->getZExtValue();
2004 if (RHSC < 0 && RHSC > -0x1000) {
2005 isInc = false;
2006 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
2007 Base = Ptr->getOperand(0);
2008 return true;
2009 }
2010 }
2011
2012 if (Ptr->getOpcode() == ISD::ADD) {
2013 isInc = true;
2014 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
2015 if (ShOpcVal != ARM_AM::no_shift) {
2016 Base = Ptr->getOperand(1);
2017 Offset = Ptr->getOperand(0);
2018 } else {
2019 Base = Ptr->getOperand(0);
2020 Offset = Ptr->getOperand(1);
2021 }
2022 return true;
2023 }
2024
2025 isInc = (Ptr->getOpcode() == ISD::ADD);
2026 Base = Ptr->getOperand(0);
2027 Offset = Ptr->getOperand(1);
2028 return true;
2029 }
2030
2031 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
2032 return false;
2033 }
2034
2035 /// getPreIndexedAddressParts - returns true by value, base pointer and
2036 /// offset pointer and addressing mode by reference if the node's address
2037 /// can be legally represented as pre-indexed load / store address.
2038 bool
2039 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2040 SDValue &Offset,
2041 ISD::MemIndexedMode &AM,
2042 SelectionDAG &DAG) const {
2043 if (Subtarget->isThumb())
2044 return false;
2045
2046 MVT VT;
2047 SDValue Ptr;
2048 bool isSEXTLoad = false;
2049 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2050 Ptr = LD->getBasePtr();
2051 VT = LD->getMemoryVT();
2052 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2053 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2054 Ptr = ST->getBasePtr();
2055 VT = ST->getMemoryVT();
2056 } else
2057 return false;
2058
2059 bool isInc;
2060 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
2061 isInc, DAG);
2062 if (isLegal) {
2063 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
2064 return true;
2065 }
2066 return false;
2067 }
2068
2069 /// getPostIndexedAddressParts - returns true by value, base pointer and
2070 /// offset pointer and addressing mode by reference if this node can be
2071 /// combined with a load / store to form a post-indexed load / store.
2072 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
2073 SDValue &Base,
2074 SDValue &Offset,
2075 ISD::MemIndexedMode &AM,
2076 SelectionDAG &DAG) const {
2077 if (Subtarget->isThumb())
2078 return false;
2079
2080 MVT VT;
2081 SDValue Ptr;
2082 bool isSEXTLoad = false;
2083 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2084 VT = LD->getMemoryVT();
2085 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
2086 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2087 VT = ST->getMemoryVT();
2088 } else
2089 return false;
2090
2091 bool isInc;
2092 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
2093 isInc, DAG);
2094 if (isLegal) {
2095 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
2096 return true;
2097 }
2098 return false;
2099 }
2100
2101 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
2102 const APInt &Mask,
2103 APInt &KnownZero,
2104 APInt &KnownOne,
2105 const SelectionDAG &DAG,
2106 unsigned Depth) const {
2107 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
2108 switch (Op.getOpcode()) {
2109 default: break;
2110 case ARMISD::CMOV: {
2111 // Bits are known zero/one if known on the LHS and RHS.
2112 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
2113 if (KnownZero == 0 && KnownOne == 0) return;
2114
2115 APInt KnownZeroRHS, KnownOneRHS;
2116 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
2117 KnownZeroRHS, KnownOneRHS, Depth+1);
2118 KnownZero &= KnownZeroRHS;
2119 KnownOne &= KnownOneRHS;
2120 return;
2121 }
2122 }
2123 }
2124
2125 //===----------------------------------------------------------------------===//
2126 // ARM Inline Assembly Support
2127 //===----------------------------------------------------------------------===//
2128
2129 /// getConstraintType - Given a constraint letter, return the type of
2130 /// constraint it is for this target.
2131 ARMTargetLowering::ConstraintType
2132 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
2133 if (Constraint.size() == 1) {
2134 switch (Constraint[0]) {
2135 default: break;
2136 case 'l': return C_RegisterClass;
2137 case 'w': return C_RegisterClass;
2138 }
2139 }
2140 return TargetLowering::getConstraintType(Constraint);
2141 }
2142
2143 std::pair<unsigned, const TargetRegisterClass*>
2144 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
2145 MVT VT) const {
2146 if (Constraint.size() == 1) {
2147 // GCC RS6000 Constraint Letters
2148 switch (Constraint[0]) {
2149 case 'l':
2150 if (Subtarget->isThumb())
2151 return std::make_pair(0U, ARM::tGPRRegisterClass);
2152 else
2153 return std::make_pair(0U, ARM::GPRRegisterClass);
2154 case 'r':
2155 return std::make_pair(0U, ARM::GPRRegisterClass);
2156 case 'w':
2157 if (VT == MVT::f32)
2158 return std::make_pair(0U, ARM::SPRRegisterClass);
2159 if (VT == MVT::f64)
2160 return std::make_pair(0U, ARM::DPRRegisterClass);
2161 break;
2162 }
2163 }
2164 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
2165 }
2166
2167 std::vector<unsigned> ARMTargetLowering::
2168 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2169 MVT VT) const {
2170 if (Constraint.size() != 1)
2171 return std::vector<unsigned>();
2172
2173 switch (Constraint[0]) { // GCC ARM Constraint Letters
2174 default: break;
2175 case 'l':
2176 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2177 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2178 0);
2179 case 'r':
2180 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
2181 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
2182 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
2183 ARM::R12, ARM::LR, 0);
2184 case 'w':
2185 if (VT == MVT::f32)
2186 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
2187 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
2188 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
2189 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
2190 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
2191 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
2192 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
2193 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
2194 if (VT == MVT::f64)
2195 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
2196 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
2197 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
2198 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
2199 break;
2200 }
2201
2202 return std::vector<unsigned>();
2203 }
2204
2205 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2206 /// vector. If it is invalid, don't add anything to Ops.
2207 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2208 char Constraint,
2209 bool hasMemory,
2210 std::vector<SDValue>&Ops,
2211 SelectionDAG &DAG) const {
2212 SDValue Result(0, 0);
2213
2214 switch (Constraint) {
2215 default: break;
2216 case 'I': case 'J': case 'K': case 'L':
2217 case 'M': case 'N': case 'O':
2218 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2219 if (!C)
2220 return;
2221
2222 int64_t CVal64 = C->getSExtValue();
2223 int CVal = (int) CVal64;
2224 // None of these constraints allow values larger than 32 bits. Check
2225 // that the value fits in an int.
2226 if (CVal != CVal64)
2227 return;
2228
2229 switch (Constraint) {
2230 case 'I':
2231 if (Subtarget->isThumb()) {
2232 // This must be a constant between 0 and 255, for ADD immediates.
2233 if (CVal >= 0 && CVal <= 255)
2234 break;
2235 } else {
2236 // A constant that can be used as an immediate value in a
2237 // data-processing instruction.
2238 if (ARM_AM::getSOImmVal(CVal) != -1)
2239 break;
2240 }
2241 return;
2242
2243 case 'J':
2244 if (Subtarget->isThumb()) {
2245 // This must be a constant between -255 and -1, for negated ADD
2246 // immediates. This can be used in GCC with an "n" modifier that
2247 // prints the negated value, for use with SUB instructions. It is
2248 // not useful otherwise but is implemented for compatibility.
2249 if (CVal >= -255 && CVal <= -1)
2250 break;
2251 } else {
2252 // This must be a constant between -4095 and 4095. It is not clear
2253 // what this constraint is intended for. Implemented for
2254 // compatibility with GCC.
2255 if (CVal >= -4095 && CVal <= 4095)
2256 break;
2257 }
2258 return;
2259
2260 case 'K':
2261 if (Subtarget->isThumb()) {
2262 // A 32-bit value where only one byte has a nonzero value. Exclude
2263 // zero to match GCC. This constraint is used by GCC internally for
2264 // constants that can be loaded with a move/shift combination.
2265 // It is not useful otherwise but is implemented for compatibility.
2266 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
2267 break;
2268 } else {
2269 // A constant whose bitwise inverse can be used as an immediate
2270 // value in a data-processing instruction. This can be used in GCC
2271 // with a "B" modifier that prints the inverted value, for use with
2272 // BIC and MVN instructions. It is not useful otherwise but is
2273 // implemented for compatibility.
2274 if (ARM_AM::getSOImmVal(~CVal) != -1)
2275 break;
2276 }
2277 return;
2278
2279 case 'L':
2280 if (Subtarget->isThumb()) {
2281 // This must be a constant between -7 and 7,
2282 // for 3-operand ADD/SUB immediate instructions.
2283 if (CVal >= -7 && CVal < 7)
2284 break;
2285 } else {
2286 // A constant whose negation can be used as an immediate value in a
2287 // data-processing instruction. This can be used in GCC with an "n"
2288 // modifier that prints the negated value, for use with SUB
2289 // instructions. It is not useful otherwise but is implemented for
2290 // compatibility.
2291 if (ARM_AM::getSOImmVal(-CVal) != -1)
2292 break;
2293 }
2294 return;
2295
2296 case 'M':
2297 if (Subtarget->isThumb()) {
2298 // This must be a multiple of 4 between 0 and 1020, for
2299 // ADD sp + immediate.
2300 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
2301 break;
2302 } else {
2303 // A power of two or a constant between 0 and 32. This is used in
2304 // GCC for the shift amount on shifted register operands, but it is
2305 // useful in general for any shift amounts.
2306 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
2307 break;
2308 }
2309 return;
2310
2311 case 'N':
2312 if (Subtarget->isThumb()) {
2313 // This must be a constant between 0 and 31, for shift amounts.
2314 if (CVal >= 0 && CVal <= 31)
2315 break;
2316 }
2317 return;
2318
2319 case 'O':
2320 if (Subtarget->isThumb()) {
2321 // This must be a multiple of 4 between -508 and 508, for
2322 // ADD/SUB sp = sp + immediate.
2323 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
2324 break;
2325 }
2326 return;
2327 }
2328 Result = DAG.getTargetConstant(CVal, Op.getValueType());
2329 break;
2330 }
2331
2332 if (Result.getNode()) {
2333 Ops.push_back(Result);
2334 return;
2335 }
2336 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
2337 Ops, DAG);
2338 }
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