lib/Target/Alpha/AlphaInstrInfo.cpp

   1 //===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Alpha implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Alpha.h"
  15 #include "AlphaInstrInfo.h"
  16 #include "AlphaGenInstrInfo.inc"
  17 #include "llvm/ADT/STLExtras.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 using namespace llvm;
  21
  22 AlphaInstrInfo::AlphaInstrInfo()
  23   : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
  24     RI(*this) { }
  25
  26
  27 bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
  28                                  unsigned& sourceReg, unsigned& destReg,
  29                                  unsigned& SrcSR, unsigned& DstSR) const {
  30   unsigned oc = MI.getOpcode();
  31   if (oc == Alpha::BISr   ||
  32       oc == Alpha::CPYSS  ||
  33       oc == Alpha::CPYST  ||
  34       oc == Alpha::CPYSSt ||
  35       oc == Alpha::CPYSTs) {
  36     // or r1, r2, r2
  37     // cpys(s|t) r1 r2 r2
  38     assert(MI.getNumOperands() >= 3 &&
  39            MI.getOperand(0).isReg() &&
  40            MI.getOperand(1).isReg() &&
  41            MI.getOperand(2).isReg() &&
  42            "invalid Alpha BIS instruction!");
  43     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
  44       sourceReg = MI.getOperand(1).getReg();
  45       destReg = MI.getOperand(0).getReg();
  46       SrcSR = DstSR = 0;
  47       return true;
  48     }
  49   }
  50   return false;
  51 }
  52
  53 unsigned
  54 AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
  55                                     int &FrameIndex) const {
  56   switch (MI->getOpcode()) {
  57   case Alpha::LDL:
  58   case Alpha::LDQ:
  59   case Alpha::LDBU:
  60   case Alpha::LDWU:
  61   case Alpha::LDS:
  62   case Alpha::LDT:
  63     if (MI->getOperand(1).isFI()) {
  64       FrameIndex = MI->getOperand(1).getIndex();
  65       return MI->getOperand(0).getReg();
  66     }
  67     break;
  68   }
  69   return 0;
  70 }
  71
  72 unsigned
  73 AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
  74                                    int &FrameIndex) const {
  75   switch (MI->getOpcode()) {
  76   case Alpha::STL:
  77   case Alpha::STQ:
  78   case Alpha::STB:
  79   case Alpha::STW:
  80   case Alpha::STS:
  81   case Alpha::STT:
  82     if (MI->getOperand(1).isFI()) {
  83       FrameIndex = MI->getOperand(1).getIndex();
  84       return MI->getOperand(0).getReg();
  85     }
  86     break;
  87   }
  88   return 0;
  89 }
  90
  91 static bool isAlphaIntCondCode(unsigned Opcode) {
  92   switch (Opcode) {
  93   case Alpha::BEQ:
  94   case Alpha::BNE:
  95   case Alpha::BGE:
  96   case Alpha::BGT:
  97   case Alpha::BLE:
  98   case Alpha::BLT:
  99   case Alpha::BLBC:
 100   case Alpha::BLBS:
 101     return true;
 102   default:
 103     return false;
 104   }
 105 }
 106
 107 unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
 108                                       MachineBasicBlock *TBB,
 109                                       MachineBasicBlock *FBB,
 110                             const SmallVectorImpl<MachineOperand> &Cond) const {
 111   // FIXME this should probably have a DebugLoc argument
 112   DebugLoc dl = DebugLoc::getUnknownLoc();
 113   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 114   assert((Cond.size() == 2 || Cond.size() == 0) &&
 115          "Alpha branch conditions have two components!");
 116
 117   // One-way branch.
 118   if (FBB == 0) {
 119     if (Cond.empty())   // Unconditional branch
 120       BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB);
 121     else                // Conditional branch
 122       if (isAlphaIntCondCode(Cond[0].getImm()))
 123         BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
 124           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 125       else
 126         BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
 127           .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 128     return 1;
 129   }
 130
 131   // Two-way Conditional Branch.
 132   if (isAlphaIntCondCode(Cond[0].getImm()))
 133     BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I))
 134       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 135   else
 136     BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F))
 137       .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
 138   BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB);
 139   return 2;
 140 }
 141
 142 bool AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
 143                                   MachineBasicBlock::iterator MI,
 144                                   unsigned DestReg, unsigned SrcReg,
 145                                   const TargetRegisterClass *DestRC,
 146                                   const TargetRegisterClass *SrcRC) const {
 147   //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
 148   if (DestRC != SrcRC) {
 149     // Not yet supported!
 150     return false;
 151   }
 152
 153   DebugLoc DL = DebugLoc::getUnknownLoc();
 154   if (MI != MBB.end()) DL = MI->getDebugLoc();
 155
 156   if (DestRC == Alpha::GPRCRegisterClass) {
 157     BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
 158       .addReg(SrcReg)
 159       .addReg(SrcReg);
 160   } else if (DestRC == Alpha::F4RCRegisterClass) {
 161     BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
 162       .addReg(SrcReg)
 163       .addReg(SrcReg);
 164   } else if (DestRC == Alpha::F8RCRegisterClass) {
 165     BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
 166       .addReg(SrcReg)
 167       .addReg(SrcReg);
 168   } else {
 169     // Attempt to copy register that is not GPR or FPR
 170     return false;
 171   }
 172
 173   return true;
 174 }
 175
 176 void
 177 AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
 178                                     MachineBasicBlock::iterator MI,
 179                                     unsigned SrcReg, bool isKill, int FrameIdx,
 180                                     const TargetRegisterClass *RC) const {
 181   //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
 182   //     << FrameIdx << "\n";
 183   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
 184
 185   DebugLoc DL = DebugLoc::getUnknownLoc();
 186   if (MI != MBB.end()) DL = MI->getDebugLoc();
 187
 188   if (RC == Alpha::F4RCRegisterClass)
 189     BuildMI(MBB, MI, DL, get(Alpha::STS))
 190       .addReg(SrcReg, getKillRegState(isKill))
 191       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 192   else if (RC == Alpha::F8RCRegisterClass)
 193     BuildMI(MBB, MI, DL, get(Alpha::STT))
 194       .addReg(SrcReg, getKillRegState(isKill))
 195       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 196   else if (RC == Alpha::GPRCRegisterClass)
 197     BuildMI(MBB, MI, DL, get(Alpha::STQ))
 198       .addReg(SrcReg, getKillRegState(isKill))
 199       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 200   else
 201     abort();
 202 }
 203
 204 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
 205                                        bool isKill,
 206                                        SmallVectorImpl<MachineOperand> &Addr,
 207                                        const TargetRegisterClass *RC,
 208                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
 209   unsigned Opc = 0;
 210   if (RC == Alpha::F4RCRegisterClass)
 211     Opc = Alpha::STS;
 212   else if (RC == Alpha::F8RCRegisterClass)
 213     Opc = Alpha::STT;
 214   else if (RC == Alpha::GPRCRegisterClass)
 215     Opc = Alpha::STQ;
 216   else
 217     abort();
 218   DebugLoc DL = DebugLoc::getUnknownLoc();
 219   MachineInstrBuilder MIB =
 220     BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
 221   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
 222     MIB.addOperand(Addr[i]);
 223   NewMIs.push_back(MIB);
 224 }
 225
 226 void
 227 AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
 228                                         MachineBasicBlock::iterator MI,
 229                                         unsigned DestReg, int FrameIdx,
 230                                         const TargetRegisterClass *RC) const {
 231   //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
 232   //     << FrameIdx << "\n";
 233   DebugLoc DL = DebugLoc::getUnknownLoc();
 234   if (MI != MBB.end()) DL = MI->getDebugLoc();
 235
 236   if (RC == Alpha::F4RCRegisterClass)
 237     BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
 238       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 239   else if (RC == Alpha::F8RCRegisterClass)
 240     BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
 241       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 242   else if (RC == Alpha::GPRCRegisterClass)
 243     BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
 244       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
 245   else
 246     abort();
 247 }
 248
 249 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 250                                         SmallVectorImpl<MachineOperand> &Addr,
 251                                         const TargetRegisterClass *RC,
 252                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
 253   unsigned Opc = 0;
 254   if (RC == Alpha::F4RCRegisterClass)
 255     Opc = Alpha::LDS;
 256   else if (RC == Alpha::F8RCRegisterClass)
 257     Opc = Alpha::LDT;
 258   else if (RC == Alpha::GPRCRegisterClass)
 259     Opc = Alpha::LDQ;
 260   else
 261     abort();
 262   DebugLoc DL = DebugLoc::getUnknownLoc();
 263   MachineInstrBuilder MIB =
 264     BuildMI(MF, DL, get(Opc), DestReg);
 265   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
 266     MIB.addOperand(Addr[i]);
 267   NewMIs.push_back(MIB);
 268 }
 269
 270 MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
 271                                                     MachineInstr *MI,
 272                                           const SmallVectorImpl<unsigned> &Ops,
 273                                                     int FrameIndex) const {
 274    if (Ops.size() != 1) return NULL;
 275
 276    // Make sure this is a reg-reg copy.
 277    unsigned Opc = MI->getOpcode();
 278
 279    MachineInstr *NewMI = NULL;
 280    switch(Opc) {
 281    default:
 282      break;
 283    case Alpha::BISr:
 284    case Alpha::CPYSS:
 285    case Alpha::CPYST:
 286      if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
 287        if (Ops[0] == 0) {  // move -> store
 288          unsigned InReg = MI->getOperand(1).getReg();
 289          bool isKill = MI->getOperand(1).isKill();
 290          Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
 291            ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
 292          NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
 293            .addReg(InReg, getKillRegState(isKill))
 294            .addFrameIndex(FrameIndex)
 295            .addReg(Alpha::F31);
 296        } else {           // load -> move
 297          unsigned OutReg = MI->getOperand(0).getReg();
 298          bool isDead = MI->getOperand(0).isDead();
 299          Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
 300            ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
 301          NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
 302            .addReg(OutReg, RegState::Define | getDeadRegState(isDead))
 303            .addFrameIndex(FrameIndex)
 304            .addReg(Alpha::F31);
 305        }
 306      }
 307      break;
 308    }
 309   return NewMI;
 310 }
 311
 312 static unsigned AlphaRevCondCode(unsigned Opcode) {
 313   switch (Opcode) {
 314   case Alpha::BEQ: return Alpha::BNE;
 315   case Alpha::BNE: return Alpha::BEQ;
 316   case Alpha::BGE: return Alpha::BLT;
 317   case Alpha::BGT: return Alpha::BLE;
 318   case Alpha::BLE: return Alpha::BGT;
 319   case Alpha::BLT: return Alpha::BGE;
 320   case Alpha::BLBC: return Alpha::BLBS;
 321   case Alpha::BLBS: return Alpha::BLBC;
 322   case Alpha::FBEQ: return Alpha::FBNE;
 323   case Alpha::FBNE: return Alpha::FBEQ;
 324   case Alpha::FBGE: return Alpha::FBLT;
 325   case Alpha::FBGT: return Alpha::FBLE;
 326   case Alpha::FBLE: return Alpha::FBGT;
 327   case Alpha::FBLT: return Alpha::FBGE;
 328   default:
 329     assert(0 && "Unknown opcode");
 330   }
 331   return 0; // Not reached
 332 }
 333
 334 // Branch analysis.
 335 bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
 336                                    MachineBasicBlock *&FBB,
 337                                    SmallVectorImpl<MachineOperand> &Cond,
 338                                    bool AllowModify) const {
 339   // If the block has no terminators, it just falls into the block after it.
 340   MachineBasicBlock::iterator I = MBB.end();
 341   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 342     return false;
 343
 344   // Get the last instruction in the block.
 345   MachineInstr *LastInst = I;
 346
 347   // If there is only one terminator instruction, process it.
 348   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 349     if (LastInst->getOpcode() == Alpha::BR) {
 350       TBB = LastInst->getOperand(0).getMBB();
 351       return false;
 352     } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
 353                LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
 354       // Block ends with fall-through condbranch.
 355       TBB = LastInst->getOperand(2).getMBB();
 356       Cond.push_back(LastInst->getOperand(0));
 357       Cond.push_back(LastInst->getOperand(1));
 358       return false;
 359     }
 360     // Otherwise, don't know what this is.
 361     return true;
 362   }
 363
 364   // Get the instruction before it if it's a terminator.
 365   MachineInstr *SecondLastInst = I;
 366
 367   // If there are three terminators, we don't know what sort of block this is.
 368   if (SecondLastInst && I != MBB.begin() &&
 369       isUnpredicatedTerminator(--I))
 370     return true;
 371
 372   // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
 373   if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
 374       SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) &&
 375       LastInst->getOpcode() == Alpha::BR) {
 376     TBB =  SecondLastInst->getOperand(2).getMBB();
 377     Cond.push_back(SecondLastInst->getOperand(0));
 378     Cond.push_back(SecondLastInst->getOperand(1));
 379     FBB = LastInst->getOperand(0).getMBB();
 380     return false;
 381   }
 382
 383   // If the block ends with two Alpha::BRs, handle it.  The second one is not
 384   // executed, so remove it.
 385   if (SecondLastInst->getOpcode() == Alpha::BR &&
 386       LastInst->getOpcode() == Alpha::BR) {
 387     TBB = SecondLastInst->getOperand(0).getMBB();
 388     I = LastInst;
 389     if (AllowModify)
 390       I->eraseFromParent();
 391     return false;
 392   }
 393
 394   // Otherwise, can't handle this.
 395   return true;
 396 }
 397
 398 unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 399   MachineBasicBlock::iterator I = MBB.end();
 400   if (I == MBB.begin()) return 0;
 401   --I;
 402   if (I->getOpcode() != Alpha::BR &&
 403       I->getOpcode() != Alpha::COND_BRANCH_I &&
 404       I->getOpcode() != Alpha::COND_BRANCH_F)
 405     return 0;
 406
 407   // Remove the branch.
 408   I->eraseFromParent();
 409
 410   I = MBB.end();
 411
 412   if (I == MBB.begin()) return 1;
 413   --I;
 414   if (I->getOpcode() != Alpha::COND_BRANCH_I &&
 415       I->getOpcode() != Alpha::COND_BRANCH_F)
 416     return 1;
 417
 418   // Remove the branch.
 419   I->eraseFromParent();
 420   return 2;
 421 }
 422
 423 void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
 424                                 MachineBasicBlock::iterator MI) const {
 425   DebugLoc DL = DebugLoc::getUnknownLoc();
 426   if (MI != MBB.end()) DL = MI->getDebugLoc();
 427   BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
 428     .addReg(Alpha::R31)
 429     .addReg(Alpha::R31);
 430 }
 431
 432 bool AlphaInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
 433   if (MBB.empty()) return false;
 434
 435   switch (MBB.back().getOpcode()) {
 436   case Alpha::RETDAG: // Return.
 437   case Alpha::RETDAGp:
 438   case Alpha::BR:     // Uncond branch.
 439   case Alpha::JMP:  // Indirect branch.
 440     return true;
 441   default: return false;
 442   }
 443 }
 444 bool AlphaInstrInfo::
 445 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
 446   assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
 447   Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
 448   return false;
 449 }
 450