lib/Target/Alpha/AlphaInstrInfo.h

   1 //===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Alpha implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef ALPHAINSTRUCTIONINFO_H
  15 #define ALPHAINSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "AlphaRegisterInfo.h"
  19
  20 namespace llvm {
  21
  22 class AlphaInstrInfo : public TargetInstrInfoImpl {
  23   const AlphaRegisterInfo RI;
  24 public:
  25   AlphaInstrInfo();
  26
  27   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  28   /// such, whenever a client has an instance of instruction info, it should
  29   /// always be able to get register info as well (through this method).
  30   ///
  31   virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
  32
  33   /// Return true if the instruction is a register to register move and return
  34   /// the source and dest operands and their sub-register indices by reference.
  35   virtual bool isMoveInstr(const MachineInstr &MI,
  36                            unsigned &SrcReg, unsigned &DstReg,
  37                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
  38
  39   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  40                                        int &FrameIndex) const;
  41   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  42                                       int &FrameIndex) const;
  43
  44   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  45                             MachineBasicBlock *FBB,
  46                             const SmallVectorImpl<MachineOperand> &Cond) const;
  47   virtual bool copyRegToReg(MachineBasicBlock &MBB,
  48                             MachineBasicBlock::iterator MI,
  49                             unsigned DestReg, unsigned SrcReg,
  50                             const TargetRegisterClass *DestRC,
  51                             const TargetRegisterClass *SrcRC) const;
  52   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  53                                    MachineBasicBlock::iterator MBBI,
  54                                    unsigned SrcReg, bool isKill, int FrameIndex,
  55                                    const TargetRegisterClass *RC) const;
  56
  57   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
  58                               SmallVectorImpl<MachineOperand> &Addr,
  59                               const TargetRegisterClass *RC,
  60                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
  61
  62   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  63                                     MachineBasicBlock::iterator MBBI,
  64                                     unsigned DestReg, int FrameIndex,
  65                                     const TargetRegisterClass *RC) const;
  66
  67   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
  68                                SmallVectorImpl<MachineOperand> &Addr,
  69                                const TargetRegisterClass *RC,
  70                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
  71
  72   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  73                                               MachineInstr* MI,
  74                                            const SmallVectorImpl<unsigned> &Ops,
  75                                               int FrameIndex) const;
  76
  77   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
  78                                               MachineInstr* MI,
  79                                            const SmallVectorImpl<unsigned> &Ops,
  80                                               MachineInstr* LoadMI) const {
  81     return 0;
  82   }
  83
  84   bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
  85                      MachineBasicBlock *&FBB,
  86                      SmallVectorImpl<MachineOperand> &Cond,
  87                      bool AllowModify) const;
  88   unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  89   void insertNoop(MachineBasicBlock &MBB,
  90                   MachineBasicBlock::iterator MI) const;
  91   bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
  92   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  93 };
  94
  95 }
  96
  97 #endif