lib/Target/CellSPU/SPUFrameInfo.h

   1 //===-- SPUFrameInfo.h - Top-level interface for Cell SPU Target -*- C++ -*-==//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains CellSPU frame information that doesn't fit anywhere else
  11 // cleanly...
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #if !defined(SPUFRAMEINFO_H)
  16
  17 #include "llvm/Target/TargetFrameInfo.h"
  18 #include "llvm/Target/TargetMachine.h"
  19 #include "SPURegisterInfo.h"
  20
  21 namespace llvm {
  22   class SPUFrameInfo: public TargetFrameInfo {
  23     const TargetMachine &TM;
  24     std::pair<unsigned, int> LR[1];
  25
  26   public:
  27     SPUFrameInfo(const TargetMachine &tm);
  28
  29     //! Return a function's saved spill slots
  30     /*!
  31       For CellSPU, a function's saved spill slots is just the link register.
  32      */
  33     const std::pair<unsigned, int> *
  34     getCalleeSaveSpillSlots(unsigned &NumEntries) const;
  35
  36     //! Stack slot size (16 bytes)
  37     static int stackSlotSize() {
  38       return 16;
  39     }
  40     //! Maximum frame offset representable by a signed 10-bit integer
  41     /*!
  42       This is the maximum frame offset that can be expressed as a 10-bit
  43       integer, used in D-form addresses.
  44      */
  45     static int maxFrameOffset() {
  46       return ((1 << 9) - 1) * stackSlotSize();
  47     }
  48     //! Minimum frame offset representable by a signed 10-bit integer
  49     static int minFrameOffset() {
  50       return -(1 << 9) * stackSlotSize();
  51     }
  52     //! Minimum frame size (enough to spill LR + SP)
  53     static int minStackSize() {
  54       return (2 * stackSlotSize());
  55     }
  56     //! Frame size required to spill all registers plus frame info
  57     static int fullSpillSize() {
  58       return (SPURegisterInfo::getNumArgRegs() * stackSlotSize());
  59     }
  60     //! Convert frame index to stack offset
  61     static int FItoStackOffset(int frame_index) {
  62       return frame_index * stackSlotSize();
  63     }
  64     //! Number of instructions required to overcome hint-for-branch latency
  65     /*!
  66       HBR (hint-for-branch) instructions can be inserted when, for example,
  67       we know that a given function is going to be called, such as printf(),
  68       in the control flow graph. HBRs are only inserted if a sufficient number
  69       of instructions occurs between the HBR and the target. Currently, HBRs
  70       take 6 cycles, ergo, the magic number 6.
  71      */
  72     static int branchHintPenalty() {
  73       return 6;
  74     }
  75   };
  76 }
  77
  78 #define SPUFRAMEINFO_H 1
  79 #endif