lib/Target/IA64/IA64Bundling.cpp

   1 //===-- IA64Bundling.cpp - IA-64 instruction bundling pass. ------------ --===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Add stops where required to prevent read-after-write and write-after-write
  11 // dependencies, for both registers and memory addresses. There are exceptions:
  12 //
  13 //    - Compare instructions (cmp*, tbit, tnat, fcmp, frcpa) are OK with
  14 //      WAW dependencies so long as they all target p0, or are of parallel
  15 //      type (.and*/.or*)
  16 //
  17 // FIXME: bundling, for now, is left to the assembler.
  18 // FIXME: this might be an appropriate place to translate between different
  19 //        instructions that do the same thing, if this helps bundling.
  20 //
  21 //===----------------------------------------------------------------------===//
  22
  23 #define DEBUG_TYPE "ia64-codegen"
  24 #include "IA64.h"
  25 #include "IA64InstrInfo.h"
  26 #include "IA64TargetMachine.h"
  27 #include "llvm/CodeGen/MachineFunctionPass.h"
  28 #include "llvm/CodeGen/MachineInstrBuilder.h"
  29 #include "llvm/ADT/SetOperations.h"
  30 #include "llvm/ADT/Statistic.h"
  31 #include "llvm/Support/Debug.h"
  32 #include <set>
  33 using namespace llvm;
  34
  35 STATISTIC(StopBitsAdded, "Number of stop bits added");
  36
  37 namespace {
  38   struct IA64BundlingPass : public MachineFunctionPass {
  39     static char ID;
  40     /// Target machine description which we query for reg. names, data
  41     /// layout, etc.
  42     ///
  43     IA64TargetMachine &TM;
  44
  45     IA64BundlingPass(IA64TargetMachine &tm)
  46       : MachineFunctionPass(&ID), TM(tm) { }
  47
  48     virtual const char *getPassName() const {
  49       return "IA64 (Itanium) Bundling Pass";
  50     }
  51
  52     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
  53     bool runOnMachineFunction(MachineFunction &F) {
  54       bool Changed = false;
  55       for (MachineFunction::iterator FI = F.begin(), FE = F.end();
  56            FI != FE; ++FI)
  57         Changed |= runOnMachineBasicBlock(*FI);
  58       return Changed;
  59     }
  60
  61     // XXX: ugly global, but pending writes can cross basic blocks. Note that
  62     // taken branches end instruction groups. So we only need to worry about
  63     // 'fallthrough' code
  64     std::set<unsigned> PendingRegWrites;
  65   };
  66   char IA64BundlingPass::ID = 0;
  67 } // end of anonymous namespace
  68
  69 /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
  70 /// and arranges the result into bundles.
  71 ///
  72 FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
  73   return new IA64BundlingPass(tm);
  74 }
  75
  76 /// runOnMachineBasicBlock - add stops and bundle this MBB.
  77 ///
  78 bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
  79   bool Changed = false;
  80
  81   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
  82     MachineInstr *CurrentInsn = I++;
  83     std::set<unsigned> CurrentReads, CurrentWrites, OrigWrites;
  84
  85     for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
  86       MachineOperand &MO=CurrentInsn->getOperand(i);
  87       if (MO.isReg()) {
  88         if(MO.isUse()) { // TODO: exclude p0
  89           CurrentReads.insert(MO.getReg());
  90         }
  91         if(MO.isDef()) { // TODO: exclude p0
  92           CurrentWrites.insert(MO.getReg());
  93           OrigWrites.insert(MO.getReg()); // FIXME: use a nondestructive
  94                                           // set_intersect instead?
  95         }
  96       }
  97     }
  98
  99     // CurrentReads/CurrentWrites contain info for the current instruction.
 100     // Does it read or write any registers that are pending a write?
 101     // (i.e. not separated by a stop)
 102     set_intersect(CurrentReads, PendingRegWrites);
 103     set_intersect(CurrentWrites, PendingRegWrites);
 104
 105     if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
 106       // there is a conflict, insert a stop and reset PendingRegWrites
 107       CurrentInsn = BuildMI(MBB, CurrentInsn, CurrentInsn->getDebugLoc(),
 108                             TM.getInstrInfo()->get(IA64::STOP), 0);
 109       PendingRegWrites=OrigWrites; // carry over current writes to next insn
 110       Changed=true; StopBitsAdded++; // update stats
 111     } else { // otherwise, track additional pending writes
 112       set_union(PendingRegWrites, OrigWrites);
 113     }
 114   } // onto the next insn in the MBB
 115
 116   return Changed;
 117 }
 118