lib/Target/MSP430/MSP430ISelLowering.cpp

   1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the MSP430TargetLowering class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "msp430-lower"
  15
  16 #include "MSP430ISelLowering.h"
  17 #include "MSP430.h"
  18 #include "MSP430TargetMachine.h"
  19 #include "MSP430Subtarget.h"
  20 #include "llvm/DerivedTypes.h"
  21 #include "llvm/Function.h"
  22 #include "llvm/Intrinsics.h"
  23 #include "llvm/CallingConv.h"
  24 #include "llvm/GlobalVariable.h"
  25 #include "llvm/GlobalAlias.h"
  26 #include "llvm/CodeGen/CallingConvLower.h"
  27 #include "llvm/CodeGen/MachineFrameInfo.h"
  28 #include "llvm/CodeGen/MachineFunction.h"
  29 #include "llvm/CodeGen/MachineInstrBuilder.h"
  30 #include "llvm/CodeGen/MachineRegisterInfo.h"
  31 #include "llvm/CodeGen/PseudoSourceValue.h"
  32 #include "llvm/CodeGen/SelectionDAGISel.h"
  33 #include "llvm/CodeGen/ValueTypes.h"
  34 #include "llvm/Support/Debug.h"
  35 #include "llvm/ADT/VectorExtras.h"
  36 using namespace llvm;
  37
  38 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
  39   TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
  40
  41   // Set up the register classes.
  42   addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
  43   addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
  44
  45   // Compute derived properties from the register classes
  46   computeRegisterProperties();
  47
  48   // Provide all sorts of operation actions
  49
  50   // Division is expensive
  51   setIntDivIsCheap(false);
  52
  53   // Even if we have only 1 bit shift here, we can perform
  54   // shifts of the whole bitwidth 1 bit per step.
  55   setShiftAmountType(MVT::i8);
  56
  57   setStackPointerRegisterToSaveRestore(MSP430::SPW);
  58   setBooleanContents(ZeroOrOneBooleanContent);
  59   setSchedulingPreference(SchedulingForLatency);
  60
  61   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
  62   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
  63   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
  64   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
  65   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
  66
  67   // We don't have any truncstores
  68   setTruncStoreAction(MVT::i16, MVT::i8, Expand);
  69
  70   setOperationAction(ISD::SRA,              MVT::i8,    Custom);
  71   setOperationAction(ISD::SHL,              MVT::i8,    Custom);
  72   setOperationAction(ISD::SRL,              MVT::i8,    Custom);
  73   setOperationAction(ISD::SRA,              MVT::i16,   Custom);
  74   setOperationAction(ISD::SHL,              MVT::i16,   Custom);
  75   setOperationAction(ISD::SRL,              MVT::i16,   Custom);
  76   setOperationAction(ISD::RET,              MVT::Other, Custom);
  77   setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
  78   setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
  79   setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
  80   setOperationAction(ISD::BRIND,            MVT::Other, Expand);
  81   setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
  82   setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
  83   setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
  84   setOperationAction(ISD::SETCC,            MVT::i8,    Expand);
  85   setOperationAction(ISD::SETCC,            MVT::i16,   Expand);
  86   setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
  87   setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
  88   setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
  89   setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
  90   setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
  91
  92   // FIXME: Implement efficiently multiplication by a constant
  93   setOperationAction(ISD::MUL,              MVT::i16,   Expand);
  94   setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
  95   setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
  96   setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
  97   setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
  98
  99   setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
 100   setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
 101   setOperationAction(ISD::UREM,             MVT::i16,   Expand);
 102   setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
 103   setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
 104   setOperationAction(ISD::SREM,             MVT::i16,   Expand);
 105 }
 106
 107 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
 108   switch (Op.getOpcode()) {
 109   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
 110   case ISD::SHL: // FALLTHROUGH
 111   case ISD::SRL:
 112   case ISD::SRA:              return LowerShifts(Op, DAG);
 113   case ISD::RET:              return LowerRET(Op, DAG);
 114   case ISD::CALL:             return LowerCALL(Op, DAG);
 115   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
 116   case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
 117   case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
 118   case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
 119   case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
 120   default:
 121     assert(0 && "unimplemented operand");
 122     return SDValue();
 123   }
 124 }
 125
 126 //===----------------------------------------------------------------------===//
 127 //                      Calling Convention Implementation
 128 //===----------------------------------------------------------------------===//
 129
 130 #include "MSP430GenCallingConv.inc"
 131
 132 SDValue MSP430TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
 133                                                     SelectionDAG &DAG) {
 134   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
 135   switch (CC) {
 136   default:
 137     assert(0 && "Unsupported calling convention");
 138   case CallingConv::C:
 139   case CallingConv::Fast:
 140     return LowerCCCArguments(Op, DAG);
 141   }
 142 }
 143
 144 SDValue MSP430TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
 145   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
 146   unsigned CallingConv = TheCall->getCallingConv();
 147   switch (CallingConv) {
 148   default:
 149     assert(0 && "Unsupported calling convention");
 150   case CallingConv::Fast:
 151   case CallingConv::C:
 152     return LowerCCCCallTo(Op, DAG, CallingConv);
 153   }
 154 }
 155
 156 /// LowerCCCArguments - transform physical registers into virtual registers and
 157 /// generate load operations for arguments places on the stack.
 158 // FIXME: struct return stuff
 159 // FIXME: varargs
 160 SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
 161                                                 SelectionDAG &DAG) {
 162   MachineFunction &MF = DAG.getMachineFunction();
 163   MachineFrameInfo *MFI = MF.getFrameInfo();
 164   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 165   SDValue Root = Op.getOperand(0);
 166   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
 167   unsigned CC = MF.getFunction()->getCallingConv();
 168   DebugLoc dl = Op.getDebugLoc();
 169
 170   // Assign locations to all of the incoming arguments.
 171   SmallVector<CCValAssign, 16> ArgLocs;
 172   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 173   CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
 174
 175   assert(!isVarArg && "Varargs not supported yet");
 176
 177   SmallVector<SDValue, 16> ArgValues;
 178   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 179     CCValAssign &VA = ArgLocs[i];
 180     if (VA.isRegLoc()) {
 181       // Arguments passed in registers
 182       MVT RegVT = VA.getLocVT();
 183       switch (RegVT.getSimpleVT()) {
 184       default:
 185         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 186              << RegVT.getSimpleVT()
 187              << "\n";
 188         abort();
 189       case MVT::i16:
 190         unsigned VReg =
 191           RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
 192         RegInfo.addLiveIn(VA.getLocReg(), VReg);
 193         SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
 194
 195         // If this is an 8-bit value, it is really passed promoted to 16
 196         // bits. Insert an assert[sz]ext to capture this, then truncate to the
 197         // right size.
 198         if (VA.getLocInfo() == CCValAssign::SExt)
 199           ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
 200                                  DAG.getValueType(VA.getValVT()));
 201         else if (VA.getLocInfo() == CCValAssign::ZExt)
 202           ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
 203                                  DAG.getValueType(VA.getValVT()));
 204
 205         if (VA.getLocInfo() != CCValAssign::Full)
 206           ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
 207
 208         ArgValues.push_back(ArgValue);
 209       }
 210     } else {
 211       // Sanity check
 212       assert(VA.isMemLoc());
 213       // Load the argument to a virtual register
 214       unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
 215       if (ObjSize > 2) {
 216         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 217              << VA.getLocVT().getSimpleVT()
 218              << "\n";
 219       }
 220       // Create the frame index object for this incoming parameter...
 221       int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
 222
 223       // Create the SelectionDAG nodes corresponding to a load
 224       //from this parameter
 225       SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
 226       ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
 227                                       PseudoSourceValue::getFixedStack(FI), 0));
 228     }
 229   }
 230
 231   ArgValues.push_back(Root);
 232
 233   // Return the new list of results.
 234   return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
 235                      &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
 236 }
 237
 238 SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
 239   // CCValAssign - represent the assignment of the return value to a location
 240   SmallVector<CCValAssign, 16> RVLocs;
 241   unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
 242   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
 243   DebugLoc dl = Op.getDebugLoc();
 244
 245   // CCState - Info about the registers and stack slot.
 246   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
 247
 248   // Analize return values of ISD::RET
 249   CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
 250
 251   // If this is the first return lowered for this function, add the regs to the
 252   // liveout set for the function.
 253   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 254     for (unsigned i = 0; i != RVLocs.size(); ++i)
 255       if (RVLocs[i].isRegLoc())
 256         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 257   }
 258
 259   // The chain is always operand #0
 260   SDValue Chain = Op.getOperand(0);
 261   SDValue Flag;
 262
 263   // Copy the result values into the output registers.
 264   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 265     CCValAssign &VA = RVLocs[i];
 266     assert(VA.isRegLoc() && "Can only return in registers!");
 267
 268     // ISD::RET => ret chain, (regnum1,val1), ...
 269     // So i*2+1 index only the regnums
 270     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
 271                              Op.getOperand(i*2+1), Flag);
 272
 273     // Guarantee that all emitted copies are stuck together,
 274     // avoiding something bad.
 275     Flag = Chain.getValue(1);
 276   }
 277
 278   if (Flag.getNode())
 279     return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
 280
 281   // Return Void
 282   return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
 283 }
 284
 285 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
 286 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
 287 /// TODO: sret.
 288 SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
 289                                              unsigned CC) {
 290   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
 291   SDValue Chain  = TheCall->getChain();
 292   SDValue Callee = TheCall->getCallee();
 293   bool isVarArg  = TheCall->isVarArg();
 294   DebugLoc dl = Op.getDebugLoc();
 295
 296   // Analyze operands of the call, assigning locations to each operand.
 297   SmallVector<CCValAssign, 16> ArgLocs;
 298   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 299
 300   CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
 301
 302   // Get a count of how many bytes are to be pushed on the stack.
 303   unsigned NumBytes = CCInfo.getNextStackOffset();
 304
 305   Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
 306                                                       getPointerTy(), true));
 307
 308   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
 309   SmallVector<SDValue, 12> MemOpChains;
 310   SDValue StackPtr;
 311
 312   // Walk the register/memloc assignments, inserting copies/loads.
 313   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 314     CCValAssign &VA = ArgLocs[i];
 315
 316     // Arguments start after the 5 first operands of ISD::CALL
 317     SDValue Arg = TheCall->getArg(i);
 318
 319     // Promote the value if needed.
 320     switch (VA.getLocInfo()) {
 321       default: assert(0 && "Unknown loc info!");
 322       case CCValAssign::Full: break;
 323       case CCValAssign::SExt:
 324         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 325         break;
 326       case CCValAssign::ZExt:
 327         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 328         break;
 329       case CCValAssign::AExt:
 330         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 331         break;
 332     }
 333
 334     // Arguments that can be passed on register must be kept at RegsToPass
 335     // vector
 336     if (VA.isRegLoc()) {
 337       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 338     } else {
 339       assert(VA.isMemLoc());
 340
 341       if (StackPtr.getNode() == 0)
 342         StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
 343
 344       SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
 345                                    StackPtr,
 346                                    DAG.getIntPtrConstant(VA.getLocMemOffset()));
 347
 348
 349       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
 350                                          PseudoSourceValue::getStack(),
 351                                          VA.getLocMemOffset()));
 352     }
 353   }
 354
 355   // Transform all store nodes into one single node because all store nodes are
 356   // independent of each other.
 357   if (!MemOpChains.empty())
 358     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 359                         &MemOpChains[0], MemOpChains.size());
 360
 361   // Build a sequence of copy-to-reg nodes chained together with token chain and
 362   // flag operands which copy the outgoing args into registers.  The InFlag in
 363   // necessary since all emited instructions must be stuck together.
 364   SDValue InFlag;
 365   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 366     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 367                              RegsToPass[i].second, InFlag);
 368     InFlag = Chain.getValue(1);
 369   }
 370
 371   // If the callee is a GlobalAddress node (quite common, every direct call is)
 372   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 373   // Likewise ExternalSymbol -> TargetExternalSymbol.
 374   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 375     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
 376   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 377     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
 378
 379   // Returns a chain & a flag for retval copy to use.
 380   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
 381   SmallVector<SDValue, 8> Ops;
 382   Ops.push_back(Chain);
 383   Ops.push_back(Callee);
 384
 385   // Add argument registers to the end of the list so that they are
 386   // known live into the call.
 387   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
 388     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
 389                                   RegsToPass[i].second.getValueType()));
 390
 391   if (InFlag.getNode())
 392     Ops.push_back(InFlag);
 393
 394   Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
 395   InFlag = Chain.getValue(1);
 396
 397   // Create the CALLSEQ_END node.
 398   Chain = DAG.getCALLSEQ_END(Chain,
 399                              DAG.getConstant(NumBytes, getPointerTy(), true),
 400                              DAG.getConstant(0, getPointerTy(), true),
 401                              InFlag);
 402   InFlag = Chain.getValue(1);
 403
 404   // Handle result values, copying them out of physregs into vregs that we
 405   // return.
 406   return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
 407                  Op.getResNo());
 408 }
 409
 410 /// LowerCallResult - Lower the result values of an ISD::CALL into the
 411 /// appropriate copies out of appropriate physical registers.  This assumes that
 412 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
 413 /// being lowered. Returns a SDNode with the same number of values as the
 414 /// ISD::CALL.
 415 SDNode*
 416 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
 417                                       CallSDNode *TheCall,
 418                                       unsigned CallingConv,
 419                                       SelectionDAG &DAG) {
 420   bool isVarArg = TheCall->isVarArg();
 421   DebugLoc dl = TheCall->getDebugLoc();
 422
 423   // Assign locations to each value returned by this call.
 424   SmallVector<CCValAssign, 16> RVLocs;
 425   CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
 426
 427   CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
 428   SmallVector<SDValue, 8> ResultVals;
 429
 430   // Copy all of the result registers out of their specified physreg.
 431   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 432     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
 433                                RVLocs[i].getValVT(), InFlag).getValue(1);
 434     InFlag = Chain.getValue(2);
 435     ResultVals.push_back(Chain.getValue(0));
 436   }
 437
 438   ResultVals.push_back(Chain);
 439
 440   // Merge everything together with a MERGE_VALUES node.
 441   return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
 442                      &ResultVals[0], ResultVals.size()).getNode();
 443 }
 444
 445 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
 446                                           SelectionDAG &DAG) {
 447   unsigned Opc = Op.getOpcode();
 448   SDNode* N = Op.getNode();
 449   MVT VT = Op.getValueType();
 450   DebugLoc dl = N->getDebugLoc();
 451
 452   // We currently only lower shifts of constant argument.
 453   if (!isa<ConstantSDNode>(N->getOperand(1)))
 454     return SDValue();
 455
 456   uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
 457
 458   // Expand the stuff into sequence of shifts.
 459   // FIXME: for some shift amounts this might be done better!
 460   // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
 461   SDValue Victim = N->getOperand(0);
 462
 463   if (Opc == ISD::SRL && ShiftAmount) {
 464     // Emit a special goodness here:
 465     // srl A, 1 => clrc; rrc A
 466     Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
 467     ShiftAmount -= 1;
 468   }
 469
 470   while (ShiftAmount--)
 471     Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
 472                          dl, VT, Victim);
 473
 474   return Victim;
 475 }
 476
 477 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
 478   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 479   int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
 480
 481   // Create the TargetGlobalAddress node, folding in the constant offset.
 482   SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
 483   return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
 484                      getPointerTy(), Result);
 485 }
 486
 487 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
 488                                                   SelectionDAG &DAG) {
 489   DebugLoc dl = Op.getDebugLoc();
 490   const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
 491   SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
 492
 493   return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
 494 }
 495
 496 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC,
 497                        ISD::CondCode CC,
 498                        DebugLoc dl, SelectionDAG &DAG) {
 499   // FIXME: Handle bittests someday
 500   assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
 501
 502   // FIXME: Handle jump negative someday
 503   TargetCC = MSP430::COND_INVALID;
 504   switch (CC) {
 505   default: assert(0 && "Invalid integer condition!");
 506   case ISD::SETEQ:
 507     TargetCC = MSP430::COND_E;  // aka COND_Z
 508     break;
 509   case ISD::SETNE:
 510     TargetCC = MSP430::COND_NE; // aka COND_NZ
 511     break;
 512   case ISD::SETULE:
 513     std::swap(LHS, RHS);        // FALLTHROUGH
 514   case ISD::SETUGE:
 515     TargetCC = MSP430::COND_HS; // aka COND_C
 516     break;
 517   case ISD::SETUGT:
 518     std::swap(LHS, RHS);        // FALLTHROUGH
 519   case ISD::SETULT:
 520     TargetCC = MSP430::COND_LO; // aka COND_NC
 521     break;
 522   case ISD::SETLE:
 523     std::swap(LHS, RHS);        // FALLTHROUGH
 524   case ISD::SETGE:
 525     TargetCC = MSP430::COND_GE;
 526     break;
 527   case ISD::SETGT:
 528     std::swap(LHS, RHS);        // FALLTHROUGH
 529   case ISD::SETLT:
 530     TargetCC = MSP430::COND_L;
 531     break;
 532   }
 533
 534   return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
 535 }
 536
 537
 538 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
 539   SDValue Chain = Op.getOperand(0);
 540   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
 541   SDValue LHS   = Op.getOperand(2);
 542   SDValue RHS   = Op.getOperand(3);
 543   SDValue Dest  = Op.getOperand(4);
 544   DebugLoc dl   = Op.getDebugLoc();
 545
 546   unsigned TargetCC = MSP430::COND_INVALID;
 547   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
 548
 549   return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
 550                      Chain,
 551                      Dest, DAG.getConstant(TargetCC, MVT::i8),
 552                      Flag);
 553 }
 554
 555 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
 556   SDValue LHS    = Op.getOperand(0);
 557   SDValue RHS    = Op.getOperand(1);
 558   SDValue TrueV  = Op.getOperand(2);
 559   SDValue FalseV = Op.getOperand(3);
 560   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
 561   DebugLoc dl    = Op.getDebugLoc();
 562
 563   unsigned TargetCC = MSP430::COND_INVALID;
 564   SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
 565
 566   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
 567   SmallVector<SDValue, 4> Ops;
 568   Ops.push_back(TrueV);
 569   Ops.push_back(FalseV);
 570   Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
 571   Ops.push_back(Flag);
 572
 573   return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
 574 }
 575
 576 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
 577                                                SelectionDAG &DAG) {
 578   SDValue Val = Op.getOperand(0);
 579   MVT VT      = Op.getValueType();
 580   DebugLoc dl = Op.getDebugLoc();
 581
 582   assert(VT == MVT::i16 && "Only support i16 for now!");
 583
 584   return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
 585                      DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
 586                      DAG.getValueType(Val.getValueType()));
 587 }
 588
 589 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
 590   switch (Opcode) {
 591   default: return NULL;
 592   case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
 593   case MSP430ISD::RRA:                return "MSP430ISD::RRA";
 594   case MSP430ISD::RLA:                return "MSP430ISD::RLA";
 595   case MSP430ISD::RRC:                return "MSP430ISD::RRC";
 596   case MSP430ISD::CALL:               return "MSP430ISD::CALL";
 597   case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
 598   case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
 599   case MSP430ISD::CMP:                return "MSP430ISD::CMP";
 600   case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
 601   }
 602 }
 603
 604 //===----------------------------------------------------------------------===//
 605 //  Other Lowering Code
 606 //===----------------------------------------------------------------------===//
 607
 608 MachineBasicBlock*
 609 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
 610                                                   MachineBasicBlock *BB) const {
 611   const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
 612   DebugLoc dl = MI->getDebugLoc();
 613   assert((MI->getOpcode() == MSP430::Select16 ||
 614           MI->getOpcode() == MSP430::Select8) &&
 615          "Unexpected instr type to insert");
 616
 617   // To "insert" a SELECT instruction, we actually have to insert the diamond
 618   // control-flow pattern.  The incoming instruction knows the destination vreg
 619   // to set, the condition code register to branch on, the true/false values to
 620   // select between, and a branch opcode to use.
 621   const BasicBlock *LLVM_BB = BB->getBasicBlock();
 622   MachineFunction::iterator I = BB;
 623   ++I;
 624
 625   //  thisMBB:
 626   //  ...
 627   //   TrueVal = ...
 628   //   cmpTY ccX, r1, r2
 629   //   jCC copy1MBB
 630   //   fallthrough --> copy0MBB
 631   MachineBasicBlock *thisMBB = BB;
 632   MachineFunction *F = BB->getParent();
 633   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
 634   MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
 635   BuildMI(BB, dl, TII.get(MSP430::JCC))
 636     .addMBB(copy1MBB)
 637     .addImm(MI->getOperand(3).getImm());
 638   F->insert(I, copy0MBB);
 639   F->insert(I, copy1MBB);
 640   // Update machine-CFG edges by transferring all successors of the current
 641   // block to the new block which will contain the Phi node for the select.
 642   copy1MBB->transferSuccessors(BB);
 643   // Next, add the true and fallthrough blocks as its successors.
 644   BB->addSuccessor(copy0MBB);
 645   BB->addSuccessor(copy1MBB);
 646
 647   //  copy0MBB:
 648   //   %FalseValue = ...
 649   //   # fallthrough to copy1MBB
 650   BB = copy0MBB;
 651
 652   // Update machine-CFG edges
 653   BB->addSuccessor(copy1MBB);
 654
 655   //  copy1MBB:
 656   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
 657   //  ...
 658   BB = copy1MBB;
 659   BuildMI(BB, dl, TII.get(MSP430::PHI),
 660           MI->getOperand(0).getReg())
 661     .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
 662     .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
 663
 664   F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
 665   return BB;
 666 }