lib/Target/Mips/MipsInstrInfo.h

   1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef MIPSINSTRUCTIONINFO_H
  15 #define MIPSINSTRUCTIONINFO_H
  16
  17 #include "Mips.h"
  18 #include "llvm/Target/TargetInstrInfo.h"
  19 #include "MipsRegisterInfo.h"
  20
  21 namespace llvm {
  22
  23 namespace Mips {
  24
  25   // Mips Branch Codes
  26   enum FPBranchCode {
  27     BRANCH_F,
  28     BRANCH_T,
  29     BRANCH_FL,
  30     BRANCH_TL,
  31     BRANCH_INVALID
  32   };
  33
  34   // Mips Condition Codes
  35   enum CondCode {
  36     // To be used with float branch True
  37     FCOND_F,
  38     FCOND_UN,
  39     FCOND_EQ,
  40     FCOND_UEQ,
  41     FCOND_OLT,
  42     FCOND_ULT,
  43     FCOND_OLE,
  44     FCOND_ULE,
  45     FCOND_SF,
  46     FCOND_NGLE,
  47     FCOND_SEQ,
  48     FCOND_NGL,
  49     FCOND_LT,
  50     FCOND_NGE,
  51     FCOND_LE,
  52     FCOND_NGT,
  53
  54     // To be used with float branch False
  55     // This conditions have the same mnemonic as the
  56     // above ones, but are used with a branch False;
  57     FCOND_T,
  58     FCOND_OR,
  59     FCOND_NEQ,
  60     FCOND_OGL,
  61     FCOND_UGE,
  62     FCOND_OGE,
  63     FCOND_UGT,
  64     FCOND_OGT,
  65     FCOND_ST,
  66     FCOND_GLE,
  67     FCOND_SNE,
  68     FCOND_GL,
  69     FCOND_NLT,
  70     FCOND_GE,
  71     FCOND_NLE,
  72     FCOND_GT,
  73
  74     // Only integer conditions
  75     COND_E,
  76     COND_GZ,
  77     COND_GEZ,
  78     COND_LZ,
  79     COND_LEZ,
  80     COND_NE,
  81     COND_INVALID
  82   };
  83
  84   // Turn condition code into conditional branch opcode.
  85   unsigned GetCondBranchFromCond(CondCode CC);
  86
  87   /// GetOppositeBranchCondition - Return the inverse of the specified cond,
  88   /// e.g. turning COND_E to COND_NE.
  89   CondCode GetOppositeBranchCondition(Mips::CondCode CC);
  90
  91   /// MipsCCToString - Map each FP condition code to its string
  92   inline static const char *MipsFCCToString(Mips::CondCode CC)
  93   {
  94     switch (CC) {
  95       default: assert(0 && "Unknown condition code");
  96       case FCOND_F:
  97       case FCOND_T:   return "f";
  98       case FCOND_UN:
  99       case FCOND_OR:  return "un";
 100       case FCOND_EQ:
 101       case FCOND_NEQ: return "eq";
 102       case FCOND_UEQ:
 103       case FCOND_OGL: return "ueq";
 104       case FCOND_OLT:
 105       case FCOND_UGE: return "olt";
 106       case FCOND_ULT:
 107       case FCOND_OGE: return "ult";
 108       case FCOND_OLE:
 109       case FCOND_UGT: return "ole";
 110       case FCOND_ULE:
 111       case FCOND_OGT: return "ule";
 112       case FCOND_SF:
 113       case FCOND_ST:  return "sf";
 114       case FCOND_NGLE:
 115       case FCOND_GLE: return "ngle";
 116       case FCOND_SEQ:
 117       case FCOND_SNE: return "seq";
 118       case FCOND_NGL:
 119       case FCOND_GL:  return "ngl";
 120       case FCOND_LT:
 121       case FCOND_NLT: return "lt";
 122       case FCOND_NGE:
 123       case FCOND_GE:  return "ge";
 124       case FCOND_LE:
 125       case FCOND_NLE: return "nle";
 126       case FCOND_NGT:
 127       case FCOND_GT:  return "gt";
 128     }
 129   }
 130 }
 131
 132 class MipsInstrInfo : public TargetInstrInfoImpl {
 133   MipsTargetMachine &TM;
 134   const MipsRegisterInfo RI;
 135 public:
 136   explicit MipsInstrInfo(MipsTargetMachine &TM);
 137
 138   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
 139   /// such, whenever a client has an instance of instruction info, it should
 140   /// always be able to get register info as well (through this method).
 141   ///
 142   virtual const MipsRegisterInfo &getRegisterInfo() const { return RI; }
 143
 144   /// Return true if the instruction is a register to register move and return
 145   /// the source and dest operands and their sub-register indices by reference.
 146   virtual bool isMoveInstr(const MachineInstr &MI,
 147                            unsigned &SrcReg, unsigned &DstReg,
 148                            unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
 149
 150   /// isLoadFromStackSlot - If the specified machine instruction is a direct
 151   /// load from a stack slot, return the virtual or physical register number of
 152   /// the destination along with the FrameIndex of the loaded stack slot.  If
 153   /// not, return 0.  This predicate must return 0 if the instruction has
 154   /// any side effects other than loading from the stack slot.
 155   virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
 156                                        int &FrameIndex) const;
 157
 158   /// isStoreToStackSlot - If the specified machine instruction is a direct
 159   /// store to a stack slot, return the virtual or physical register number of
 160   /// the source reg along with the FrameIndex of the loaded stack slot.  If
 161   /// not, return 0.  This predicate must return 0 if the instruction has
 162   /// any side effects other than storing to the stack slot.
 163   virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
 164                                       int &FrameIndex) const;
 165
 166   /// Branch Analysis
 167   virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 168                              MachineBasicBlock *&FBB,
 169                              SmallVectorImpl<MachineOperand> &Cond,
 170                              bool AllowModify) const;
 171   virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
 172   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 173                                 MachineBasicBlock *FBB,
 174                             const SmallVectorImpl<MachineOperand> &Cond) const;
 175   virtual bool copyRegToReg(MachineBasicBlock &MBB,
 176                             MachineBasicBlock::iterator I,
 177                             unsigned DestReg, unsigned SrcReg,
 178                             const TargetRegisterClass *DestRC,
 179                             const TargetRegisterClass *SrcRC) const;
 180   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
 181                                    MachineBasicBlock::iterator MBBI,
 182                                    unsigned SrcReg, bool isKill, int FrameIndex,
 183                                    const TargetRegisterClass *RC) const;
 184
 185   virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
 186                               SmallVectorImpl<MachineOperand> &Addr,
 187                               const TargetRegisterClass *RC,
 188                               SmallVectorImpl<MachineInstr*> &NewMIs) const;
 189
 190   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
 191                                     MachineBasicBlock::iterator MBBI,
 192                                     unsigned DestReg, int FrameIndex,
 193                                     const TargetRegisterClass *RC) const;
 194
 195   virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 196                                SmallVectorImpl<MachineOperand> &Addr,
 197                                const TargetRegisterClass *RC,
 198                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
 199
 200   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 201                                               MachineInstr* MI,
 202                                            const SmallVectorImpl<unsigned> &Ops,
 203                                               int FrameIndex) const;
 204
 205   virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
 206                                               MachineInstr* MI,
 207                                            const SmallVectorImpl<unsigned> &Ops,
 208                                               MachineInstr* LoadMI) const {
 209     return 0;
 210   }
 211
 212   virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
 213   virtual
 214   bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
 215
 216   /// Insert nop instruction when hazard condition is found
 217   virtual void insertNoop(MachineBasicBlock &MBB,
 218                           MachineBasicBlock::iterator MI) const;
 219 };
 220
 221 }
 222
 223 #endif