Merge branch 'master' into msp430
[llvm/msp430.git] / lib / Target / Mips / MipsSubtarget.h
blob656199a69ac3e560ae3a6d9c3a2581983592d089
1 //=====-- MipsSubtarget.h - Define Subtarget for the Mips -----*- C++ -*--====//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
17 #include "llvm/Target/TargetSubtarget.h"
18 #include "llvm/Target/TargetMachine.h"
20 #include <string>
22 namespace llvm {
23 class Module;
25 class MipsSubtarget : public TargetSubtarget {
27 public:
28 enum MipsABIEnum {
29 O32, O64, N32, N64, EABI
30 };
32 protected:
34 enum MipsArchEnum {
35 Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2
38 // Mips architecture version
39 MipsArchEnum MipsArchVersion;
41 // Mips supported ABIs
42 MipsABIEnum MipsABI;
44 // IsLittle - The target is Little Endian
45 bool IsLittle;
47 // IsSingleFloat - The target only supports single precision float
48 // point operations. This enable the target to use all 32 32-bit
49 // floating point registers instead of only using even ones.
50 bool IsSingleFloat;
52 // IsFP64bit - The target processor has 64-bit floating point registers.
53 bool IsFP64bit;
55 // IsFP64bit - General-purpose registers are 64 bits wide
56 bool IsGP64bit;
58 // HasVFPU - Processor has a vector floating point unit.
59 bool HasVFPU;
61 // IsABICall - Enable SRV4 code for SVR4-style dynamic objects
62 bool HasABICall;
64 // HasAbsoluteCall - Enable code that is not fully position-independent.
65 // Only works with HasABICall enabled.
66 bool HasAbsoluteCall;
68 // isLinux - Target system is Linux. Is false we consider ELFOS for now.
69 bool IsLinux;
71 // Put global and static items less than or equal to SSectionThreshold
72 // bytes into the small data or bss section. The default is 8.
73 unsigned SSectionThreshold;
75 /// Features related to the presence of specific instructions.
77 // HasSEInReg - SEB and SEH (signext in register) instructions.
78 bool HasSEInReg;
80 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
81 bool HasCondMov;
83 // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
84 // instructions.
85 bool HasMulDivAdd;
87 // HasMinMax - MIN and MAX instructions.
88 bool HasMinMax;
90 // HasSwap - Byte and half swap instructions.
91 bool HasSwap;
93 // HasBitCount - Count leading '1' and '0' bits.
94 bool HasBitCount;
96 InstrItineraryData InstrItins;
98 public:
100 /// Only O32 and EABI supported right now.
101 bool isABI_EABI() const { return MipsABI == EABI; }
102 bool isABI_O32() const { return MipsABI == O32; }
103 unsigned getTargetABI() const { return MipsABI; }
105 /// This constructor initializes the data members to match that
106 /// of the specified module.
107 MipsSubtarget(const TargetMachine &TM, const Module &M,
108 const std::string &FS, bool little);
110 /// ParseSubtargetFeatures - Parses features string setting specified
111 /// subtarget options. Definition of function is auto generated by tblgen.
112 void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
114 bool hasMips2Ops() const { return MipsArchVersion >= Mips2; }
116 bool isLittle() const { return IsLittle; }
117 bool isFP64bit() const { return IsFP64bit; };
118 bool isGP64bit() const { return IsGP64bit; };
119 bool isGP32bit() const { return !IsGP64bit; };
120 bool isSingleFloat() const { return IsSingleFloat; };
121 bool isNotSingleFloat() const { return !IsSingleFloat; };
122 bool hasVFPU() const { return HasVFPU; };
123 bool hasABICall() const { return HasABICall; };
124 bool hasAbsoluteCall() const { return HasAbsoluteCall; };
125 bool isLinux() const { return IsLinux; };
126 unsigned getSSectionThreshold() const { return SSectionThreshold; }
128 /// Features related to the presence of specific instructions.
129 bool hasSEInReg() const { return HasSEInReg; };
130 bool hasCondMov() const { return HasCondMov; };
131 bool hasMulDivAdd() const { return HasMulDivAdd; };
132 bool hasMinMax() const { return HasMinMax; };
133 bool hasSwap() const { return HasSwap; };
134 bool hasBitCount() const { return HasBitCount; };
136 } // End llvm namespace
138 #endif