lib/Target/PowerPC/PPC.td

   1 //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  27 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  28 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  29 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  32 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  33 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  34 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  35 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  36
  37 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  38                                         "Enable 64-bit instructions">;
  39 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  40                               "Enable 64-bit registers usage for ppc32 [beta]">;
  41 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  42                                         "Enable Altivec instructions">;
  43 def FeatureGPUL      : SubtargetFeature<"gpul","IsGigaProcessor", "true",
  44                                         "Enable GPUL instructions">;
  45 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  46                                         "Enable the fsqrt instruction">;
  47 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  48                                         "Enable the stfiwx instruction">;
  49
  50 //===----------------------------------------------------------------------===//
  51 // Register File Description
  52 //===----------------------------------------------------------------------===//
  53
  54 include "PPCRegisterInfo.td"
  55 include "PPCSchedule.td"
  56 include "PPCInstrInfo.td"
  57
  58 //===----------------------------------------------------------------------===//
  59 // PowerPC processors supported.
  60 //
  61
  62 def : Processor<"generic", G3Itineraries, [Directive32]>;
  63 def : Processor<"601", G3Itineraries, [Directive601]>;
  64 def : Processor<"602", G3Itineraries, [Directive602]>;
  65 def : Processor<"603", G3Itineraries, [Directive603]>;
  66 def : Processor<"603e", G3Itineraries, [Directive603]>;
  67 def : Processor<"603ev", G3Itineraries, [Directive603]>;
  68 def : Processor<"604", G3Itineraries, [Directive604]>;
  69 def : Processor<"604e", G3Itineraries, [Directive604]>;
  70 def : Processor<"620", G3Itineraries, [Directive620]>;
  71 def : Processor<"g3", G3Itineraries, [Directive7400]>;
  72 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
  73 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
  74 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
  75 def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
  76 def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
  77 def : Processor<"970", G5Itineraries,
  78                   [Directive970, FeatureAltivec,
  79                    FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  80                    Feature64Bit /*, Feature64BitRegs */]>;
  81 def : Processor<"g5", G5Itineraries,
  82                   [Directive970, FeatureAltivec,
  83                    FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  84                    Feature64Bit /*, Feature64BitRegs */]>;
  85 def : Processor<"ppc", G3Itineraries, [Directive32]>;
  86 def : Processor<"ppc64", G5Itineraries,
  87                   [Directive64, FeatureAltivec,
  88                    FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
  89                    Feature64Bit /*, Feature64BitRegs */]>;
  90
  91
  92 //===----------------------------------------------------------------------===//
  93 // Calling Conventions
  94 //===----------------------------------------------------------------------===//
  95
  96 include "PPCCallingConv.td"
  97
  98 def PPCInstrInfo : InstrInfo {
  99   // Define how we want to layout our TargetSpecific information field... This
 100   // should be kept up-to-date with the fields in the PPCInstrInfo.h file.
 101   let TSFlagsFields = ["PPC970_First",
 102                        "PPC970_Single",
 103                        "PPC970_Cracked",
 104                        "PPC970_Unit"];
 105   let TSFlagsShifts = [0, 1, 2, 3];
 106
 107   let isLittleEndianEncoding = 1;
 108 }
 109
 110
 111 def PPC : Target {
 112   // Information about the instructions.
 113   let InstructionSet = PPCInstrInfo;
 114 }