lib/Target/CellSPU/SPUISelDAGToDAG.cpp

   1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines a pattern matching instruction selector for the Cell SPU,
  11 // converting from a legalized dag to a SPU-target dag.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "SPU.h"
  16 #include "SPUTargetMachine.h"
  17 #include "SPUISelLowering.h"
  18 #include "SPUHazardRecognizers.h"
  19 #include "SPUFrameInfo.h"
  20 #include "SPURegisterNames.h"
  21 #include "SPUTargetMachine.h"
  22 #include "llvm/CodeGen/MachineConstantPool.h"
  23 #include "llvm/CodeGen/MachineInstrBuilder.h"
  24 #include "llvm/CodeGen/MachineFunction.h"
  25 #include "llvm/CodeGen/SelectionDAG.h"
  26 #include "llvm/CodeGen/SelectionDAGISel.h"
  27 #include "llvm/CodeGen/PseudoSourceValue.h"
  28 #include "llvm/Target/TargetOptions.h"
  29 #include "llvm/ADT/Statistic.h"
  30 #include "llvm/Constants.h"
  31 #include "llvm/GlobalValue.h"
  32 #include "llvm/Intrinsics.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Support/MathExtras.h"
  35 #include "llvm/Support/Compiler.h"
  36
  37 using namespace llvm;
  38
  39 namespace {
  40   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
  41   bool
  42   isI64IntS10Immediate(ConstantSDNode *CN)
  43   {
  44     return isS10Constant(CN->getSExtValue());
  45   }
  46
  47   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
  48   bool
  49   isI32IntS10Immediate(ConstantSDNode *CN)
  50   {
  51     return isS10Constant(CN->getSExtValue());
  52   }
  53
  54   //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
  55   bool
  56   isI32IntU10Immediate(ConstantSDNode *CN)
  57   {
  58     return isU10Constant(CN->getSExtValue());
  59   }
  60
  61   //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
  62   bool
  63   isI16IntS10Immediate(ConstantSDNode *CN)
  64   {
  65     return isS10Constant(CN->getSExtValue());
  66   }
  67
  68   //! SDNode predicate for i16 sign-extended, 10-bit immediate values
  69   bool
  70   isI16IntS10Immediate(SDNode *N)
  71   {
  72     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
  73     return (CN != 0 && isI16IntS10Immediate(CN));
  74   }
  75
  76   //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
  77   bool
  78   isI16IntU10Immediate(ConstantSDNode *CN)
  79   {
  80     return isU10Constant((short) CN->getZExtValue());
  81   }
  82
  83   //! SDNode predicate for i16 sign-extended, 10-bit immediate values
  84   bool
  85   isI16IntU10Immediate(SDNode *N)
  86   {
  87     return (N->getOpcode() == ISD::Constant
  88             && isI16IntU10Immediate(cast<ConstantSDNode>(N)));
  89   }
  90
  91   //! ConstantSDNode predicate for signed 16-bit values
  92   /*!
  93     \arg CN The constant SelectionDAG node holding the value
  94     \arg Imm The returned 16-bit value, if returning true
  95
  96     This predicate tests the value in \a CN to see whether it can be
  97     represented as a 16-bit, sign-extended quantity. Returns true if
  98     this is the case.
  99    */
 100   bool
 101   isIntS16Immediate(ConstantSDNode *CN, short &Imm)
 102   {
 103     MVT vt = CN->getValueType(0);
 104     Imm = (short) CN->getZExtValue();
 105     if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
 106       return true;
 107     } else if (vt == MVT::i32) {
 108       int32_t i_val = (int32_t) CN->getZExtValue();
 109       short s_val = (short) i_val;
 110       return i_val == s_val;
 111     } else {
 112       int64_t i_val = (int64_t) CN->getZExtValue();
 113       short s_val = (short) i_val;
 114       return i_val == s_val;
 115     }
 116
 117     return false;
 118   }
 119
 120   //! SDNode predicate for signed 16-bit values.
 121   bool
 122   isIntS16Immediate(SDNode *N, short &Imm)
 123   {
 124     return (N->getOpcode() == ISD::Constant
 125             && isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
 126   }
 127
 128   //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
 129   static bool
 130   isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
 131   {
 132     MVT vt = FPN->getValueType(0);
 133     if (vt == MVT::f32) {
 134       int val = FloatToBits(FPN->getValueAPF().convertToFloat());
 135       int sval = (int) ((val << 16) >> 16);
 136       Imm = (short) val;
 137       return val == sval;
 138     }
 139
 140     return false;
 141   }
 142
 143   bool
 144   isHighLow(const SDValue &Op)
 145   {
 146     return (Op.getOpcode() == SPUISD::IndirectAddr
 147             && ((Op.getOperand(0).getOpcode() == SPUISD::Hi
 148                  && Op.getOperand(1).getOpcode() == SPUISD::Lo)
 149                 || (Op.getOperand(0).getOpcode() == SPUISD::Lo
 150                     && Op.getOperand(1).getOpcode() == SPUISD::Hi)));
 151   }
 152
 153   //===------------------------------------------------------------------===//
 154   //! MVT to "useful stuff" mapping structure:
 155
 156   struct valtype_map_s {
 157     MVT VT;
 158     unsigned ldresult_ins;      /// LDRESULT instruction (0 = undefined)
 159     bool ldresult_imm;          /// LDRESULT instruction requires immediate?
 160     unsigned lrinst;            /// LR instruction
 161   };
 162
 163   const valtype_map_s valtype_map[] = {
 164     { MVT::i8,    SPU::ORBIr8,  true,  SPU::LRr8 },
 165     { MVT::i16,   SPU::ORHIr16, true,  SPU::LRr16 },
 166     { MVT::i32,   SPU::ORIr32,  true,  SPU::LRr32 },
 167     { MVT::i64,   SPU::ORr64,   false, SPU::LRr64 },
 168     { MVT::f32,   SPU::ORf32,   false, SPU::LRf32 },
 169     { MVT::f64,   SPU::ORf64,   false, SPU::LRf64 },
 170     // vector types... (sigh!)
 171     { MVT::v16i8, 0,            false, SPU::LRv16i8 },
 172     { MVT::v8i16, 0,            false, SPU::LRv8i16 },
 173     { MVT::v4i32, 0,            false, SPU::LRv4i32 },
 174     { MVT::v2i64, 0,            false, SPU::LRv2i64 },
 175     { MVT::v4f32, 0,            false, SPU::LRv4f32 },
 176     { MVT::v2f64, 0,            false, SPU::LRv2f64 }
 177   };
 178
 179   const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
 180
 181   const valtype_map_s *getValueTypeMapEntry(MVT VT)
 182   {
 183     const valtype_map_s *retval = 0;
 184     for (size_t i = 0; i < n_valtype_map; ++i) {
 185       if (valtype_map[i].VT == VT) {
 186         retval = valtype_map + i;
 187         break;
 188       }
 189     }
 190
 191
 192 #ifndef NDEBUG
 193     if (retval == 0) {
 194       cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
 195            << VT.getMVTString()
 196            << "\n";
 197       abort();
 198     }
 199 #endif
 200
 201     return retval;
 202   }
 203
 204   //! Generate the carry-generate shuffle mask.
 205   SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
 206     SmallVector<SDValue, 16 > ShufBytes;
 207
 208     // Create the shuffle mask for "rotating" the borrow up one register slot
 209     // once the borrow is generated.
 210     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
 211     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
 212     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
 213     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
 214
 215     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 216                        &ShufBytes[0], ShufBytes.size());
 217   }
 218
 219   //! Generate the borrow-generate shuffle mask
 220   SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
 221     SmallVector<SDValue, 16 > ShufBytes;
 222
 223     // Create the shuffle mask for "rotating" the borrow up one register slot
 224     // once the borrow is generated.
 225     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
 226     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
 227     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
 228     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
 229
 230     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 231                        &ShufBytes[0], ShufBytes.size());
 232   }
 233
 234   //===------------------------------------------------------------------===//
 235   /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
 236   /// instructions for SelectionDAG operations.
 237   ///
 238   class SPUDAGToDAGISel :
 239     public SelectionDAGISel
 240   {
 241     SPUTargetMachine &TM;
 242     SPUTargetLowering &SPUtli;
 243     unsigned GlobalBaseReg;
 244
 245   public:
 246     explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
 247       SelectionDAGISel(tm),
 248       TM(tm),
 249       SPUtli(*tm.getTargetLowering())
 250     { }
 251
 252     virtual bool runOnFunction(Function &Fn) {
 253       // Make sure we re-emit a set of the global base reg if necessary
 254       GlobalBaseReg = 0;
 255       SelectionDAGISel::runOnFunction(Fn);
 256       return true;
 257     }
 258
 259     /// getI32Imm - Return a target constant with the specified value, of type
 260     /// i32.
 261     inline SDValue getI32Imm(uint32_t Imm) {
 262       return CurDAG->getTargetConstant(Imm, MVT::i32);
 263     }
 264
 265     /// getI64Imm - Return a target constant with the specified value, of type
 266     /// i64.
 267     inline SDValue getI64Imm(uint64_t Imm) {
 268       return CurDAG->getTargetConstant(Imm, MVT::i64);
 269     }
 270
 271     /// getSmallIPtrImm - Return a target constant of pointer type.
 272     inline SDValue getSmallIPtrImm(unsigned Imm) {
 273       return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
 274       }
 275
 276     SDNode *emitBuildVector(SDValue build_vec) {
 277       MVT vecVT = build_vec.getValueType();
 278       MVT eltVT = vecVT.getVectorElementType();
 279       SDNode *bvNode = build_vec.getNode();
 280       DebugLoc dl = bvNode->getDebugLoc();
 281
 282       // Check to see if this vector can be represented as a CellSPU immediate
 283       // constant by invoking all of the instruction selection predicates:
 284       if (((vecVT == MVT::v8i16) &&
 285            (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
 286           ((vecVT == MVT::v4i32) &&
 287            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 288             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 289             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
 290             (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
 291           ((vecVT == MVT::v2i64) &&
 292            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
 293             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
 294             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
 295         return Select(build_vec);
 296
 297       // No, need to emit a constant pool spill:
 298       std::vector<Constant*> CV;
 299
 300       for (size_t i = 0; i < build_vec.getNumOperands(); ++i) {
 301         ConstantSDNode *V = dyn_cast<ConstantSDNode > (build_vec.getOperand(i));
 302         CV.push_back(const_cast<ConstantInt *> (V->getConstantIntValue()));
 303       }
 304
 305       Constant *CP = ConstantVector::get(CV);
 306       SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
 307       unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
 308       SDValue CGPoolOffset =
 309               SPU::LowerConstantPool(CPIdx, *CurDAG,
 310                                      SPUtli.getSPUTargetMachine());
 311       return SelectCode(CurDAG->getLoad(build_vec.getValueType(), dl,
 312                                         CurDAG->getEntryNode(), CGPoolOffset,
 313                                         PseudoSourceValue::getConstantPool(), 0,
 314                                         false, Alignment));
 315     }
 316
 317     /// Select - Convert the specified operand from a target-independent to a
 318     /// target-specific node if it hasn't already been changed.
 319     SDNode *Select(SDValue Op);
 320
 321     //! Emit the instruction sequence for i64 shl
 322     SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
 323
 324     //! Emit the instruction sequence for i64 srl
 325     SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
 326
 327     //! Emit the instruction sequence for i64 sra
 328     SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
 329
 330     //! Emit the necessary sequence for loading i64 constants:
 331     SDNode *SelectI64Constant(SDValue &Op, MVT OpVT, DebugLoc dl);
 332
 333     //! Alternate instruction emit sequence for loading i64 constants
 334     SDNode *SelectI64Constant(uint64_t i64const, MVT OpVT, DebugLoc dl);
 335
 336     //! Returns true if the address N is an A-form (local store) address
 337     bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
 338                          SDValue &Index);
 339
 340     //! D-form address predicate
 341     bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
 342                          SDValue &Index);
 343
 344     /// Alternate D-form address using i7 offset predicate
 345     bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
 346                           SDValue &Base);
 347
 348     /// D-form address selection workhorse
 349     bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
 350                                SDValue &Base, int minOffset, int maxOffset);
 351
 352     //! Address predicate if N can be expressed as an indexed [r+r] operation.
 353     bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
 354                          SDValue &Index);
 355
 356     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
 357     /// inline asm expressions.
 358     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
 359                                               char ConstraintCode,
 360                                               std::vector<SDValue> &OutOps) {
 361       SDValue Op0, Op1;
 362       switch (ConstraintCode) {
 363       default: return true;
 364       case 'm':   // memory
 365         if (!SelectDFormAddr(Op, Op, Op0, Op1)
 366             && !SelectAFormAddr(Op, Op, Op0, Op1))
 367           SelectXFormAddr(Op, Op, Op0, Op1);
 368         break;
 369       case 'o':   // offsetable
 370         if (!SelectDFormAddr(Op, Op, Op0, Op1)
 371             && !SelectAFormAddr(Op, Op, Op0, Op1)) {
 372           Op0 = Op;
 373           Op1 = getSmallIPtrImm(0);
 374         }
 375         break;
 376       case 'v':   // not offsetable
 377 #if 1
 378         assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
 379 #else
 380         SelectAddrIdxOnly(Op, Op, Op0, Op1);
 381 #endif
 382         break;
 383       }
 384
 385       OutOps.push_back(Op0);
 386       OutOps.push_back(Op1);
 387       return false;
 388     }
 389
 390     /// InstructionSelect - This callback is invoked by
 391     /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 392     virtual void InstructionSelect();
 393
 394     virtual const char *getPassName() const {
 395       return "Cell SPU DAG->DAG Pattern Instruction Selection";
 396     }
 397
 398     /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
 399     /// this target when scheduling the DAG.
 400     virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
 401       const TargetInstrInfo *II = TM.getInstrInfo();
 402       assert(II && "No InstrInfo?");
 403       return new SPUHazardRecognizer(*II);
 404     }
 405
 406     // Include the pieces autogenerated from the target description.
 407 #include "SPUGenDAGISel.inc"
 408   };
 409 }
 410
 411 /// InstructionSelect - This callback is invoked by
 412 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 413 void
 414 SPUDAGToDAGISel::InstructionSelect()
 415 {
 416   DEBUG(BB->dump());
 417
 418   // Select target instructions for the DAG.
 419   SelectRoot(*CurDAG);
 420   CurDAG->RemoveDeadNodes();
 421 }
 422
 423 /*!
 424  \arg Op The ISD instruction operand
 425  \arg N The address to be tested
 426  \arg Base The base address
 427  \arg Index The base address index
 428  */
 429 bool
 430 SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
 431                     SDValue &Index) {
 432   // These match the addr256k operand type:
 433   MVT OffsVT = MVT::i16;
 434   SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
 435
 436   switch (N.getOpcode()) {
 437   case ISD::Constant:
 438   case ISD::ConstantPool:
 439   case ISD::GlobalAddress:
 440     cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
 441     abort();
 442     /*NOTREACHED*/
 443
 444   case ISD::TargetConstant:
 445   case ISD::TargetGlobalAddress:
 446   case ISD::TargetJumpTable:
 447     cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
 448          << "A-form address.\n";
 449     abort();
 450     /*NOTREACHED*/
 451
 452   case SPUISD::AFormAddr:
 453     // Just load from memory if there's only a single use of the location,
 454     // otherwise, this will get handled below with D-form offset addresses
 455     if (N.hasOneUse()) {
 456       SDValue Op0 = N.getOperand(0);
 457       switch (Op0.getOpcode()) {
 458       case ISD::TargetConstantPool:
 459       case ISD::TargetJumpTable:
 460         Base = Op0;
 461         Index = Zero;
 462         return true;
 463
 464       case ISD::TargetGlobalAddress: {
 465         GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
 466         GlobalValue *GV = GSDN->getGlobal();
 467         if (GV->getAlignment() == 16) {
 468           Base = Op0;
 469           Index = Zero;
 470           return true;
 471         }
 472         break;
 473       }
 474       }
 475     }
 476     break;
 477   }
 478   return false;
 479 }
 480
 481 bool
 482 SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
 483                                   SDValue &Base) {
 484   const int minDForm2Offset = -(1 << 7);
 485   const int maxDForm2Offset = (1 << 7) - 1;
 486   return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
 487                                maxDForm2Offset);
 488 }
 489
 490 /*!
 491   \arg Op The ISD instruction (ignored)
 492   \arg N The address to be tested
 493   \arg Base Base address register/pointer
 494   \arg Index Base address index
 495
 496   Examine the input address by a base register plus a signed 10-bit
 497   displacement, [r+I10] (D-form address).
 498
 499   \return true if \a N is a D-form address with \a Base and \a Index set
 500   to non-empty SDValue instances.
 501 */
 502 bool
 503 SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
 504                                  SDValue &Index) {
 505   return DFormAddressPredicate(Op, N, Base, Index,
 506                                SPUFrameInfo::minFrameOffset(),
 507                                SPUFrameInfo::maxFrameOffset());
 508 }
 509
 510 bool
 511 SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
 512                                       SDValue &Index, int minOffset,
 513                                       int maxOffset) {
 514   unsigned Opc = N.getOpcode();
 515   MVT PtrTy = SPUtli.getPointerTy();
 516
 517   if (Opc == ISD::FrameIndex) {
 518     // Stack frame index must be less than 512 (divided by 16):
 519     FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
 520     int FI = int(FIN->getIndex());
 521     DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
 522                << FI << "\n");
 523     if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
 524       Base = CurDAG->getTargetConstant(0, PtrTy);
 525       Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 526       return true;
 527     }
 528   } else if (Opc == ISD::ADD) {
 529     // Generated by getelementptr
 530     const SDValue Op0 = N.getOperand(0);
 531     const SDValue Op1 = N.getOperand(1);
 532
 533     if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
 534         || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
 535       Base = CurDAG->getTargetConstant(0, PtrTy);
 536       Index = N;
 537       return true;
 538     } else if (Op1.getOpcode() == ISD::Constant
 539                || Op1.getOpcode() == ISD::TargetConstant) {
 540       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
 541       int32_t offset = int32_t(CN->getSExtValue());
 542
 543       if (Op0.getOpcode() == ISD::FrameIndex) {
 544         FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
 545         int FI = int(FIN->getIndex());
 546         DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
 547                    << " frame index = " << FI << "\n");
 548
 549         if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
 550           Base = CurDAG->getTargetConstant(offset, PtrTy);
 551           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 552           return true;
 553         }
 554       } else if (offset > minOffset && offset < maxOffset) {
 555         Base = CurDAG->getTargetConstant(offset, PtrTy);
 556         Index = Op0;
 557         return true;
 558       }
 559     } else if (Op0.getOpcode() == ISD::Constant
 560                || Op0.getOpcode() == ISD::TargetConstant) {
 561       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
 562       int32_t offset = int32_t(CN->getSExtValue());
 563
 564       if (Op1.getOpcode() == ISD::FrameIndex) {
 565         FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
 566         int FI = int(FIN->getIndex());
 567         DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
 568                    << " frame index = " << FI << "\n");
 569
 570         if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
 571           Base = CurDAG->getTargetConstant(offset, PtrTy);
 572           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
 573           return true;
 574         }
 575       } else if (offset > minOffset && offset < maxOffset) {
 576         Base = CurDAG->getTargetConstant(offset, PtrTy);
 577         Index = Op1;
 578         return true;
 579       }
 580     }
 581   } else if (Opc == SPUISD::IndirectAddr) {
 582     // Indirect with constant offset -> D-Form address
 583     const SDValue Op0 = N.getOperand(0);
 584     const SDValue Op1 = N.getOperand(1);
 585
 586     if (Op0.getOpcode() == SPUISD::Hi
 587         && Op1.getOpcode() == SPUISD::Lo) {
 588       // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
 589       Base = CurDAG->getTargetConstant(0, PtrTy);
 590       Index = N;
 591       return true;
 592     } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
 593       int32_t offset = 0;
 594       SDValue idxOp;
 595
 596       if (isa<ConstantSDNode>(Op1)) {
 597         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
 598         offset = int32_t(CN->getSExtValue());
 599         idxOp = Op0;
 600       } else if (isa<ConstantSDNode>(Op0)) {
 601         ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
 602         offset = int32_t(CN->getSExtValue());
 603         idxOp = Op1;
 604       }
 605
 606       if (offset >= minOffset && offset <= maxOffset) {
 607         Base = CurDAG->getTargetConstant(offset, PtrTy);
 608         Index = idxOp;
 609         return true;
 610       }
 611     }
 612   } else if (Opc == SPUISD::AFormAddr) {
 613     Base = CurDAG->getTargetConstant(0, N.getValueType());
 614     Index = N;
 615     return true;
 616   } else if (Opc == SPUISD::LDRESULT) {
 617     Base = CurDAG->getTargetConstant(0, N.getValueType());
 618     Index = N;
 619     return true;
 620   } else if (Opc == ISD::Register || Opc == ISD::CopyFromReg) {
 621     unsigned OpOpc = Op.getOpcode();
 622
 623     if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
 624       // Direct load/store without getelementptr
 625       SDValue Addr, Offs;
 626
 627       // Get the register from CopyFromReg
 628       if (Opc == ISD::CopyFromReg)
 629         Addr = N.getOperand(1);
 630       else
 631         Addr = N;                       // Register
 632
 633       Offs = ((OpOpc == ISD::STORE) ? Op.getOperand(3) : Op.getOperand(2));
 634
 635       if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
 636         if (Offs.getOpcode() == ISD::UNDEF)
 637           Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
 638
 639         Base = Offs;
 640         Index = Addr;
 641         return true;
 642       }
 643     } else {
 644       /* If otherwise unadorned, default to D-form address with 0 offset: */
 645       if (Opc == ISD::CopyFromReg) {
 646         Index = N.getOperand(1);
 647       } else {
 648         Index = N;
 649       }
 650
 651       Base = CurDAG->getTargetConstant(0, Index.getValueType());
 652       return true;
 653     }
 654   }
 655
 656   return false;
 657 }
 658
 659 /*!
 660   \arg Op The ISD instruction operand
 661   \arg N The address operand
 662   \arg Base The base pointer operand
 663   \arg Index The offset/index operand
 664
 665   If the address \a N can be expressed as an A-form or D-form address, returns
 666   false.  Otherwise, creates two operands, Base and Index that will become the
 667   (r)(r) X-form address.
 668 */
 669 bool
 670 SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
 671                                  SDValue &Index) {
 672   if (!SelectAFormAddr(Op, N, Base, Index)
 673       && !SelectDFormAddr(Op, N, Base, Index)) {
 674     // If the address is neither A-form or D-form, punt and use an X-form
 675     // address:
 676     Base = N.getOperand(1);
 677     Index = N.getOperand(0);
 678     return true;
 679   }
 680
 681   return false;
 682 }
 683
 684 //! Convert the operand from a target-independent to a target-specific node
 685 /*!
 686  */
 687 SDNode *
 688 SPUDAGToDAGISel::Select(SDValue Op) {
 689   SDNode *N = Op.getNode();
 690   unsigned Opc = N->getOpcode();
 691   int n_ops = -1;
 692   unsigned NewOpc;
 693   MVT OpVT = Op.getValueType();
 694   SDValue Ops[8];
 695   DebugLoc dl = N->getDebugLoc();
 696
 697   if (N->isMachineOpcode()) {
 698     return NULL;   // Already selected.
 699   }
 700
 701   if (Opc == ISD::FrameIndex) {
 702     int FI = cast<FrameIndexSDNode>(N)->getIndex();
 703     SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
 704     SDValue Imm0 = CurDAG->getTargetConstant(0, Op.getValueType());
 705
 706     if (FI < 128) {
 707       NewOpc = SPU::AIr32;
 708       Ops[0] = TFI;
 709       Ops[1] = Imm0;
 710       n_ops = 2;
 711     } else {
 712       NewOpc = SPU::Ar32;
 713       Ops[0] = CurDAG->getRegister(SPU::R1, Op.getValueType());
 714       Ops[1] = SDValue(CurDAG->getTargetNode(SPU::ILAr32, dl, Op.getValueType(),
 715                                              TFI, Imm0), 0);
 716       n_ops = 2;
 717     }
 718   } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
 719     // Catch the i64 constants that end up here. Note: The backend doesn't
 720     // attempt to legalize the constant (it's useless because DAGCombiner
 721     // will insert 64-bit constants and we can't stop it).
 722     return SelectI64Constant(Op, OpVT, Op.getDebugLoc());
 723   } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
 724              && OpVT == MVT::i64) {
 725     SDValue Op0 = Op.getOperand(0);
 726     MVT Op0VT = Op0.getValueType();
 727     MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
 728     MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
 729     SDValue shufMask;
 730
 731     switch (Op0VT.getSimpleVT()) {
 732     default:
 733       cerr << "CellSPU Select: Unhandled zero/any extend MVT\n";
 734       abort();
 735       /*NOTREACHED*/
 736       break;
 737     case MVT::i32:
 738       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 739                                  CurDAG->getConstant(0x80808080, MVT::i32),
 740                                  CurDAG->getConstant(0x00010203, MVT::i32),
 741                                  CurDAG->getConstant(0x80808080, MVT::i32),
 742                                  CurDAG->getConstant(0x08090a0b, MVT::i32));
 743       break;
 744
 745     case MVT::i16:
 746       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 747                                  CurDAG->getConstant(0x80808080, MVT::i32),
 748                                  CurDAG->getConstant(0x80800203, MVT::i32),
 749                                  CurDAG->getConstant(0x80808080, MVT::i32),
 750                                  CurDAG->getConstant(0x80800a0b, MVT::i32));
 751       break;
 752
 753     case MVT::i8:
 754       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
 755                                  CurDAG->getConstant(0x80808080, MVT::i32),
 756                                  CurDAG->getConstant(0x80808003, MVT::i32),
 757                                  CurDAG->getConstant(0x80808080, MVT::i32),
 758                                  CurDAG->getConstant(0x8080800b, MVT::i32));
 759       break;
 760     }
 761
 762     SDNode *shufMaskLoad = emitBuildVector(shufMask);
 763     SDNode *PromoteScalar =
 764             SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl, Op0VecVT, Op0));
 765
 766     SDValue zextShuffle =
 767             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
 768                             SDValue(PromoteScalar, 0),
 769                             SDValue(PromoteScalar, 0),
 770                             SDValue(shufMaskLoad, 0));
 771
 772     // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
 773     // re-use it in the VEC2PREFSLOT selection without needing to explicitly
 774     // call SelectCode (it's already done for us.)
 775     SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
 776     return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
 777                                       zextShuffle));
 778   } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 779     SDNode *CGLoad =
 780             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
 781
 782     return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
 783                                       Op.getOperand(0), Op.getOperand(1),
 784                                       SDValue(CGLoad, 0)));
 785   } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 786     SDNode *CGLoad =
 787             emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl));
 788
 789     return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
 790                                       Op.getOperand(0), Op.getOperand(1),
 791                                       SDValue(CGLoad, 0)));
 792   } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
 793     SDNode *CGLoad =
 794             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
 795
 796     return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
 797                                       Op.getOperand(0), Op.getOperand(1),
 798                                       SDValue(CGLoad, 0)));
 799   } else if (Opc == ISD::TRUNCATE) {
 800     SDValue Op0 = Op.getOperand(0);
 801     if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
 802         && OpVT == MVT::i32
 803         && Op0.getValueType() == MVT::i64) {
 804       // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
 805       //
 806       // Take advantage of the fact that the upper 32 bits are in the
 807       // i32 preferred slot and avoid shuffle gymnastics:
 808       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
 809       if (CN != 0) {
 810         unsigned shift_amt = unsigned(CN->getZExtValue());
 811
 812         if (shift_amt >= 32) {
 813           SDNode *hi32 =
 814                   CurDAG->getTargetNode(SPU::ORr32_r64, dl, OpVT,
 815                                         Op0.getOperand(0));
 816
 817           shift_amt -= 32;
 818           if (shift_amt > 0) {
 819             // Take care of the additional shift, if present:
 820             SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
 821             unsigned Opc = SPU::ROTMAIr32_i32;
 822
 823             if (Op0.getOpcode() == ISD::SRL)
 824               Opc = SPU::ROTMr32;
 825
 826             hi32 = CurDAG->getTargetNode(Opc, dl, OpVT, SDValue(hi32, 0),
 827                                          shift);
 828           }
 829
 830           return hi32;
 831         }
 832       }
 833     }
 834   } else if (Opc == ISD::SHL) {
 835     if (OpVT == MVT::i64) {
 836       return SelectSHLi64(Op, OpVT);
 837     }
 838   } else if (Opc == ISD::SRL) {
 839     if (OpVT == MVT::i64) {
 840       return SelectSRLi64(Op, OpVT);
 841     }
 842   } else if (Opc == ISD::SRA) {
 843     if (OpVT == MVT::i64) {
 844       return SelectSRAi64(Op, OpVT);
 845     }
 846   } else if (Opc == ISD::FNEG
 847              && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
 848     DebugLoc dl = Op.getDebugLoc();
 849     // Check if the pattern is a special form of DFNMS:
 850     // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
 851     SDValue Op0 = Op.getOperand(0);
 852     if (Op0.getOpcode() == ISD::FSUB) {
 853       SDValue Op00 = Op0.getOperand(0);
 854       if (Op00.getOpcode() == ISD::FMUL) {
 855         unsigned Opc = SPU::DFNMSf64;
 856         if (OpVT == MVT::v2f64)
 857           Opc = SPU::DFNMSv2f64;
 858
 859         return CurDAG->getTargetNode(Opc, dl, OpVT,
 860                                      Op00.getOperand(0),
 861                                      Op00.getOperand(1),
 862                                      Op0.getOperand(1));
 863       }
 864     }
 865
 866     SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
 867     SDNode *signMask = 0;
 868     unsigned Opc = SPU::XORfneg64;
 869
 870     if (OpVT == MVT::f64) {
 871       signMask = SelectI64Constant(negConst, MVT::i64, dl);
 872     } else if (OpVT == MVT::v2f64) {
 873       Opc = SPU::XORfnegvec;
 874       signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
 875                                                  MVT::v2i64,
 876                                                  negConst, negConst));
 877     }
 878
 879     return CurDAG->getTargetNode(Opc, dl, OpVT,
 880                                  Op.getOperand(0), SDValue(signMask, 0));
 881   } else if (Opc == ISD::FABS) {
 882     if (OpVT == MVT::f64) {
 883       SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
 884       return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT,
 885                                    Op.getOperand(0), SDValue(signMask, 0));
 886     } else if (OpVT == MVT::v2f64) {
 887       SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
 888       SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
 889                                        absConst, absConst);
 890       SDNode *signMask = emitBuildVector(absVec);
 891       return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT,
 892                                    Op.getOperand(0), SDValue(signMask, 0));
 893     }
 894   } else if (Opc == SPUISD::LDRESULT) {
 895     // Custom select instructions for LDRESULT
 896     MVT VT = N->getValueType(0);
 897     SDValue Arg = N->getOperand(0);
 898     SDValue Chain = N->getOperand(1);
 899     SDNode *Result;
 900     const valtype_map_s *vtm = getValueTypeMapEntry(VT);
 901
 902     if (vtm->ldresult_ins == 0) {
 903       cerr << "LDRESULT for unsupported type: "
 904            << VT.getMVTString()
 905            << "\n";
 906       abort();
 907     }
 908
 909     Opc = vtm->ldresult_ins;
 910     if (vtm->ldresult_imm) {
 911       SDValue Zero = CurDAG->getTargetConstant(0, VT);
 912
 913       Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
 914     } else {
 915       Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
 916     }
 917
 918     return Result;
 919   } else if (Opc == SPUISD::IndirectAddr) {
 920     // Look at the operands: SelectCode() will catch the cases that aren't
 921     // specifically handled here.
 922     //
 923     // SPUInstrInfo catches the following patterns:
 924     // (SPUindirect (SPUhi ...), (SPUlo ...))
 925     // (SPUindirect $sp, imm)
 926     MVT VT = Op.getValueType();
 927     SDValue Op0 = N->getOperand(0);
 928     SDValue Op1 = N->getOperand(1);
 929     RegisterSDNode *RN;
 930
 931     if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
 932         || (Op0.getOpcode() == ISD::Register
 933             && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
 934                 && RN->getReg() != SPU::R1))) {
 935       NewOpc = SPU::Ar32;
 936       if (Op1.getOpcode() == ISD::Constant) {
 937         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
 938         Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
 939         NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
 940       }
 941       Ops[0] = Op0;
 942       Ops[1] = Op1;
 943       n_ops = 2;
 944     }
 945   }
 946
 947   if (n_ops > 0) {
 948     if (N->hasOneUse())
 949       return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
 950     else
 951       return CurDAG->getTargetNode(NewOpc, dl, OpVT, Ops, n_ops);
 952   } else
 953     return SelectCode(Op);
 954 }
 955
 956 /*!
 957  * Emit the instruction sequence for i64 left shifts. The basic algorithm
 958  * is to fill the bottom two word slots with zeros so that zeros are shifted
 959  * in as the entire quadword is shifted left.
 960  *
 961  * \note This code could also be used to implement v2i64 shl.
 962  *
 963  * @param Op The shl operand
 964  * @param OpVT Op's machine value value type (doesn't need to be passed, but
 965  * makes life easier.)
 966  * @return The SDNode with the entire instruction sequence
 967  */
 968 SDNode *
 969 SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
 970   SDValue Op0 = Op.getOperand(0);
 971   MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
 972   SDValue ShiftAmt = Op.getOperand(1);
 973   MVT ShiftAmtVT = ShiftAmt.getValueType();
 974   SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
 975   SDValue SelMaskVal;
 976   DebugLoc dl = Op.getDebugLoc();
 977
 978   VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
 979   SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
 980   SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
 981   ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
 982                                    CurDAG->getTargetConstant(0, OpVT));
 983   VecOp0 = CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
 984                                  SDValue(ZeroFill, 0),
 985                                  SDValue(VecOp0, 0),
 986                                  SDValue(SelMask, 0));
 987
 988   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
 989     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
 990     unsigned bits = unsigned(CN->getZExtValue()) & 7;
 991
 992     if (bytes > 0) {
 993       Shift =
 994         CurDAG->getTargetNode(SPU::SHLQBYIv2i64, dl, VecVT,
 995                               SDValue(VecOp0, 0),
 996                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
 997     }
 998
 999     if (bits > 0) {
1000       Shift =
1001         CurDAG->getTargetNode(SPU::SHLQBIIv2i64, dl, VecVT,
1002                               SDValue((Shift != 0 ? Shift : VecOp0), 0),
1003                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1004     }
1005   } else {
1006     SDNode *Bytes =
1007       CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1008                             ShiftAmt,
1009                             CurDAG->getTargetConstant(3, ShiftAmtVT));
1010     SDNode *Bits =
1011       CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
1012                             ShiftAmt,
1013                             CurDAG->getTargetConstant(7, ShiftAmtVT));
1014     Shift =
1015       CurDAG->getTargetNode(SPU::SHLQBYv2i64, dl, VecVT,
1016                             SDValue(VecOp0, 0), SDValue(Bytes, 0));
1017     Shift =
1018       CurDAG->getTargetNode(SPU::SHLQBIv2i64, dl, VecVT,
1019                             SDValue(Shift, 0), SDValue(Bits, 0));
1020   }
1021
1022   return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1023 }
1024
1025 /*!
1026  * Emit the instruction sequence for i64 logical right shifts.
1027  *
1028  * @param Op The shl operand
1029  * @param OpVT Op's machine value value type (doesn't need to be passed, but
1030  * makes life easier.)
1031  * @return The SDNode with the entire instruction sequence
1032  */
1033 SDNode *
1034 SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
1035   SDValue Op0 = Op.getOperand(0);
1036   MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1037   SDValue ShiftAmt = Op.getOperand(1);
1038   MVT ShiftAmtVT = ShiftAmt.getValueType();
1039   SDNode *VecOp0, *Shift = 0;
1040   DebugLoc dl = Op.getDebugLoc();
1041
1042   VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
1043
1044   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1045     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1046     unsigned bits = unsigned(CN->getZExtValue()) & 7;
1047
1048     if (bytes > 0) {
1049       Shift =
1050         CurDAG->getTargetNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1051                               SDValue(VecOp0, 0),
1052                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1053     }
1054
1055     if (bits > 0) {
1056       Shift =
1057         CurDAG->getTargetNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1058                               SDValue((Shift != 0 ? Shift : VecOp0), 0),
1059                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1060     }
1061   } else {
1062     SDNode *Bytes =
1063       CurDAG->getTargetNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1064                             ShiftAmt,
1065                             CurDAG->getTargetConstant(3, ShiftAmtVT));
1066     SDNode *Bits =
1067       CurDAG->getTargetNode(SPU::ANDIr32, dl, ShiftAmtVT,
1068                             ShiftAmt,
1069                             CurDAG->getTargetConstant(7, ShiftAmtVT));
1070
1071     // Ensure that the shift amounts are negated!
1072     Bytes = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1073                                   SDValue(Bytes, 0),
1074                                   CurDAG->getTargetConstant(0, ShiftAmtVT));
1075
1076     Bits = CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1077                                  SDValue(Bits, 0),
1078                                  CurDAG->getTargetConstant(0, ShiftAmtVT));
1079
1080     Shift =
1081       CurDAG->getTargetNode(SPU::ROTQMBYv2i64, dl, VecVT,
1082                             SDValue(VecOp0, 0), SDValue(Bytes, 0));
1083     Shift =
1084       CurDAG->getTargetNode(SPU::ROTQMBIv2i64, dl, VecVT,
1085                             SDValue(Shift, 0), SDValue(Bits, 0));
1086   }
1087
1088   return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1089 }
1090
1091 /*!
1092  * Emit the instruction sequence for i64 arithmetic right shifts.
1093  *
1094  * @param Op The shl operand
1095  * @param OpVT Op's machine value value type (doesn't need to be passed, but
1096  * makes life easier.)
1097  * @return The SDNode with the entire instruction sequence
1098  */
1099 SDNode *
1100 SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
1101   // Promote Op0 to vector
1102   MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
1103   SDValue ShiftAmt = Op.getOperand(1);
1104   MVT ShiftAmtVT = ShiftAmt.getValueType();
1105   DebugLoc dl = Op.getDebugLoc();
1106
1107   SDNode *VecOp0 =
1108     CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op.getOperand(0));
1109
1110   SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1111   SDNode *SignRot =
1112     CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1113                           SDValue(VecOp0, 0), SignRotAmt);
1114   SDNode *UpperHalfSign =
1115     CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
1116
1117   SDNode *UpperHalfSignMask =
1118     CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1119   SDNode *UpperLowerMask =
1120     CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
1121                           CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1122   SDNode *UpperLowerSelect =
1123     CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
1124                           SDValue(UpperHalfSignMask, 0),
1125                           SDValue(VecOp0, 0),
1126                           SDValue(UpperLowerMask, 0));
1127
1128   SDNode *Shift = 0;
1129
1130   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1131     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1132     unsigned bits = unsigned(CN->getZExtValue()) & 7;
1133
1134     if (bytes > 0) {
1135       bytes = 31 - bytes;
1136       Shift =
1137         CurDAG->getTargetNode(SPU::ROTQBYIv2i64, dl, VecVT,
1138                               SDValue(UpperLowerSelect, 0),
1139                               CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1140     }
1141
1142     if (bits > 0) {
1143       bits = 8 - bits;
1144       Shift =
1145         CurDAG->getTargetNode(SPU::ROTQBIIv2i64, dl, VecVT,
1146                               SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1147                               CurDAG->getTargetConstant(bits, ShiftAmtVT));
1148     }
1149   } else {
1150     SDNode *NegShift =
1151       CurDAG->getTargetNode(SPU::SFIr32, dl, ShiftAmtVT,
1152                             ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1153
1154     Shift =
1155       CurDAG->getTargetNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1156                             SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1157     Shift =
1158       CurDAG->getTargetNode(SPU::ROTQBIv2i64, dl, VecVT,
1159                             SDValue(Shift, 0), SDValue(NegShift, 0));
1160   }
1161
1162   return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT, SDValue(Shift, 0));
1163 }
1164
1165 /*!
1166  Do the necessary magic necessary to load a i64 constant
1167  */
1168 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT,
1169                                            DebugLoc dl) {
1170   ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
1171   return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1172 }
1173
1174 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, MVT OpVT,
1175                                            DebugLoc dl) {
1176   MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
1177   SDValue i64vec =
1178           SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1179
1180   // Here's where it gets interesting, because we have to parse out the
1181   // subtree handed back in i64vec:
1182
1183   if (i64vec.getOpcode() == ISD::BIT_CONVERT) {
1184     // The degenerate case where the upper and lower bits in the splat are
1185     // identical:
1186     SDValue Op0 = i64vec.getOperand(0);
1187
1188     ReplaceUses(i64vec, Op0);
1189     return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1190                                  SDValue(emitBuildVector(Op0), 0));
1191   } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1192     SDValue lhs = i64vec.getOperand(0);
1193     SDValue rhs = i64vec.getOperand(1);
1194     SDValue shufmask = i64vec.getOperand(2);
1195
1196     if (lhs.getOpcode() == ISD::BIT_CONVERT) {
1197       ReplaceUses(lhs, lhs.getOperand(0));
1198       lhs = lhs.getOperand(0);
1199     }
1200
1201     SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1202                        ? lhs.getNode()
1203                        : emitBuildVector(lhs));
1204
1205     if (rhs.getOpcode() == ISD::BIT_CONVERT) {
1206       ReplaceUses(rhs, rhs.getOperand(0));
1207       rhs = rhs.getOperand(0);
1208     }
1209
1210     SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1211                        ? rhs.getNode()
1212                        : emitBuildVector(rhs));
1213
1214     if (shufmask.getOpcode() == ISD::BIT_CONVERT) {
1215       ReplaceUses(shufmask, shufmask.getOperand(0));
1216       shufmask = shufmask.getOperand(0);
1217     }
1218
1219     SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1220                             ? shufmask.getNode()
1221                             : emitBuildVector(shufmask));
1222
1223     SDNode *shufNode =
1224             Select(CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1225                                    SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1226                                    SDValue(shufMaskNode, 0)));
1227
1228     return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1229                                  SDValue(shufNode, 0));
1230   } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1231     return CurDAG->getTargetNode(SPU::ORi64_v2i64, dl, OpVT,
1232                                  SDValue(emitBuildVector(i64vec), 0));
1233   } else {
1234     cerr << "SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec condition\n";
1235     abort();
1236   }
1237 }
1238
1239 /// createSPUISelDag - This pass converts a legalized DAG into a
1240 /// SPU-specific DAG, ready for instruction scheduling.
1241 ///
1242 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1243   return new SPUDAGToDAGISel(TM);
1244 }