lib/Target/Mips/MipsInstrInfo.cpp

   1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Mips implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "MipsInstrInfo.h"
  15 #include "MipsTargetMachine.h"
  16 #include "llvm/ADT/STLExtras.h"
  17 #include "llvm/CodeGen/MachineInstrBuilder.h"
  18 #include "MipsGenInstrInfo.inc"
  19
  20 using namespace llvm;
  21
  22 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
  23   : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
  24     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
  25
  26 static bool isZeroImm(const MachineOperand &op) {
  27   return op.isImm() && op.getImm() == 0;
  28 }
  29
  30 /// Return true if the instruction is a register to register move and
  31 /// leave the source and dest operands in the passed parameters.
  32 bool MipsInstrInfo::
  33 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
  34             unsigned &SrcSubIdx, unsigned &DstSubIdx) const
  35 {
  36   SrcSubIdx = DstSubIdx = 0; // No sub-registers.
  37
  38   //  addu  $dst, $src, $zero || addu  $dst, $zero, $src
  39   //  or    $dst, $src, $zero || or    $dst, $zero, $src
  40   if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
  41     if (MI.getOperand(1).getReg() == Mips::ZERO) {
  42       DstReg = MI.getOperand(0).getReg();
  43       SrcReg = MI.getOperand(2).getReg();
  44       return true;
  45     } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
  46       DstReg = MI.getOperand(0).getReg();
  47       SrcReg = MI.getOperand(1).getReg();
  48       return true;
  49     }
  50   }
  51
  52   // mov $fpDst, $fpSrc
  53   // mfc $gpDst, $fpSrc
  54   // mtc $fpDst, $gpSrc
  55   if (MI.getOpcode() == Mips::FMOV_SO32 || MI.getOpcode() == Mips::FMOV_AS32 ||
  56       MI.getOpcode() == Mips::FMOV_D32 || MI.getOpcode() == Mips::MFC1A ||
  57       MI.getOpcode() == Mips::MFC1 || MI.getOpcode() == Mips::MTC1A ||
  58       MI.getOpcode() == Mips::MTC1 ) {
  59     DstReg = MI.getOperand(0).getReg();
  60     SrcReg = MI.getOperand(1).getReg();
  61     return true;
  62   }
  63
  64   //  addiu $dst, $src, 0
  65   if (MI.getOpcode() == Mips::ADDiu) {
  66     if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
  67       DstReg = MI.getOperand(0).getReg();
  68       SrcReg = MI.getOperand(1).getReg();
  69       return true;
  70     }
  71   }
  72   return false;
  73 }
  74
  75 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  76 /// load from a stack slot, return the virtual or physical register number of
  77 /// the destination along with the FrameIndex of the loaded stack slot.  If
  78 /// not, return 0.  This predicate must return 0 if the instruction has
  79 /// any side effects other than loading from the stack slot.
  80 unsigned MipsInstrInfo::
  81 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
  82 {
  83   if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
  84       (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) {
  85     if ((MI->getOperand(2).isFI()) && // is a stack slot
  86         (MI->getOperand(1).isImm()) &&  // the imm is zero
  87         (isZeroImm(MI->getOperand(1)))) {
  88       FrameIndex = MI->getOperand(2).getIndex();
  89       return MI->getOperand(0).getReg();
  90     }
  91   }
  92
  93   return 0;
  94 }
  95
  96 /// isStoreToStackSlot - If the specified machine instruction is a direct
  97 /// store to a stack slot, return the virtual or physical register number of
  98 /// the source reg along with the FrameIndex of the loaded stack slot.  If
  99 /// not, return 0.  This predicate must return 0 if the instruction has
 100 /// any side effects other than storing to the stack slot.
 101 unsigned MipsInstrInfo::
 102 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
 103 {
 104   if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
 105       (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) {
 106     if ((MI->getOperand(2).isFI()) && // is a stack slot
 107         (MI->getOperand(1).isImm()) &&  // the imm is zero
 108         (isZeroImm(MI->getOperand(1)))) {
 109       FrameIndex = MI->getOperand(2).getIndex();
 110       return MI->getOperand(0).getReg();
 111     }
 112   }
 113   return 0;
 114 }
 115
 116 /// insertNoop - If data hazard condition is found insert the target nop
 117 /// instruction.
 118 void MipsInstrInfo::
 119 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
 120 {
 121   DebugLoc DL = DebugLoc::getUnknownLoc();
 122   if (MI != MBB.end()) DL = MI->getDebugLoc();
 123   BuildMI(MBB, MI, DL, get(Mips::NOP));
 124 }
 125
 126 bool MipsInstrInfo::
 127 copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 128              unsigned DestReg, unsigned SrcReg,
 129              const TargetRegisterClass *DestRC,
 130              const TargetRegisterClass *SrcRC) const {
 131   DebugLoc DL = DebugLoc::getUnknownLoc();
 132   if (I != MBB.end()) DL = I->getDebugLoc();
 133
 134   if (DestRC != SrcRC) {
 135     if ((DestRC == Mips::CPURegsRegisterClass) &&
 136         (SrcRC == Mips::FGR32RegisterClass))
 137       BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
 138     else if ((DestRC == Mips::CPURegsRegisterClass) &&
 139              (SrcRC == Mips::AFGR32RegisterClass))
 140       BuildMI(MBB, I, DL, get(Mips::MFC1A), DestReg).addReg(SrcReg);
 141     else if ((DestRC == Mips::FGR32RegisterClass) &&
 142              (SrcRC == Mips::CPURegsRegisterClass))
 143       BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
 144     else if ((DestRC == Mips::AFGR32RegisterClass) &&
 145              (SrcRC == Mips::CPURegsRegisterClass))
 146       BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
 147     else if ((DestRC == Mips::AFGR32RegisterClass) &&
 148              (SrcRC == Mips::CPURegsRegisterClass))
 149       BuildMI(MBB, I, DL, get(Mips::MTC1A), DestReg).addReg(SrcReg);
 150     else if ((SrcRC == Mips::CCRRegisterClass) &&
 151              (SrcReg == Mips::FCR31))
 152       return true; // This register is used implicitly, no copy needed.
 153     else if ((DestRC == Mips::CCRRegisterClass) &&
 154              (DestReg == Mips::FCR31))
 155       return true; // This register is used implicitly, no copy needed.
 156     else if ((DestRC == Mips::HILORegisterClass) &&
 157              (SrcRC == Mips::CPURegsRegisterClass)) {
 158       unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
 159       BuildMI(MBB, I, DL, get(Opc), DestReg);
 160     } else if ((SrcRC == Mips::HILORegisterClass) &&
 161                (DestRC == Mips::CPURegsRegisterClass)) {
 162       unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
 163       BuildMI(MBB, I, DL, get(Opc), DestReg);
 164     } else
 165       // DestRC != SrcRC, Can't copy this register
 166       return false;
 167
 168     return true;
 169   }
 170
 171   if (DestRC == Mips::CPURegsRegisterClass)
 172     BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
 173       .addReg(SrcReg);
 174   else if (DestRC == Mips::FGR32RegisterClass)
 175     BuildMI(MBB, I, DL, get(Mips::FMOV_SO32), DestReg).addReg(SrcReg);
 176   else if (DestRC == Mips::AFGR32RegisterClass)
 177     BuildMI(MBB, I, DL, get(Mips::FMOV_AS32), DestReg).addReg(SrcReg);
 178   else if (DestRC == Mips::AFGR64RegisterClass)
 179     BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
 180   else
 181     // Can't copy this register
 182     return false;
 183
 184   return true;
 185 }
 186
 187 void MipsInstrInfo::
 188 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 189                     unsigned SrcReg, bool isKill, int FI,
 190                     const TargetRegisterClass *RC) const
 191 {
 192   unsigned Opc;
 193
 194   DebugLoc DL = DebugLoc::getUnknownLoc();
 195   if (I != MBB.end()) DL = I->getDebugLoc();
 196
 197   if (RC == Mips::CPURegsRegisterClass)
 198     Opc = Mips::SW;
 199   else if (RC == Mips::FGR32RegisterClass)
 200     Opc = Mips::SWC1;
 201   else if (RC == Mips::AFGR32RegisterClass)
 202     Opc = Mips::SWC1A;
 203   else if (RC == Mips::AFGR64RegisterClass)
 204     Opc = Mips::SDC1;
 205   else
 206     assert(0 && "Can't store this register to stack slot");
 207
 208   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill)
 209           .addImm(0).addFrameIndex(FI);
 210 }
 211
 212 void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
 213   bool isKill, SmallVectorImpl<MachineOperand> &Addr,
 214   const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
 215 {
 216   unsigned Opc;
 217   if (RC == Mips::CPURegsRegisterClass)
 218     Opc = Mips::SW;
 219   else if (RC == Mips::FGR32RegisterClass)
 220     Opc = Mips::SWC1;
 221   else if (RC == Mips::AFGR32RegisterClass)
 222     Opc = Mips::SWC1A;
 223   else if (RC == Mips::AFGR64RegisterClass)
 224     Opc = Mips::SDC1;
 225   else
 226     assert(0 && "Can't store this register");
 227
 228   DebugLoc DL = DebugLoc::getUnknownLoc();
 229   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
 230     .addReg(SrcReg, false, false, isKill);
 231   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
 232     MIB.addOperand(Addr[i]);
 233   NewMIs.push_back(MIB);
 234   return;
 235 }
 236
 237 void MipsInstrInfo::
 238 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 239                      unsigned DestReg, int FI,
 240                      const TargetRegisterClass *RC) const
 241 {
 242   unsigned Opc;
 243   if (RC == Mips::CPURegsRegisterClass)
 244     Opc = Mips::LW;
 245   else if (RC == Mips::FGR32RegisterClass)
 246     Opc = Mips::LWC1;
 247   else if (RC == Mips::AFGR32RegisterClass)
 248     Opc = Mips::LWC1A;
 249   else if (RC == Mips::AFGR64RegisterClass)
 250     Opc = Mips::LDC1;
 251   else
 252     assert(0 && "Can't load this register from stack slot");
 253
 254   DebugLoc DL = DebugLoc::getUnknownLoc();
 255   if (I != MBB.end()) DL = I->getDebugLoc();
 256   BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
 257 }
 258
 259 void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 260                                     SmallVectorImpl<MachineOperand> &Addr,
 261                                     const TargetRegisterClass *RC,
 262                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
 263   unsigned Opc;
 264   if (RC == Mips::CPURegsRegisterClass)
 265     Opc = Mips::LW;
 266   else if (RC == Mips::FGR32RegisterClass)
 267     Opc = Mips::LWC1;
 268   else if (RC == Mips::AFGR32RegisterClass)
 269     Opc = Mips::LWC1A;
 270   else if (RC == Mips::AFGR64RegisterClass)
 271     Opc = Mips::LDC1;
 272   else
 273     assert(0 && "Can't load this register");
 274
 275   DebugLoc DL = DebugLoc::getUnknownLoc();
 276   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
 277   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
 278     MIB.addOperand(Addr[i]);
 279   NewMIs.push_back(MIB);
 280   return;
 281 }
 282
 283 MachineInstr *MipsInstrInfo::
 284 foldMemoryOperandImpl(MachineFunction &MF,
 285                       MachineInstr* MI,
 286                       const SmallVectorImpl<unsigned> &Ops, int FI) const
 287 {
 288   if (Ops.size() != 1) return NULL;
 289
 290   MachineInstr *NewMI = NULL;
 291
 292   switch (MI->getOpcode()) {
 293   case Mips::ADDu:
 294     if ((MI->getOperand(0).isReg()) &&
 295         (MI->getOperand(1).isReg()) &&
 296         (MI->getOperand(1).getReg() == Mips::ZERO) &&
 297         (MI->getOperand(2).isReg())) {
 298       if (Ops[0] == 0) {    // COPY -> STORE
 299         unsigned SrcReg = MI->getOperand(2).getReg();
 300         bool isKill = MI->getOperand(2).isKill();
 301         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
 302           .addReg(SrcReg, false, false, isKill)
 303           .addImm(0).addFrameIndex(FI);
 304       } else {              // COPY -> LOAD
 305         unsigned DstReg = MI->getOperand(0).getReg();
 306         bool isDead = MI->getOperand(0).isDead();
 307         NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
 308           .addReg(DstReg, true, false, false, isDead)
 309           .addImm(0).addFrameIndex(FI);
 310       }
 311     }
 312     break;
 313   case Mips::FMOV_SO32:
 314   case Mips::FMOV_AS32:
 315   case Mips::FMOV_D32:
 316     if ((MI->getOperand(0).isReg()) &&
 317         (MI->getOperand(1).isReg())) {
 318       const TargetRegisterClass
 319         *RC = RI.getRegClass(MI->getOperand(0).getReg());
 320       unsigned StoreOpc, LoadOpc;
 321
 322       if (RC == Mips::FGR32RegisterClass) {
 323         LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
 324       } else if (RC == Mips::AFGR32RegisterClass) {
 325         LoadOpc = Mips::LWC1A; StoreOpc = Mips::SWC1A;
 326       } else if (RC == Mips::AFGR64RegisterClass) {
 327         LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
 328       } else
 329         assert(0 && "foldMemoryOperandImpl register unknown");
 330
 331       if (Ops[0] == 0) {    // COPY -> STORE
 332         unsigned SrcReg = MI->getOperand(1).getReg();
 333         bool isKill = MI->getOperand(1).isKill();
 334         NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
 335           .addReg(SrcReg, false, false, isKill)
 336           .addImm(0).addFrameIndex(FI) ;
 337       } else {              // COPY -> LOAD
 338         unsigned DstReg = MI->getOperand(0).getReg();
 339         bool isDead = MI->getOperand(0).isDead();
 340         NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
 341           .addReg(DstReg, true, false, false, isDead)
 342           .addImm(0).addFrameIndex(FI);
 343       }
 344     }
 345     break;
 346   }
 347
 348   return NewMI;
 349 }
 350
 351 //===----------------------------------------------------------------------===//
 352 // Branch Analysis
 353 //===----------------------------------------------------------------------===//
 354
 355 /// GetCondFromBranchOpc - Return the Mips CC that matches
 356 /// the correspondent Branch instruction opcode.
 357 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
 358 {
 359   switch (BrOpc) {
 360   default: return Mips::COND_INVALID;
 361   case Mips::BEQ  : return Mips::COND_E;
 362   case Mips::BNE  : return Mips::COND_NE;
 363   case Mips::BGTZ : return Mips::COND_GZ;
 364   case Mips::BGEZ : return Mips::COND_GEZ;
 365   case Mips::BLTZ : return Mips::COND_LZ;
 366   case Mips::BLEZ : return Mips::COND_LEZ;
 367
 368   // We dont do fp branch analysis yet!
 369   case Mips::BC1T :
 370   case Mips::BC1F : return Mips::COND_INVALID;
 371   }
 372 }
 373
 374 /// GetCondBranchFromCond - Return the Branch instruction
 375 /// opcode that matches the cc.
 376 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
 377 {
 378   switch (CC) {
 379   default: assert(0 && "Illegal condition code!");
 380   case Mips::COND_E   : return Mips::BEQ;
 381   case Mips::COND_NE  : return Mips::BNE;
 382   case Mips::COND_GZ  : return Mips::BGTZ;
 383   case Mips::COND_GEZ : return Mips::BGEZ;
 384   case Mips::COND_LZ  : return Mips::BLTZ;
 385   case Mips::COND_LEZ : return Mips::BLEZ;
 386
 387   case Mips::FCOND_F:
 388   case Mips::FCOND_UN:
 389   case Mips::FCOND_EQ:
 390   case Mips::FCOND_UEQ:
 391   case Mips::FCOND_OLT:
 392   case Mips::FCOND_ULT:
 393   case Mips::FCOND_OLE:
 394   case Mips::FCOND_ULE:
 395   case Mips::FCOND_SF:
 396   case Mips::FCOND_NGLE:
 397   case Mips::FCOND_SEQ:
 398   case Mips::FCOND_NGL:
 399   case Mips::FCOND_LT:
 400   case Mips::FCOND_NGE:
 401   case Mips::FCOND_LE:
 402   case Mips::FCOND_NGT: return Mips::BC1T;
 403
 404   case Mips::FCOND_T:
 405   case Mips::FCOND_OR:
 406   case Mips::FCOND_NEQ:
 407   case Mips::FCOND_OGL:
 408   case Mips::FCOND_UGE:
 409   case Mips::FCOND_OGE:
 410   case Mips::FCOND_UGT:
 411   case Mips::FCOND_OGT:
 412   case Mips::FCOND_ST:
 413   case Mips::FCOND_GLE:
 414   case Mips::FCOND_SNE:
 415   case Mips::FCOND_GL:
 416   case Mips::FCOND_NLT:
 417   case Mips::FCOND_GE:
 418   case Mips::FCOND_NLE:
 419   case Mips::FCOND_GT: return Mips::BC1F;
 420   }
 421 }
 422
 423 /// GetOppositeBranchCondition - Return the inverse of the specified
 424 /// condition, e.g. turning COND_E to COND_NE.
 425 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
 426 {
 427   switch (CC) {
 428   default: assert(0 && "Illegal condition code!");
 429   case Mips::COND_E   : return Mips::COND_NE;
 430   case Mips::COND_NE  : return Mips::COND_E;
 431   case Mips::COND_GZ  : return Mips::COND_LEZ;
 432   case Mips::COND_GEZ : return Mips::COND_LZ;
 433   case Mips::COND_LZ  : return Mips::COND_GEZ;
 434   case Mips::COND_LEZ : return Mips::COND_GZ;
 435   case Mips::FCOND_F  : return Mips::FCOND_T;
 436   case Mips::FCOND_UN : return Mips::FCOND_OR;
 437   case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
 438   case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
 439   case Mips::FCOND_OLT: return Mips::FCOND_UGE;
 440   case Mips::FCOND_ULT: return Mips::FCOND_OGE;
 441   case Mips::FCOND_OLE: return Mips::FCOND_UGT;
 442   case Mips::FCOND_ULE: return Mips::FCOND_OGT;
 443   case Mips::FCOND_SF:  return Mips::FCOND_ST;
 444   case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
 445   case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
 446   case Mips::FCOND_NGL: return Mips::FCOND_GL;
 447   case Mips::FCOND_LT:  return Mips::FCOND_NLT;
 448   case Mips::FCOND_NGE: return Mips::FCOND_GE;
 449   case Mips::FCOND_LE:  return Mips::FCOND_NLE;
 450   case Mips::FCOND_NGT: return Mips::FCOND_GT;
 451   }
 452 }
 453
 454 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
 455                                   MachineBasicBlock *&TBB,
 456                                   MachineBasicBlock *&FBB,
 457                                   SmallVectorImpl<MachineOperand> &Cond,
 458                                   bool AllowModify) const
 459 {
 460   // If the block has no terminators, it just falls into the block after it.
 461   MachineBasicBlock::iterator I = MBB.end();
 462   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
 463     return false;
 464
 465   // Get the last instruction in the block.
 466   MachineInstr *LastInst = I;
 467
 468   // If there is only one terminator instruction, process it.
 469   unsigned LastOpc = LastInst->getOpcode();
 470   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
 471     if (!LastInst->getDesc().isBranch())
 472       return true;
 473
 474     // Unconditional branch
 475     if (LastOpc == Mips::J) {
 476       TBB = LastInst->getOperand(0).getMBB();
 477       return false;
 478     }
 479
 480     Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
 481     if (BranchCode == Mips::COND_INVALID)
 482       return true;  // Can't handle indirect branch.
 483
 484     // Conditional branch
 485     // Block ends with fall-through condbranch.
 486     if (LastOpc != Mips::COND_INVALID) {
 487       int LastNumOp = LastInst->getNumOperands();
 488
 489       TBB = LastInst->getOperand(LastNumOp-1).getMBB();
 490       Cond.push_back(MachineOperand::CreateImm(BranchCode));
 491
 492       for (int i=0; i<LastNumOp-1; i++) {
 493         Cond.push_back(LastInst->getOperand(i));
 494       }
 495
 496       return false;
 497     }
 498   }
 499
 500   // Get the instruction before it if it is a terminator.
 501   MachineInstr *SecondLastInst = I;
 502
 503   // If there are three terminators, we don't know what sort of block this is.
 504   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
 505     return true;
 506
 507   // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
 508   unsigned SecondLastOpc    = SecondLastInst->getOpcode();
 509   Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
 510
 511   if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
 512     int SecondNumOp = SecondLastInst->getNumOperands();
 513
 514     TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
 515     Cond.push_back(MachineOperand::CreateImm(BranchCode));
 516
 517     for (int i=0; i<SecondNumOp-1; i++) {
 518       Cond.push_back(SecondLastInst->getOperand(i));
 519     }
 520
 521     FBB = LastInst->getOperand(0).getMBB();
 522     return false;
 523   }
 524
 525   // If the block ends with two unconditional branches, handle it. The last
 526   // one is not executed, so remove it.
 527   if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
 528     TBB = SecondLastInst->getOperand(0).getMBB();
 529     I = LastInst;
 530     if (AllowModify)
 531       I->eraseFromParent();
 532     return false;
 533   }
 534
 535   // Otherwise, can't handle this.
 536   return true;
 537 }
 538
 539 unsigned MipsInstrInfo::
 540 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
 541              MachineBasicBlock *FBB,
 542              const SmallVectorImpl<MachineOperand> &Cond) const {
 543   // FIXME this should probably have a DebugLoc argument
 544   DebugLoc dl = DebugLoc::getUnknownLoc();
 545   // Shouldn't be a fall through.
 546   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
 547   assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
 548          "Mips branch conditions can have two|three components!");
 549
 550   if (FBB == 0) { // One way branch.
 551     if (Cond.empty()) {
 552       // Unconditional branch?
 553       BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
 554     } else {
 555       // Conditional branch.
 556       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
 557       const TargetInstrDesc &TID = get(Opc);
 558
 559       if (TID.getNumOperands() == 3)
 560         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
 561                           .addReg(Cond[2].getReg())
 562                           .addMBB(TBB);
 563       else
 564         BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
 565                           .addMBB(TBB);
 566
 567     }
 568     return 1;
 569   }
 570
 571   // Two-way Conditional branch.
 572   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
 573   const TargetInstrDesc &TID = get(Opc);
 574
 575   if (TID.getNumOperands() == 3)
 576     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
 577                       .addMBB(TBB);
 578   else
 579     BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
 580
 581   BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
 582   return 2;
 583 }
 584
 585 unsigned MipsInstrInfo::
 586 RemoveBranch(MachineBasicBlock &MBB) const
 587 {
 588   MachineBasicBlock::iterator I = MBB.end();
 589   if (I == MBB.begin()) return 0;
 590   --I;
 591   if (I->getOpcode() != Mips::J &&
 592       GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
 593     return 0;
 594
 595   // Remove the branch.
 596   I->eraseFromParent();
 597
 598   I = MBB.end();
 599
 600   if (I == MBB.begin()) return 1;
 601   --I;
 602   if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
 603     return 1;
 604
 605   // Remove the branch.
 606   I->eraseFromParent();
 607   return 2;
 608 }
 609
 610 /// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
 611 /// fall-through into its successor block.
 612 bool MipsInstrInfo::
 613 BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
 614 {
 615   if (MBB.empty()) return false;
 616
 617   switch (MBB.back().getOpcode()) {
 618   case Mips::RET:     // Return.
 619   case Mips::JR:      // Indirect branch.
 620   case Mips::J:       // Uncond branch.
 621     return true;
 622   default: return false;
 623   }
 624 }
 625
 626 /// ReverseBranchCondition - Return the inverse opcode of the
 627 /// specified Branch instruction.
 628 bool MipsInstrInfo::
 629 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
 630 {
 631   assert( (Cond.size() == 3 || Cond.size() == 2) &&
 632           "Invalid Mips branch condition!");
 633   Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
 634   return false;
 635 }