Add 8-bit regclass and pattern for sext_inreg
[llvm/msp430.git] / lib / Target / X86 / X86InstrBuilder.h
blobaa3e0333daf8e4ce6f6bbfa102700976775a50a0
1 //===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file exposes functions that may be used with BuildMI from the
11 // MachineInstrBuilder.h file to handle X86'isms in a clean way.
13 // The BuildMem function may be used with the BuildMI function to add entire
14 // memory references in a single, typed, function call. X86 memory references
15 // can be very complex expressions (described in the README), so wrapping them
16 // up behind an easier to use interface makes sense. Descriptions of the
17 // functions are included below.
19 // For reference, the order of operands for memory references is:
20 // (Operand), Base, Scale, Index, Displacement.
22 //===----------------------------------------------------------------------===//
24 #ifndef X86INSTRBUILDER_H
25 #define X86INSTRBUILDER_H
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/PseudoSourceValue.h"
31 namespace llvm {
33 /// X86AddressMode - This struct holds a generalized full x86 address mode.
34 /// The base register can be a frame index, which will eventually be replaced
35 /// with BP or SP and Disp being offsetted accordingly. The displacement may
36 /// also include the offset of a global value.
37 struct X86AddressMode {
38 enum {
39 RegBase,
40 FrameIndexBase
41 } BaseType;
43 union {
44 unsigned Reg;
45 int FrameIndex;
46 } Base;
48 unsigned Scale;
49 unsigned IndexReg;
50 unsigned Disp;
51 GlobalValue *GV;
53 X86AddressMode() : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0) {
54 Base.Reg = 0;
58 /// addDirectMem - This function is used to add a direct memory reference to the
59 /// current instruction -- that is, a dereference of an address in a register,
60 /// with no scale, index or displacement. An example is: DWORD PTR [EAX].
61 ///
62 inline const MachineInstrBuilder &addDirectMem(const MachineInstrBuilder &MIB,
63 unsigned Reg) {
64 // Because memory references are always represented with four
65 // values, this adds: Reg, [1, NoReg, 0] to the instruction.
66 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0);
69 inline const MachineInstrBuilder &addLeaOffset(const MachineInstrBuilder &MIB,
70 int Offset) {
71 return MIB.addImm(1).addReg(0).addImm(Offset);
74 inline const MachineInstrBuilder &addOffset(const MachineInstrBuilder &MIB,
75 int Offset) {
76 return addLeaOffset(MIB, Offset).addReg(0);
79 /// addRegOffset - This function is used to add a memory reference of the form
80 /// [Reg + Offset], i.e., one with no scale or index, but with a
81 /// displacement. An example is: DWORD PTR [EAX + 4].
82 ///
83 inline const MachineInstrBuilder &addRegOffset(const MachineInstrBuilder &MIB,
84 unsigned Reg, bool isKill,
85 int Offset) {
86 return addOffset(MIB.addReg(Reg, false, false, isKill), Offset);
89 inline const MachineInstrBuilder &addLeaRegOffset(const MachineInstrBuilder &MIB,
90 unsigned Reg, bool isKill,
91 int Offset) {
92 return addLeaOffset(MIB.addReg(Reg, false, false, isKill), Offset);
95 /// addRegReg - This function is used to add a memory reference of the form:
96 /// [Reg + Reg].
97 inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
98 unsigned Reg1, bool isKill1,
99 unsigned Reg2, bool isKill2) {
100 return MIB.addReg(Reg1, false, false, isKill1).addImm(1)
101 .addReg(Reg2, false, false, isKill2).addImm(0);
104 inline const MachineInstrBuilder &addLeaAddress(const MachineInstrBuilder &MIB,
105 const X86AddressMode &AM) {
106 assert (AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
108 if (AM.BaseType == X86AddressMode::RegBase)
109 MIB.addReg(AM.Base.Reg);
110 else if (AM.BaseType == X86AddressMode::FrameIndexBase)
111 MIB.addFrameIndex(AM.Base.FrameIndex);
112 else
113 assert (0);
114 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
115 if (AM.GV)
116 return MIB.addGlobalAddress(AM.GV, AM.Disp);
117 else
118 return MIB.addImm(AM.Disp);
121 inline const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
122 const X86AddressMode &AM) {
123 return addLeaAddress(MIB, AM).addReg(0);
126 /// addFrameReference - This function is used to add a reference to the base of
127 /// an abstract object on the stack frame of the current function. This
128 /// reference has base register as the FrameIndex offset until it is resolved.
129 /// This allows a constant offset to be specified as well...
131 inline const MachineInstrBuilder &
132 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
133 MachineInstr *MI = MIB;
134 MachineFunction &MF = *MI->getParent()->getParent();
135 MachineFrameInfo &MFI = *MF.getFrameInfo();
136 const TargetInstrDesc &TID = MI->getDesc();
137 unsigned Flags = 0;
138 if (TID.mayLoad())
139 Flags |= MachineMemOperand::MOLoad;
140 if (TID.mayStore())
141 Flags |= MachineMemOperand::MOStore;
142 MachineMemOperand MMO(PseudoSourceValue::getFixedStack(FI),
143 Flags,
144 MFI.getObjectOffset(FI) + Offset,
145 MFI.getObjectSize(FI),
146 MFI.getObjectAlignment(FI));
147 return addOffset(MIB.addFrameIndex(FI), Offset)
148 .addMemOperand(MMO);
151 /// addConstantPoolReference - This function is used to add a reference to the
152 /// base of a constant value spilled to the per-function constant pool. The
153 /// reference uses the abstract ConstantPoolIndex which is retained until
154 /// either machine code emission or assembly output. In PIC mode on x86-32,
155 /// the GlobalBaseReg parameter can be used to make this a
156 /// GlobalBaseReg-relative reference.
158 inline const MachineInstrBuilder &
159 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
160 unsigned GlobalBaseReg = 0) {
161 //FIXME: factor this
162 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
163 .addConstantPoolIndex(CPI).addReg(0);
166 } // End llvm namespace
168 #endif