lib/Target/XCore/XCoreISelLowering.cpp

   1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation   ------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the XCoreTargetLowering class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #define DEBUG_TYPE "xcore-lower"
  15
  16 #include "XCoreISelLowering.h"
  17 #include "XCoreMachineFunctionInfo.h"
  18 #include "XCore.h"
  19 #include "XCoreTargetMachine.h"
  20 #include "XCoreSubtarget.h"
  21 #include "llvm/DerivedTypes.h"
  22 #include "llvm/Function.h"
  23 #include "llvm/Intrinsics.h"
  24 #include "llvm/CallingConv.h"
  25 #include "llvm/GlobalVariable.h"
  26 #include "llvm/GlobalAlias.h"
  27 #include "llvm/CodeGen/CallingConvLower.h"
  28 #include "llvm/CodeGen/MachineFrameInfo.h"
  29 #include "llvm/CodeGen/MachineFunction.h"
  30 #include "llvm/CodeGen/MachineInstrBuilder.h"
  31 #include "llvm/CodeGen/MachineRegisterInfo.h"
  32 #include "llvm/CodeGen/SelectionDAGISel.h"
  33 #include "llvm/CodeGen/ValueTypes.h"
  34 #include "llvm/Support/Debug.h"
  35 #include "llvm/ADT/VectorExtras.h"
  36 #include <queue>
  37 #include <set>
  38 using namespace llvm;
  39
  40 const char *XCoreTargetLowering::
  41 getTargetNodeName(unsigned Opcode) const
  42 {
  43   switch (Opcode)
  44   {
  45     case XCoreISD::BL                : return "XCoreISD::BL";
  46     case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
  47     case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
  48     case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
  49     case XCoreISD::STWSP             : return "XCoreISD::STWSP";
  50     case XCoreISD::RETSP             : return "XCoreISD::RETSP";
  51     default                           : return NULL;
  52   }
  53 }
  54
  55 XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
  56   : TargetLowering(XTM),
  57     TM(XTM),
  58     Subtarget(*XTM.getSubtargetImpl()) {
  59
  60   // Set up the register classes.
  61   addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
  62
  63   // Compute derived properties from the register classes
  64   computeRegisterProperties();
  65
  66   // Division is expensive
  67   setIntDivIsCheap(false);
  68
  69   setShiftAmountType(MVT::i32);
  70   // shl X, 32 == 0
  71   setShiftAmountFlavor(Extend);
  72   setStackPointerRegisterToSaveRestore(XCore::SP);
  73
  74   setSchedulingPreference(SchedulingForRegPressure);
  75
  76   // Use i32 for setcc operations results (slt, sgt, ...).
  77   setBooleanContents(ZeroOrOneBooleanContent);
  78
  79   // XCore does not have the NodeTypes below.
  80   setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
  81   setOperationAction(ISD::SELECT_CC, MVT::i32,   Custom);
  82   setOperationAction(ISD::ADDC, MVT::i32, Expand);
  83   setOperationAction(ISD::ADDE, MVT::i32, Expand);
  84   setOperationAction(ISD::SUBC, MVT::i32, Expand);
  85   setOperationAction(ISD::SUBE, MVT::i32, Expand);
  86
  87   // Stop the combiner recombining select and set_cc
  88   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
  89
  90   // 64bit
  91   if (!Subtarget.isXS1A()) {
  92     setOperationAction(ISD::ADD, MVT::i64, Custom);
  93     setOperationAction(ISD::SUB, MVT::i64, Custom);
  94   }
  95   if (Subtarget.isXS1A()) {
  96     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
  97   }
  98   setOperationAction(ISD::MULHS, MVT::i32, Expand);
  99   setOperationAction(ISD::MULHU, MVT::i32, Expand);
 100   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
 101   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
 102   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
 103
 104   // Bit Manipulation
 105   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
 106   setOperationAction(ISD::ROTL , MVT::i32, Expand);
 107   setOperationAction(ISD::ROTR , MVT::i32, Expand);
 108
 109   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 110
 111   // Expand jump tables for now
 112   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
 113   setOperationAction(ISD::JumpTable, MVT::i32, Custom);
 114
 115   // RET must be custom lowered, to meet ABI requirements
 116   setOperationAction(ISD::RET,           MVT::Other, Custom);
 117
 118   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
 119
 120   // Thread Local Storage
 121   setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
 122
 123   // Conversion of i64 -> double produces constantpool nodes
 124   setOperationAction(ISD::ConstantPool, MVT::i32,   Custom);
 125
 126   // Loads
 127   setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
 128   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
 129   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
 130
 131   setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
 132   setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
 133
 134   // Varargs
 135   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 136   setOperationAction(ISD::VACOPY, MVT::Other, Expand);
 137   setOperationAction(ISD::VAARG, MVT::Other, Custom);
 138   setOperationAction(ISD::VASTART, MVT::Other, Custom);
 139
 140   // Dynamic stack
 141   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
 142   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
 143   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
 144
 145   // Debug
 146   setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
 147   setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
 148 }
 149
 150 SDValue XCoreTargetLowering::
 151 LowerOperation(SDValue Op, SelectionDAG &DAG) {
 152   switch (Op.getOpcode())
 153   {
 154   case ISD::CALL:             return LowerCALL(Op, DAG);
 155   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
 156   case ISD::RET:              return LowerRET(Op, DAG);
 157   case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
 158   case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
 159   case ISD::ConstantPool:     return LowerConstantPool(Op, DAG);
 160   case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
 161   case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
 162   case ISD::VAARG:            return LowerVAARG(Op, DAG);
 163   case ISD::VASTART:          return LowerVASTART(Op, DAG);
 164   // FIXME: Remove these when LegalizeDAGTypes lands.
 165   case ISD::ADD:
 166   case ISD::SUB:              return ExpandADDSUB(Op.getNode(), DAG);
 167   case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
 168   default:
 169     assert(0 && "unimplemented operand");
 170     return SDValue();
 171   }
 172 }
 173
 174 /// ReplaceNodeResults - Replace the results of node with an illegal result
 175 /// type with new values built out of custom code.
 176 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
 177                                              SmallVectorImpl<SDValue>&Results,
 178                                              SelectionDAG &DAG) {
 179   switch (N->getOpcode()) {
 180   default:
 181     assert(0 && "Don't know how to custom expand this!");
 182     return;
 183   case ISD::ADD:
 184   case ISD::SUB:
 185     Results.push_back(ExpandADDSUB(N, DAG));
 186     return;
 187   }
 188 }
 189
 190 //===----------------------------------------------------------------------===//
 191 //  Misc Lower Operation implementation
 192 //===----------------------------------------------------------------------===//
 193
 194 SDValue XCoreTargetLowering::
 195 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
 196 {
 197   DebugLoc dl = Op.getDebugLoc();
 198   SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
 199                              Op.getOperand(3), Op.getOperand(4));
 200   return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
 201                      Op.getOperand(1));
 202 }
 203
 204 SDValue XCoreTargetLowering::
 205 getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG)
 206 {
 207   // FIXME there is no actual debug info here
 208   DebugLoc dl = GA.getDebugLoc();
 209   if (isa<Function>(GV)) {
 210     return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
 211   } else if (!Subtarget.isXS1A()) {
 212     const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
 213     if (!GVar) {
 214       // If GV is an alias then use the aliasee to determine constness
 215       if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
 216         GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
 217     }
 218     bool isConst = GVar && GVar->isConstant();
 219     if (isConst) {
 220       return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
 221     }
 222   }
 223   return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
 224 }
 225
 226 SDValue XCoreTargetLowering::
 227 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
 228 {
 229   GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 230   SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
 231   // If it's a debug information descriptor, don't mess with it.
 232   if (DAG.isVerifiedDebugInfoDesc(Op))
 233     return GA;
 234   return getGlobalAddressWrapper(GA, GV, DAG);
 235 }
 236
 237 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
 238   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
 239                      DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
 240 }
 241
 242 static inline bool isZeroLengthArray(const Type *Ty) {
 243   const ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty);
 244   return AT && (AT->getNumElements() == 0);
 245 }
 246
 247 SDValue XCoreTargetLowering::
 248 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
 249 {
 250   // FIXME there isn't really debug info here
 251   DebugLoc dl = Op.getDebugLoc();
 252   // transform to label + getid() * size
 253   GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
 254   SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
 255   const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
 256   if (!GVar) {
 257     // If GV is an alias then use the aliasee to determine size
 258     if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
 259       GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
 260   }
 261   if (! GVar) {
 262     assert(0 && "Thread local object not a GlobalVariable?");
 263     return SDValue();
 264   }
 265   const Type *Ty = cast<PointerType>(GV->getType())->getElementType();
 266   if (!Ty->isSized() || isZeroLengthArray(Ty)) {
 267     cerr << "Size of thread local object " << GVar->getName()
 268          << " is unknown\n";
 269     abort();
 270   }
 271   SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
 272   const TargetData *TD = TM.getTargetData();
 273   unsigned Size = TD->getTypePaddedSize(Ty);
 274   SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
 275                        DAG.getConstant(Size, MVT::i32));
 276   return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
 277 }
 278
 279 SDValue XCoreTargetLowering::
 280 LowerConstantPool(SDValue Op, SelectionDAG &DAG)
 281 {
 282   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
 283   // FIXME there isn't really debug info here
 284   DebugLoc dl = CP->getDebugLoc();
 285   if (Subtarget.isXS1A()) {
 286     assert(0 && "Lowering of constant pool unimplemented");
 287     return SDValue();
 288   } else {
 289     MVT PtrVT = Op.getValueType();
 290     SDValue Res;
 291     if (CP->isMachineConstantPoolEntry()) {
 292       Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
 293                                       CP->getAlignment());
 294     } else {
 295       Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
 296                                       CP->getAlignment());
 297     }
 298     return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
 299   }
 300 }
 301
 302 SDValue XCoreTargetLowering::
 303 LowerJumpTable(SDValue Op, SelectionDAG &DAG)
 304 {
 305   // FIXME there isn't really debug info here
 306   DebugLoc dl = Op.getDebugLoc();
 307   MVT PtrVT = Op.getValueType();
 308   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
 309   SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
 310   return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, JTI);
 311 }
 312
 313 SDValue XCoreTargetLowering::
 314 ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
 315 {
 316   assert(N->getValueType(0) == MVT::i64 &&
 317          (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
 318         "Unknown operand to lower!");
 319   assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a");
 320   DebugLoc dl = N->getDebugLoc();
 321
 322   // Extract components
 323   SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
 324                             N->getOperand(0),  DAG.getConstant(0, MVT::i32));
 325   SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
 326                             N->getOperand(0),  DAG.getConstant(1, MVT::i32));
 327   SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
 328                              N->getOperand(1), DAG.getConstant(0, MVT::i32));
 329   SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
 330                              N->getOperand(1), DAG.getConstant(1, MVT::i32));
 331
 332   // Expand
 333   unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
 334                                                    XCoreISD::LSUB;
 335   SDValue Zero = DAG.getConstant(0, MVT::i32);
 336   SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
 337                                   LHSL, RHSL, Zero);
 338   SDValue Lo(Carry.getNode(), 1);
 339
 340   SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
 341                                   LHSH, RHSH, Carry);
 342   SDValue Hi(Ignored.getNode(), 1);
 343   // Merge the pieces
 344   return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
 345 }
 346
 347 SDValue XCoreTargetLowering::
 348 LowerVAARG(SDValue Op, SelectionDAG &DAG)
 349 {
 350   assert(0 && "unimplemented");
 351   // FIX Arguments passed by reference need a extra dereference.
 352   SDNode *Node = Op.getNode();
 353   DebugLoc dl = Node->getDebugLoc();
 354   const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
 355   MVT VT = Node->getValueType(0);
 356   SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
 357                                Node->getOperand(1), V, 0);
 358   // Increment the pointer, VAList, to the next vararg
 359   SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
 360                      DAG.getConstant(VT.getSizeInBits(),
 361                                      getPointerTy()));
 362   // Store the incremented VAList to the legalized pointer
 363   Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0);
 364   // Load the actual argument out of the pointer VAList
 365   return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
 366 }
 367
 368 SDValue XCoreTargetLowering::
 369 LowerVASTART(SDValue Op, SelectionDAG &DAG)
 370 {
 371   DebugLoc dl = Op.getDebugLoc();
 372   // vastart stores the address of the VarArgsFrameIndex slot into the
 373   // memory location argument
 374   MachineFunction &MF = DAG.getMachineFunction();
 375   XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
 376   SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
 377   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
 378   return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0);
 379 }
 380
 381 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
 382   DebugLoc dl = Op.getDebugLoc();
 383   // Depths > 0 not supported yet!
 384   if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
 385     return SDValue();
 386
 387   MachineFunction &MF = DAG.getMachineFunction();
 388   const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
 389   return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
 390                             RegInfo->getFrameRegister(MF), MVT::i32);
 391 }
 392
 393 //===----------------------------------------------------------------------===//
 394 //                      Calling Convention Implementation
 395 //
 396 //  The lower operations present on calling convention works on this order:
 397 //      LowerCALL (virt regs --> phys regs, virt regs --> stack)
 398 //      LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs)
 399 //      LowerRET (virt regs --> phys regs)
 400 //      LowerCALL (phys regs --> virt regs)
 401 //
 402 //===----------------------------------------------------------------------===//
 403
 404 #include "XCoreGenCallingConv.inc"
 405
 406 //===----------------------------------------------------------------------===//
 407 //                  CALL Calling Convention Implementation
 408 //===----------------------------------------------------------------------===//
 409
 410 /// XCore custom CALL implementation
 411 SDValue XCoreTargetLowering::
 412 LowerCALL(SDValue Op, SelectionDAG &DAG)
 413 {
 414   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
 415   unsigned CallingConv = TheCall->getCallingConv();
 416   // For now, only CallingConv::C implemented
 417   switch (CallingConv)
 418   {
 419     default:
 420       assert(0 && "Unsupported calling convention");
 421     case CallingConv::Fast:
 422     case CallingConv::C:
 423       return LowerCCCCallTo(Op, DAG, CallingConv);
 424   }
 425 }
 426
 427 /// LowerCCCCallTo - functions arguments are copied from virtual
 428 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
 429 /// CALLSEQ_END are emitted.
 430 /// TODO: isTailCall, sret.
 431 SDValue XCoreTargetLowering::
 432 LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
 433 {
 434   CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
 435   SDValue Chain  = TheCall->getChain();
 436   SDValue Callee = TheCall->getCallee();
 437   bool isVarArg  = TheCall->isVarArg();
 438   DebugLoc dl = Op.getDebugLoc();
 439
 440   // Analyze operands of the call, assigning locations to each operand.
 441   SmallVector<CCValAssign, 16> ArgLocs;
 442   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 443
 444   // The ABI dictates there should be one stack slot available to the callee
 445   // on function entry (for saving lr).
 446   CCInfo.AllocateStack(4, 4);
 447
 448   CCInfo.AnalyzeCallOperands(TheCall, CC_XCore);
 449
 450   // Get a count of how many bytes are to be pushed on the stack.
 451   unsigned NumBytes = CCInfo.getNextStackOffset();
 452
 453   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
 454                                  getPointerTy(), true));
 455
 456   SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
 457   SmallVector<SDValue, 12> MemOpChains;
 458
 459   // Walk the register/memloc assignments, inserting copies/loads.
 460   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 461     CCValAssign &VA = ArgLocs[i];
 462
 463     // Arguments start after the 5 first operands of ISD::CALL
 464     SDValue Arg = TheCall->getArg(i);
 465
 466     // Promote the value if needed.
 467     switch (VA.getLocInfo()) {
 468       default: assert(0 && "Unknown loc info!");
 469       case CCValAssign::Full: break;
 470       case CCValAssign::SExt:
 471         Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
 472         break;
 473       case CCValAssign::ZExt:
 474         Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
 475         break;
 476       case CCValAssign::AExt:
 477         Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
 478         break;
 479     }
 480
 481     // Arguments that can be passed on register must be kept at
 482     // RegsToPass vector
 483     if (VA.isRegLoc()) {
 484       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
 485     } else {
 486       assert(VA.isMemLoc());
 487
 488       int Offset = VA.getLocMemOffset();
 489
 490       MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
 491                                         Chain, Arg,
 492                                         DAG.getConstant(Offset/4, MVT::i32)));
 493     }
 494   }
 495
 496   // Transform all store nodes into one single node because
 497   // all store nodes are independent of each other.
 498   if (!MemOpChains.empty())
 499     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 500                         &MemOpChains[0], MemOpChains.size());
 501
 502   // Build a sequence of copy-to-reg nodes chained together with token
 503   // chain and flag operands which copy the outgoing args into registers.
 504   // The InFlag in necessary since all emited instructions must be
 505   // stuck together.
 506   SDValue InFlag;
 507   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
 508     Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
 509                              RegsToPass[i].second, InFlag);
 510     InFlag = Chain.getValue(1);
 511   }
 512
 513   // If the callee is a GlobalAddress node (quite common, every direct call is)
 514   // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
 515   // Likewise ExternalSymbol -> TargetExternalSymbol.
 516   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
 517     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
 518   else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
 519     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
 520
 521   // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
 522   //             = Chain, Callee, Reg#1, Reg#2, ...
 523   //
 524   // Returns a chain & a flag for retval copy to use.
 525   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
 526   SmallVector<SDValue, 8> Ops;
 527   Ops.push_back(Chain);
 528   Ops.push_back(Callee);
 529
 530   // Add argument registers to the end of the list so that they are
 531   // known live into the call.
 532   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
 533     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
 534                                   RegsToPass[i].second.getValueType()));
 535
 536   if (InFlag.getNode())
 537     Ops.push_back(InFlag);
 538
 539   Chain  = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
 540   InFlag = Chain.getValue(1);
 541
 542   // Create the CALLSEQ_END node.
 543   Chain = DAG.getCALLSEQ_END(Chain,
 544                              DAG.getConstant(NumBytes, getPointerTy(), true),
 545                              DAG.getConstant(0, getPointerTy(), true),
 546                              InFlag);
 547   InFlag = Chain.getValue(1);
 548
 549   // Handle result values, copying them out of physregs into vregs that we
 550   // return.
 551   return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
 552                  Op.getResNo());
 553 }
 554
 555 /// LowerCallResult - Lower the result values of an ISD::CALL into the
 556 /// appropriate copies out of appropriate physical registers.  This assumes that
 557 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
 558 /// being lowered. Returns a SDNode with the same number of values as the
 559 /// ISD::CALL.
 560 SDNode *XCoreTargetLowering::
 561 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
 562         unsigned CallingConv, SelectionDAG &DAG) {
 563   bool isVarArg = TheCall->isVarArg();
 564   DebugLoc dl = TheCall->getDebugLoc();
 565
 566   // Assign locations to each value returned by this call.
 567   SmallVector<CCValAssign, 16> RVLocs;
 568   CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
 569
 570   CCInfo.AnalyzeCallResult(TheCall, RetCC_XCore);
 571   SmallVector<SDValue, 8> ResultVals;
 572
 573   // Copy all of the result registers out of their specified physreg.
 574   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 575     Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
 576                                  RVLocs[i].getValVT(), InFlag).getValue(1);
 577     InFlag = Chain.getValue(2);
 578     ResultVals.push_back(Chain.getValue(0));
 579   }
 580
 581   ResultVals.push_back(Chain);
 582
 583   // Merge everything together with a MERGE_VALUES node.
 584   return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
 585                      &ResultVals[0], ResultVals.size()).getNode();
 586 }
 587
 588 //===----------------------------------------------------------------------===//
 589 //             FORMAL_ARGUMENTS Calling Convention Implementation
 590 //===----------------------------------------------------------------------===//
 591
 592 /// XCore custom FORMAL_ARGUMENTS implementation
 593 SDValue XCoreTargetLowering::
 594 LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
 595 {
 596   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
 597   switch(CC)
 598   {
 599     default:
 600       assert(0 && "Unsupported calling convention");
 601     case CallingConv::C:
 602     case CallingConv::Fast:
 603       return LowerCCCArguments(Op, DAG);
 604   }
 605 }
 606
 607 /// LowerCCCArguments - transform physical registers into
 608 /// virtual registers and generate load operations for
 609 /// arguments places on the stack.
 610 /// TODO: sret
 611 SDValue XCoreTargetLowering::
 612 LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
 613 {
 614   MachineFunction &MF = DAG.getMachineFunction();
 615   MachineFrameInfo *MFI = MF.getFrameInfo();
 616   MachineRegisterInfo &RegInfo = MF.getRegInfo();
 617   SDValue Root = Op.getOperand(0);
 618   bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
 619   unsigned CC = MF.getFunction()->getCallingConv();
 620   DebugLoc dl = Op.getDebugLoc();
 621
 622   // Assign locations to all of the incoming arguments.
 623   SmallVector<CCValAssign, 16> ArgLocs;
 624   CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
 625
 626   CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_XCore);
 627
 628   unsigned StackSlotSize = XCoreFrameInfo::stackSlotSize();
 629
 630   SmallVector<SDValue, 16> ArgValues;
 631
 632   unsigned LRSaveSize = StackSlotSize;
 633
 634   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
 635
 636     CCValAssign &VA = ArgLocs[i];
 637
 638     if (VA.isRegLoc()) {
 639       // Arguments passed in registers
 640       MVT RegVT = VA.getLocVT();
 641       switch (RegVT.getSimpleVT()) {
 642       default:
 643         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 644              << RegVT.getSimpleVT()
 645              << "\n";
 646         abort();
 647       case MVT::i32:
 648         unsigned VReg = RegInfo.createVirtualRegister(
 649                           XCore::GRRegsRegisterClass);
 650         RegInfo.addLiveIn(VA.getLocReg(), VReg);
 651         ArgValues.push_back(DAG.getCopyFromReg(Root, dl, VReg, RegVT));
 652       }
 653     } else {
 654       // sanity check
 655       assert(VA.isMemLoc());
 656       // Load the argument to a virtual register
 657       unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
 658       if (ObjSize > StackSlotSize) {
 659         cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
 660              << VA.getLocVT().getSimpleVT()
 661              << "\n";
 662       }
 663       // Create the frame index object for this incoming parameter...
 664       int FI = MFI->CreateFixedObject(ObjSize,
 665                                       LRSaveSize + VA.getLocMemOffset());
 666
 667       // Create the SelectionDAG nodes corresponding to a load
 668       //from this parameter
 669       SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
 670       ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN, NULL, 0));
 671     }
 672   }
 673
 674   if (isVarArg) {
 675     /* Argument registers */
 676     static const unsigned ArgRegs[] = {
 677       XCore::R0, XCore::R1, XCore::R2, XCore::R3
 678     };
 679     XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
 680     unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
 681                                                      array_lengthof(ArgRegs));
 682     if (FirstVAReg < array_lengthof(ArgRegs)) {
 683       SmallVector<SDValue, 4> MemOps;
 684       int offset = 0;
 685       // Save remaining registers, storing higher register numbers at a higher
 686       // address
 687       for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) {
 688         // Create a stack slot
 689         int FI = MFI->CreateFixedObject(4, offset);
 690         if (i == FirstVAReg) {
 691           XFI->setVarArgsFrameIndex(FI);
 692         }
 693         offset -= StackSlotSize;
 694         SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
 695         // Move argument from phys reg -> virt reg
 696         unsigned VReg = RegInfo.createVirtualRegister(
 697                           XCore::GRRegsRegisterClass);
 698         RegInfo.addLiveIn(ArgRegs[i], VReg);
 699         SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
 700         // Move argument from virt reg -> stack
 701         SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
 702         MemOps.push_back(Store);
 703       }
 704       if (!MemOps.empty())
 705         Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
 706                            &MemOps[0], MemOps.size());
 707     } else {
 708       // This will point to the next argument passed via stack.
 709       XFI->setVarArgsFrameIndex(
 710           MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset()));
 711     }
 712   }
 713
 714   ArgValues.push_back(Root);
 715
 716   // Return the new list of results.
 717   std::vector<MVT> RetVT(Op.getNode()->value_begin(),
 718                                     Op.getNode()->value_end());
 719   return DAG.getNode(ISD::MERGE_VALUES, dl, RetVT,
 720                      &ArgValues[0], ArgValues.size());
 721 }
 722
 723 //===----------------------------------------------------------------------===//
 724 //               Return Value Calling Convention Implementation
 725 //===----------------------------------------------------------------------===//
 726
 727 SDValue XCoreTargetLowering::
 728 LowerRET(SDValue Op, SelectionDAG &DAG)
 729 {
 730   // CCValAssign - represent the assignment of
 731   // the return value to a location
 732   SmallVector<CCValAssign, 16> RVLocs;
 733   unsigned CC   = DAG.getMachineFunction().getFunction()->getCallingConv();
 734   bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
 735   DebugLoc dl = Op.getDebugLoc();
 736
 737   // CCState - Info about the registers and stack slot.
 738   CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
 739
 740   // Analize return values of ISD::RET
 741   CCInfo.AnalyzeReturn(Op.getNode(), RetCC_XCore);
 742
 743   // If this is the first return lowered for this function, add
 744   // the regs to the liveout set for the function.
 745   if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
 746     for (unsigned i = 0; i != RVLocs.size(); ++i)
 747       if (RVLocs[i].isRegLoc())
 748         DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
 749   }
 750
 751   // The chain is always operand #0
 752   SDValue Chain = Op.getOperand(0);
 753   SDValue Flag;
 754
 755   // Copy the result values into the output registers.
 756   for (unsigned i = 0; i != RVLocs.size(); ++i) {
 757     CCValAssign &VA = RVLocs[i];
 758     assert(VA.isRegLoc() && "Can only return in registers!");
 759
 760     // ISD::RET => ret chain, (regnum1,val1), ...
 761     // So i*2+1 index only the regnums
 762     Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
 763                              Op.getOperand(i*2+1), Flag);
 764
 765     // guarantee that all emitted copies are
 766     // stuck together, avoiding something bad
 767     Flag = Chain.getValue(1);
 768   }
 769
 770   // Return on XCore is always a "retsp 0"
 771   if (Flag.getNode())
 772     return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
 773                        Chain, DAG.getConstant(0, MVT::i32), Flag);
 774   else // Return Void
 775     return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
 776                        Chain, DAG.getConstant(0, MVT::i32));
 777 }
 778
 779 //===----------------------------------------------------------------------===//
 780 //  Other Lowering Code
 781 //===----------------------------------------------------------------------===//
 782
 783 MachineBasicBlock *
 784 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
 785                                                  MachineBasicBlock *BB) const {
 786   const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
 787   DebugLoc dl = MI->getDebugLoc();
 788   assert((MI->getOpcode() == XCore::SELECT_CC) &&
 789          "Unexpected instr type to insert");
 790
 791   // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
 792   // control-flow pattern.  The incoming instruction knows the destination vreg
 793   // to set, the condition code register to branch on, the true/false values to
 794   // select between, and a branch opcode to use.
 795   const BasicBlock *LLVM_BB = BB->getBasicBlock();
 796   MachineFunction::iterator It = BB;
 797   ++It;
 798
 799   //  thisMBB:
 800   //  ...
 801   //   TrueVal = ...
 802   //   cmpTY ccX, r1, r2
 803   //   bCC copy1MBB
 804   //   fallthrough --> copy0MBB
 805   MachineBasicBlock *thisMBB = BB;
 806   MachineFunction *F = BB->getParent();
 807   MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
 808   MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
 809   BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
 810     .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
 811   F->insert(It, copy0MBB);
 812   F->insert(It, sinkMBB);
 813   // Update machine-CFG edges by transferring all successors of the current
 814   // block to the new block which will contain the Phi node for the select.
 815   sinkMBB->transferSuccessors(BB);
 816   // Next, add the true and fallthrough blocks as its successors.
 817   BB->addSuccessor(copy0MBB);
 818   BB->addSuccessor(sinkMBB);
 819
 820   //  copy0MBB:
 821   //   %FalseValue = ...
 822   //   # fallthrough to sinkMBB
 823   BB = copy0MBB;
 824
 825   // Update machine-CFG edges
 826   BB->addSuccessor(sinkMBB);
 827
 828   //  sinkMBB:
 829   //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
 830   //  ...
 831   BB = sinkMBB;
 832   BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg())
 833     .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
 834     .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
 835
 836   F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
 837   return BB;
 838 }
 839
 840 //===----------------------------------------------------------------------===//
 841 //  Addressing mode description hooks
 842 //===----------------------------------------------------------------------===//
 843
 844 static inline bool isImmUs(int64_t val)
 845 {
 846   return (val >= 0 && val <= 11);
 847 }
 848
 849 static inline bool isImmUs2(int64_t val)
 850 {
 851   return (val%2 == 0 && isImmUs(val/2));
 852 }
 853
 854 static inline bool isImmUs4(int64_t val)
 855 {
 856   return (val%4 == 0 && isImmUs(val/4));
 857 }
 858
 859 /// isLegalAddressingMode - Return true if the addressing mode represented
 860 /// by AM is legal for this target, for a load/store of the specified type.
 861 bool
 862 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
 863                                               const Type *Ty) const {
 864   MVT VT = getValueType(Ty, true);
 865   // Get expected value type after legalization
 866   switch (VT.getSimpleVT()) {
 867   // Legal load / stores
 868   case MVT::i8:
 869   case MVT::i16:
 870   case MVT::i32:
 871     break;
 872   // Expand i1 -> i8
 873   case MVT::i1:
 874     VT = MVT::i8;
 875     break;
 876   // Everything else is lowered to words
 877   default:
 878     VT = MVT::i32;
 879     break;
 880   }
 881   if (AM.BaseGV) {
 882     return VT == MVT::i32 && !AM.HasBaseReg && AM.Scale == 0 &&
 883                  AM.BaseOffs%4 == 0;
 884   }
 885
 886   switch (VT.getSimpleVT()) {
 887   default:
 888     return false;
 889   case MVT::i8:
 890     // reg + imm
 891     if (AM.Scale == 0) {
 892       return isImmUs(AM.BaseOffs);
 893     }
 894     return AM.Scale == 1 && AM.BaseOffs == 0;
 895   case MVT::i16:
 896     // reg + imm
 897     if (AM.Scale == 0) {
 898       return isImmUs2(AM.BaseOffs);
 899     }
 900     return AM.Scale == 2 && AM.BaseOffs == 0;
 901   case MVT::i32:
 902     // reg + imm
 903     if (AM.Scale == 0) {
 904       return isImmUs4(AM.BaseOffs);
 905     }
 906     // reg + reg<<2
 907     return AM.Scale == 4 && AM.BaseOffs == 0;
 908   }
 909
 910   return false;
 911 }
 912
 913 //===----------------------------------------------------------------------===//
 914 //                           XCore Inline Assembly Support
 915 //===----------------------------------------------------------------------===//
 916
 917 std::vector<unsigned> XCoreTargetLowering::
 918 getRegClassForInlineAsmConstraint(const std::string &Constraint,
 919                                   MVT VT) const
 920 {
 921   if (Constraint.size() != 1)
 922     return std::vector<unsigned>();
 923
 924   switch (Constraint[0]) {
 925     default : break;
 926     case 'r':
 927       return make_vector<unsigned>(XCore::R0, XCore::R1,  XCore::R2,
 928                                    XCore::R3, XCore::R4,  XCore::R5,
 929                                    XCore::R6, XCore::R7,  XCore::R8,
 930                                    XCore::R9, XCore::R10, XCore::R11, 0);
 931       break;
 932   }
 933   return std::vector<unsigned>();
 934 }