lib/CodeGen/MachineInstr.cpp

   1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Methods common to all machine instructions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/MachineInstr.h"
  15 #include "llvm/Constants.h"
  16 #include "llvm/InlineAsm.h"
  17 #include "llvm/Value.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineRegisterInfo.h"
  20 #include "llvm/CodeGen/PseudoSourceValue.h"
  21 #include "llvm/Target/TargetMachine.h"
  22 #include "llvm/Target/TargetInstrInfo.h"
  23 #include "llvm/Target/TargetInstrDesc.h"
  24 #include "llvm/Target/TargetRegisterInfo.h"
  25 #include "llvm/Analysis/DebugInfo.h"
  26 #include "llvm/Support/LeakDetector.h"
  27 #include "llvm/Support/MathExtras.h"
  28 #include "llvm/Support/Streams.h"
  29 #include "llvm/Support/raw_ostream.h"
  30 #include "llvm/ADT/FoldingSet.h"
  31 #include <ostream>
  32 using namespace llvm;
  33
  34 //===----------------------------------------------------------------------===//
  35 // MachineOperand Implementation
  36 //===----------------------------------------------------------------------===//
  37
  38 /// AddRegOperandToRegInfo - Add this register operand to the specified
  39 /// MachineRegisterInfo.  If it is null, then the next/prev fields should be
  40 /// explicitly nulled out.
  41 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
  42   assert(isReg() && "Can only add reg operand to use lists");
  43
  44   // If the reginfo pointer is null, just explicitly null out or next/prev
  45   // pointers, to ensure they are not garbage.
  46   if (RegInfo == 0) {
  47     Contents.Reg.Prev = 0;
  48     Contents.Reg.Next = 0;
  49     return;
  50   }
  51
  52   // Otherwise, add this operand to the head of the registers use/def list.
  53   MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
  54
  55   // For SSA values, we prefer to keep the definition at the start of the list.
  56   // we do this by skipping over the definition if it is at the head of the
  57   // list.
  58   if (*Head && (*Head)->isDef())
  59     Head = &(*Head)->Contents.Reg.Next;
  60
  61   Contents.Reg.Next = *Head;
  62   if (Contents.Reg.Next) {
  63     assert(getReg() == Contents.Reg.Next->getReg() &&
  64            "Different regs on the same list!");
  65     Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
  66   }
  67
  68   Contents.Reg.Prev = Head;
  69   *Head = this;
  70 }
  71
  72 /// RemoveRegOperandFromRegInfo - Remove this register operand from the
  73 /// MachineRegisterInfo it is linked with.
  74 void MachineOperand::RemoveRegOperandFromRegInfo() {
  75   assert(isOnRegUseList() && "Reg operand is not on a use list");
  76   // Unlink this from the doubly linked list of operands.
  77   MachineOperand *NextOp = Contents.Reg.Next;
  78   *Contents.Reg.Prev = NextOp;
  79   if (NextOp) {
  80     assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
  81     NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
  82   }
  83   Contents.Reg.Prev = 0;
  84   Contents.Reg.Next = 0;
  85 }
  86
  87 void MachineOperand::setReg(unsigned Reg) {
  88   if (getReg() == Reg) return; // No change.
  89
  90   // Otherwise, we have to change the register.  If this operand is embedded
  91   // into a machine function, we need to update the old and new register's
  92   // use/def lists.
  93   if (MachineInstr *MI = getParent())
  94     if (MachineBasicBlock *MBB = MI->getParent())
  95       if (MachineFunction *MF = MBB->getParent()) {
  96         RemoveRegOperandFromRegInfo();
  97         Contents.Reg.RegNo = Reg;
  98         AddRegOperandToRegInfo(&MF->getRegInfo());
  99         return;
 100       }
 101
 102   // Otherwise, just change the register, no problem.  :)
 103   Contents.Reg.RegNo = Reg;
 104 }
 105
 106 /// ChangeToImmediate - Replace this operand with a new immediate operand of
 107 /// the specified value.  If an operand is known to be an immediate already,
 108 /// the setImm method should be used.
 109 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
 110   // If this operand is currently a register operand, and if this is in a
 111   // function, deregister the operand from the register's use/def list.
 112   if (isReg() && getParent() && getParent()->getParent() &&
 113       getParent()->getParent()->getParent())
 114     RemoveRegOperandFromRegInfo();
 115
 116   OpKind = MO_Immediate;
 117   Contents.ImmVal = ImmVal;
 118 }
 119
 120 /// ChangeToRegister - Replace this operand with a new register operand of
 121 /// the specified value.  If an operand is known to be an register already,
 122 /// the setReg method should be used.
 123 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
 124                                       bool isKill, bool isDead) {
 125   // If this operand is already a register operand, use setReg to update the
 126   // register's use/def lists.
 127   if (isReg()) {
 128     assert(!isEarlyClobber());
 129     setReg(Reg);
 130   } else {
 131     // Otherwise, change this to a register and set the reg#.
 132     OpKind = MO_Register;
 133     Contents.Reg.RegNo = Reg;
 134
 135     // If this operand is embedded in a function, add the operand to the
 136     // register's use/def list.
 137     if (MachineInstr *MI = getParent())
 138       if (MachineBasicBlock *MBB = MI->getParent())
 139         if (MachineFunction *MF = MBB->getParent())
 140           AddRegOperandToRegInfo(&MF->getRegInfo());
 141   }
 142
 143   IsDef = isDef;
 144   IsImp = isImp;
 145   IsKill = isKill;
 146   IsDead = isDead;
 147   IsEarlyClobber = false;
 148   SubReg = 0;
 149 }
 150
 151 /// isIdenticalTo - Return true if this operand is identical to the specified
 152 /// operand.
 153 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 154   if (getType() != Other.getType()) return false;
 155
 156   switch (getType()) {
 157   default: assert(0 && "Unrecognized operand type");
 158   case MachineOperand::MO_Register:
 159     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
 160            getSubReg() == Other.getSubReg();
 161   case MachineOperand::MO_Immediate:
 162     return getImm() == Other.getImm();
 163   case MachineOperand::MO_FPImmediate:
 164     return getFPImm() == Other.getFPImm();
 165   case MachineOperand::MO_MachineBasicBlock:
 166     return getMBB() == Other.getMBB();
 167   case MachineOperand::MO_FrameIndex:
 168     return getIndex() == Other.getIndex();
 169   case MachineOperand::MO_ConstantPoolIndex:
 170     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
 171   case MachineOperand::MO_JumpTableIndex:
 172     return getIndex() == Other.getIndex();
 173   case MachineOperand::MO_GlobalAddress:
 174     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
 175   case MachineOperand::MO_ExternalSymbol:
 176     return !strcmp(getSymbolName(), Other.getSymbolName()) &&
 177            getOffset() == Other.getOffset();
 178   }
 179 }
 180
 181 /// print - Print the specified machine operand.
 182 ///
 183 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
 184   raw_os_ostream RawOS(OS);
 185   print(RawOS, TM);
 186 }
 187
 188 void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
 189   switch (getType()) {
 190   case MachineOperand::MO_Register:
 191     if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
 192       OS << "%reg" << getReg();
 193     } else {
 194       // If the instruction is embedded into a basic block, we can find the
 195       // target info for the instruction.
 196       if (TM == 0)
 197         if (const MachineInstr *MI = getParent())
 198           if (const MachineBasicBlock *MBB = MI->getParent())
 199             if (const MachineFunction *MF = MBB->getParent())
 200               TM = &MF->getTarget();
 201
 202       if (TM)
 203         OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
 204       else
 205         OS << "%mreg" << getReg();
 206     }
 207
 208     if (getSubReg() != 0) {
 209       OS << ":" << getSubReg();
 210     }
 211
 212     if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
 213       OS << "<";
 214       bool NeedComma = false;
 215       if (isImplicit()) {
 216         if (NeedComma) OS << ",";
 217         OS << (isDef() ? "imp-def" : "imp-use");
 218         NeedComma = true;
 219       } else if (isDef()) {
 220         if (NeedComma) OS << ",";
 221         if (isEarlyClobber())
 222           OS << "earlyclobber,";
 223         OS << "def";
 224         NeedComma = true;
 225       }
 226       if (isKill() || isDead()) {
 227         if (NeedComma) OS << ",";
 228         if (isKill())  OS << "kill";
 229         if (isDead())  OS << "dead";
 230       }
 231       OS << ">";
 232     }
 233     break;
 234   case MachineOperand::MO_Immediate:
 235     OS << getImm();
 236     break;
 237   case MachineOperand::MO_FPImmediate:
 238     if (getFPImm()->getType() == Type::FloatTy) {
 239       OS << getFPImm()->getValueAPF().convertToFloat();
 240     } else {
 241       OS << getFPImm()->getValueAPF().convertToDouble();
 242     }
 243     break;
 244   case MachineOperand::MO_MachineBasicBlock:
 245     OS << "mbb<"
 246        << ((Value*)getMBB()->getBasicBlock())->getName()
 247        << "," << (void*)getMBB() << ">";
 248     break;
 249   case MachineOperand::MO_FrameIndex:
 250     OS << "<fi#" << getIndex() << ">";
 251     break;
 252   case MachineOperand::MO_ConstantPoolIndex:
 253     OS << "<cp#" << getIndex();
 254     if (getOffset()) OS << "+" << getOffset();
 255     OS << ">";
 256     break;
 257   case MachineOperand::MO_JumpTableIndex:
 258     OS << "<jt#" << getIndex() << ">";
 259     break;
 260   case MachineOperand::MO_GlobalAddress:
 261     OS << "<ga:" << ((Value*)getGlobal())->getName();
 262     if (getOffset()) OS << "+" << getOffset();
 263     OS << ">";
 264     break;
 265   case MachineOperand::MO_ExternalSymbol:
 266     OS << "<es:" << getSymbolName();
 267     if (getOffset()) OS << "+" << getOffset();
 268     OS << ">";
 269     break;
 270   default:
 271     assert(0 && "Unrecognized operand type");
 272   }
 273 }
 274
 275 //===----------------------------------------------------------------------===//
 276 // MachineMemOperand Implementation
 277 //===----------------------------------------------------------------------===//
 278
 279 MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
 280                                      int64_t o, uint64_t s, unsigned int a)
 281   : Offset(o), Size(s), V(v),
 282     Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
 283   assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
 284   assert((isLoad() || isStore()) && "Not a load/store!");
 285 }
 286
 287 /// Profile - Gather unique data for the object.
 288 ///
 289 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
 290   ID.AddInteger(Offset);
 291   ID.AddInteger(Size);
 292   ID.AddPointer(V);
 293   ID.AddInteger(Flags);
 294 }
 295
 296 //===----------------------------------------------------------------------===//
 297 // MachineInstr Implementation
 298 //===----------------------------------------------------------------------===//
 299
 300 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
 301 /// TID NULL and no operands.
 302 MachineInstr::MachineInstr()
 303   : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
 304   // Make sure that we get added to a machine basicblock
 305   LeakDetector::addGarbageObject(this);
 306 }
 307
 308 void MachineInstr::addImplicitDefUseOperands() {
 309   if (TID->ImplicitDefs)
 310     for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
 311       addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
 312   if (TID->ImplicitUses)
 313     for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
 314       addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
 315 }
 316
 317 /// MachineInstr ctor - This constructor create a MachineInstr and add the
 318 /// implicit operands. It reserves space for number of operands specified by
 319 /// TargetInstrDesc or the numOperands if it is not zero. (for
 320 /// instructions with variable number of operands).
 321 MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
 322   : TID(&tid), NumImplicitOps(0), Parent(0),
 323     debugLoc(DebugLoc::getUnknownLoc()) {
 324   if (!NoImp && TID->getImplicitDefs())
 325     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 326       NumImplicitOps++;
 327   if (!NoImp && TID->getImplicitUses())
 328     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 329       NumImplicitOps++;
 330   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 331   if (!NoImp)
 332     addImplicitDefUseOperands();
 333   // Make sure that we get added to a machine basicblock
 334   LeakDetector::addGarbageObject(this);
 335 }
 336
 337 /// MachineInstr ctor - As above, but with a DebugLoc.
 338 MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
 339                            bool NoImp)
 340   : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
 341   if (!NoImp && TID->getImplicitDefs())
 342     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 343       NumImplicitOps++;
 344   if (!NoImp && TID->getImplicitUses())
 345     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 346       NumImplicitOps++;
 347   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 348   if (!NoImp)
 349     addImplicitDefUseOperands();
 350   // Make sure that we get added to a machine basicblock
 351   LeakDetector::addGarbageObject(this);
 352 }
 353
 354 /// MachineInstr ctor - Work exactly the same as the ctor two above, except
 355 /// that the MachineInstr is created and added to the end of the specified
 356 /// basic block.
 357 ///
 358 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
 359   : TID(&tid), NumImplicitOps(0), Parent(0),
 360     debugLoc(DebugLoc::getUnknownLoc()) {
 361   assert(MBB && "Cannot use inserting ctor with null basic block!");
 362   if (TID->ImplicitDefs)
 363     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 364       NumImplicitOps++;
 365   if (TID->ImplicitUses)
 366     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 367       NumImplicitOps++;
 368   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 369   addImplicitDefUseOperands();
 370   // Make sure that we get added to a machine basicblock
 371   LeakDetector::addGarbageObject(this);
 372   MBB->push_back(this);  // Add instruction to end of basic block!
 373 }
 374
 375 /// MachineInstr ctor - As above, but with a DebugLoc.
 376 ///
 377 MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
 378                            const TargetInstrDesc &tid)
 379   : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
 380   assert(MBB && "Cannot use inserting ctor with null basic block!");
 381   if (TID->ImplicitDefs)
 382     for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
 383       NumImplicitOps++;
 384   if (TID->ImplicitUses)
 385     for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
 386       NumImplicitOps++;
 387   Operands.reserve(NumImplicitOps + TID->getNumOperands());
 388   addImplicitDefUseOperands();
 389   // Make sure that we get added to a machine basicblock
 390   LeakDetector::addGarbageObject(this);
 391   MBB->push_back(this);  // Add instruction to end of basic block!
 392 }
 393
 394 /// MachineInstr ctor - Copies MachineInstr arg exactly
 395 ///
 396 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
 397   : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
 398         debugLoc(MI.getDebugLoc()) {
 399   Operands.reserve(MI.getNumOperands());
 400
 401   // Add operands
 402   for (unsigned i = 0; i != MI.getNumOperands(); ++i)
 403     addOperand(MI.getOperand(i));
 404   NumImplicitOps = MI.NumImplicitOps;
 405
 406   // Add memory operands.
 407   for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
 408        j = MI.memoperands_end(); i != j; ++i)
 409     addMemOperand(MF, *i);
 410
 411   // Set parent to null.
 412   Parent = 0;
 413
 414   LeakDetector::addGarbageObject(this);
 415 }
 416
 417 MachineInstr::~MachineInstr() {
 418   LeakDetector::removeGarbageObject(this);
 419   assert(MemOperands.empty() &&
 420          "MachineInstr being deleted with live memoperands!");
 421 #ifndef NDEBUG
 422   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
 423     assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
 424     assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
 425            "Reg operand def/use list corrupted");
 426   }
 427 #endif
 428 }
 429
 430 /// getRegInfo - If this instruction is embedded into a MachineFunction,
 431 /// return the MachineRegisterInfo object for the current function, otherwise
 432 /// return null.
 433 MachineRegisterInfo *MachineInstr::getRegInfo() {
 434   if (MachineBasicBlock *MBB = getParent())
 435     return &MBB->getParent()->getRegInfo();
 436   return 0;
 437 }
 438
 439 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
 440 /// this instruction from their respective use lists.  This requires that the
 441 /// operands already be on their use lists.
 442 void MachineInstr::RemoveRegOperandsFromUseLists() {
 443   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
 444     if (Operands[i].isReg())
 445       Operands[i].RemoveRegOperandFromRegInfo();
 446   }
 447 }
 448
 449 /// AddRegOperandsToUseLists - Add all of the register operands in
 450 /// this instruction from their respective use lists.  This requires that the
 451 /// operands not be on their use lists yet.
 452 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
 453   for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
 454     if (Operands[i].isReg())
 455       Operands[i].AddRegOperandToRegInfo(&RegInfo);
 456   }
 457 }
 458
 459
 460 /// addOperand - Add the specified operand to the instruction.  If it is an
 461 /// implicit operand, it is added to the end of the operand list.  If it is
 462 /// an explicit operand it is added at the end of the explicit operand list
 463 /// (before the first implicit operand).
 464 void MachineInstr::addOperand(const MachineOperand &Op) {
 465   bool isImpReg = Op.isReg() && Op.isImplicit();
 466   assert((isImpReg || !OperandsComplete()) &&
 467          "Trying to add an operand to a machine instr that is already done!");
 468
 469   MachineRegisterInfo *RegInfo = getRegInfo();
 470
 471   // If we are adding the operand to the end of the list, our job is simpler.
 472   // This is true most of the time, so this is a reasonable optimization.
 473   if (isImpReg || NumImplicitOps == 0) {
 474     // We can only do this optimization if we know that the operand list won't
 475     // reallocate.
 476     if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
 477       Operands.push_back(Op);
 478
 479       // Set the parent of the operand.
 480       Operands.back().ParentMI = this;
 481
 482       // If the operand is a register, update the operand's use list.
 483       if (Op.isReg())
 484         Operands.back().AddRegOperandToRegInfo(RegInfo);
 485       return;
 486     }
 487   }
 488
 489   // Otherwise, we have to insert a real operand before any implicit ones.
 490   unsigned OpNo = Operands.size()-NumImplicitOps;
 491
 492   // If this instruction isn't embedded into a function, then we don't need to
 493   // update any operand lists.
 494   if (RegInfo == 0) {
 495     // Simple insertion, no reginfo update needed for other register operands.
 496     Operands.insert(Operands.begin()+OpNo, Op);
 497     Operands[OpNo].ParentMI = this;
 498
 499     // Do explicitly set the reginfo for this operand though, to ensure the
 500     // next/prev fields are properly nulled out.
 501     if (Operands[OpNo].isReg())
 502       Operands[OpNo].AddRegOperandToRegInfo(0);
 503
 504   } else if (Operands.size()+1 <= Operands.capacity()) {
 505     // Otherwise, we have to remove register operands from their register use
 506     // list, add the operand, then add the register operands back to their use
 507     // list.  This also must handle the case when the operand list reallocates
 508     // to somewhere else.
 509
 510     // If insertion of this operand won't cause reallocation of the operand
 511     // list, just remove the implicit operands, add the operand, then re-add all
 512     // the rest of the operands.
 513     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
 514       assert(Operands[i].isReg() && "Should only be an implicit reg!");
 515       Operands[i].RemoveRegOperandFromRegInfo();
 516     }
 517
 518     // Add the operand.  If it is a register, add it to the reg list.
 519     Operands.insert(Operands.begin()+OpNo, Op);
 520     Operands[OpNo].ParentMI = this;
 521
 522     if (Operands[OpNo].isReg())
 523       Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
 524
 525     // Re-add all the implicit ops.
 526     for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
 527       assert(Operands[i].isReg() && "Should only be an implicit reg!");
 528       Operands[i].AddRegOperandToRegInfo(RegInfo);
 529     }
 530   } else {
 531     // Otherwise, we will be reallocating the operand list.  Remove all reg
 532     // operands from their list, then readd them after the operand list is
 533     // reallocated.
 534     RemoveRegOperandsFromUseLists();
 535
 536     Operands.insert(Operands.begin()+OpNo, Op);
 537     Operands[OpNo].ParentMI = this;
 538
 539     // Re-add all the operands.
 540     AddRegOperandsToUseLists(*RegInfo);
 541   }
 542 }
 543
 544 /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
 545 /// fewer operand than it started with.
 546 ///
 547 void MachineInstr::RemoveOperand(unsigned OpNo) {
 548   assert(OpNo < Operands.size() && "Invalid operand number");
 549
 550   // Special case removing the last one.
 551   if (OpNo == Operands.size()-1) {
 552     // If needed, remove from the reg def/use list.
 553     if (Operands.back().isReg() && Operands.back().isOnRegUseList())
 554       Operands.back().RemoveRegOperandFromRegInfo();
 555
 556     Operands.pop_back();
 557     return;
 558   }
 559
 560   // Otherwise, we are removing an interior operand.  If we have reginfo to
 561   // update, remove all operands that will be shifted down from their reg lists,
 562   // move everything down, then re-add them.
 563   MachineRegisterInfo *RegInfo = getRegInfo();
 564   if (RegInfo) {
 565     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
 566       if (Operands[i].isReg())
 567         Operands[i].RemoveRegOperandFromRegInfo();
 568     }
 569   }
 570
 571   Operands.erase(Operands.begin()+OpNo);
 572
 573   if (RegInfo) {
 574     for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
 575       if (Operands[i].isReg())
 576         Operands[i].AddRegOperandToRegInfo(RegInfo);
 577     }
 578   }
 579 }
 580
 581 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
 582 /// referencing arbitrary storage.
 583 void MachineInstr::addMemOperand(MachineFunction &MF,
 584                                  const MachineMemOperand &MO) {
 585   MemOperands.push_back(MO);
 586 }
 587
 588 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
 589 void MachineInstr::clearMemOperands(MachineFunction &MF) {
 590   MemOperands.clear();
 591 }
 592
 593
 594 /// removeFromParent - This method unlinks 'this' from the containing basic
 595 /// block, and returns it, but does not delete it.
 596 MachineInstr *MachineInstr::removeFromParent() {
 597   assert(getParent() && "Not embedded in a basic block!");
 598   getParent()->remove(this);
 599   return this;
 600 }
 601
 602
 603 /// eraseFromParent - This method unlinks 'this' from the containing basic
 604 /// block, and deletes it.
 605 void MachineInstr::eraseFromParent() {
 606   assert(getParent() && "Not embedded in a basic block!");
 607   getParent()->erase(this);
 608 }
 609
 610
 611 /// OperandComplete - Return true if it's illegal to add a new operand
 612 ///
 613 bool MachineInstr::OperandsComplete() const {
 614   unsigned short NumOperands = TID->getNumOperands();
 615   if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
 616     return true;  // Broken: we have all the operands of this instruction!
 617   return false;
 618 }
 619
 620 /// getNumExplicitOperands - Returns the number of non-implicit operands.
 621 ///
 622 unsigned MachineInstr::getNumExplicitOperands() const {
 623   unsigned NumOperands = TID->getNumOperands();
 624   if (!TID->isVariadic())
 625     return NumOperands;
 626
 627   for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
 628     const MachineOperand &MO = getOperand(i);
 629     if (!MO.isReg() || !MO.isImplicit())
 630       NumOperands++;
 631   }
 632   return NumOperands;
 633 }
 634
 635
 636 /// isLabel - Returns true if the MachineInstr represents a label.
 637 ///
 638 bool MachineInstr::isLabel() const {
 639   return getOpcode() == TargetInstrInfo::DBG_LABEL ||
 640          getOpcode() == TargetInstrInfo::EH_LABEL ||
 641          getOpcode() == TargetInstrInfo::GC_LABEL;
 642 }
 643
 644 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
 645 ///
 646 bool MachineInstr::isDebugLabel() const {
 647   return getOpcode() == TargetInstrInfo::DBG_LABEL;
 648 }
 649
 650 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
 651 /// the specific register or -1 if it is not found. It further tightening
 652 /// the search criteria to a use that kills the register if isKill is true.
 653 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
 654                                           const TargetRegisterInfo *TRI) const {
 655   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
 656     const MachineOperand &MO = getOperand(i);
 657     if (!MO.isReg() || !MO.isUse())
 658       continue;
 659     unsigned MOReg = MO.getReg();
 660     if (!MOReg)
 661       continue;
 662     if (MOReg == Reg ||
 663         (TRI &&
 664          TargetRegisterInfo::isPhysicalRegister(MOReg) &&
 665          TargetRegisterInfo::isPhysicalRegister(Reg) &&
 666          TRI->isSubRegister(MOReg, Reg)))
 667       if (!isKill || MO.isKill())
 668         return i;
 669   }
 670   return -1;
 671 }
 672
 673 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
 674 /// the specified register or -1 if it is not found. If isDead is true, defs
 675 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
 676 /// also checks if there is a def of a super-register.
 677 int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
 678                                           const TargetRegisterInfo *TRI) const {
 679   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
 680     const MachineOperand &MO = getOperand(i);
 681     if (!MO.isReg() || !MO.isDef())
 682       continue;
 683     unsigned MOReg = MO.getReg();
 684     if (MOReg == Reg ||
 685         (TRI &&
 686          TargetRegisterInfo::isPhysicalRegister(MOReg) &&
 687          TargetRegisterInfo::isPhysicalRegister(Reg) &&
 688          TRI->isSubRegister(MOReg, Reg)))
 689       if (!isDead || MO.isDead())
 690         return i;
 691   }
 692   return -1;
 693 }
 694
 695 /// findFirstPredOperandIdx() - Find the index of the first operand in the
 696 /// operand list that is used to represent the predicate. It returns -1 if
 697 /// none is found.
 698 int MachineInstr::findFirstPredOperandIdx() const {
 699   const TargetInstrDesc &TID = getDesc();
 700   if (TID.isPredicable()) {
 701     for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
 702       if (TID.OpInfo[i].isPredicate())
 703         return i;
 704   }
 705
 706   return -1;
 707 }
 708
 709 /// isRegTiedToUseOperand - Given the index of a register def operand,
 710 /// check if the register def is tied to a source operand, due to either
 711 /// two-address elimination or inline assembly constraints. Returns the
 712 /// first tied use operand index by reference is UseOpIdx is not null.
 713 bool MachineInstr::
 714 isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
 715   if (getOpcode() == TargetInstrInfo::INLINEASM) {
 716     assert(DefOpIdx >= 2);
 717     const MachineOperand &MO = getOperand(DefOpIdx);
 718     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
 719       return false;
 720     // Determine the actual operand no corresponding to this index.
 721     unsigned DefNo = 0;
 722     for (unsigned i = 1, e = getNumOperands(); i < e; ) {
 723       const MachineOperand &FMO = getOperand(i);
 724       assert(FMO.isImm());
 725       // Skip over this def.
 726       i += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
 727       if (i > DefOpIdx)
 728         break;
 729       ++DefNo;
 730     }
 731     for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
 732       const MachineOperand &FMO = getOperand(i);
 733       if (!FMO.isImm())
 734         continue;
 735       if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
 736         continue;
 737       unsigned Idx;
 738       if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
 739           Idx == DefNo) {
 740         if (UseOpIdx)
 741           *UseOpIdx = (unsigned)i + 1;
 742         return true;
 743       }
 744     }
 745   }
 746
 747   assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
 748   const TargetInstrDesc &TID = getDesc();
 749   for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
 750     const MachineOperand &MO = getOperand(i);
 751     if (MO.isReg() && MO.isUse() &&
 752         TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
 753       if (UseOpIdx)
 754         *UseOpIdx = (unsigned)i;
 755       return true;
 756     }
 757   }
 758   return false;
 759 }
 760
 761 /// isRegTiedToDefOperand - Return true if the operand of the specified index
 762 /// is a register use and it is tied to an def operand. It also returns the def
 763 /// operand index by reference.
 764 bool MachineInstr::
 765 isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
 766   if (getOpcode() == TargetInstrInfo::INLINEASM) {
 767     const MachineOperand &MO = getOperand(UseOpIdx);
 768     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
 769       return false;
 770     assert(UseOpIdx > 0);
 771     const MachineOperand &UFMO = getOperand(UseOpIdx-1);
 772     if (!UFMO.isImm())
 773       return false;  // Must be physreg uses.
 774     unsigned DefNo;
 775     if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
 776       if (!DefOpIdx)
 777         return true;
 778
 779       unsigned DefIdx = 1;
 780       // Remember to adjust the index. First operand is asm string, then there
 781       // is a flag for each.
 782       while (DefNo) {
 783         const MachineOperand &FMO = getOperand(DefIdx);
 784         assert(FMO.isImm());
 785         // Skip over this def.
 786         DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
 787         --DefNo;
 788       }
 789       *DefOpIdx = DefIdx+1;
 790       return true;
 791     }
 792     return false;
 793   }
 794
 795   const TargetInstrDesc &TID = getDesc();
 796   if (UseOpIdx >= TID.getNumOperands())
 797     return false;
 798   const MachineOperand &MO = getOperand(UseOpIdx);
 799   if (!MO.isReg() || !MO.isUse())
 800     return false;
 801   int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
 802   if (DefIdx == -1)
 803     return false;
 804   if (DefOpIdx)
 805     *DefOpIdx = (unsigned)DefIdx;
 806   return true;
 807 }
 808
 809 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
 810 ///
 811 void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
 812   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 813     const MachineOperand &MO = MI->getOperand(i);
 814     if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
 815       continue;
 816     for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
 817       MachineOperand &MOp = getOperand(j);
 818       if (!MOp.isIdenticalTo(MO))
 819         continue;
 820       if (MO.isKill())
 821         MOp.setIsKill();
 822       else
 823         MOp.setIsDead();
 824       break;
 825     }
 826   }
 827 }
 828
 829 /// copyPredicates - Copies predicate operand(s) from MI.
 830 void MachineInstr::copyPredicates(const MachineInstr *MI) {
 831   const TargetInstrDesc &TID = MI->getDesc();
 832   if (!TID.isPredicable())
 833     return;
 834   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 835     if (TID.OpInfo[i].isPredicate()) {
 836       // Predicated operands must be last operands.
 837       addOperand(MI->getOperand(i));
 838     }
 839   }
 840 }
 841
 842 /// isSafeToMove - Return true if it is safe to move this instruction. If
 843 /// SawStore is set to true, it means that there is a store (or call) between
 844 /// the instruction's location and its intended destination.
 845 bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
 846                                 bool &SawStore) const {
 847   // Ignore stuff that we obviously can't move.
 848   if (TID->mayStore() || TID->isCall()) {
 849     SawStore = true;
 850     return false;
 851   }
 852   if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
 853     return false;
 854
 855   // See if this instruction does a load.  If so, we have to guarantee that the
 856   // loaded value doesn't change between the load and the its intended
 857   // destination. The check for isInvariantLoad gives the targe the chance to
 858   // classify the load as always returning a constant, e.g. a constant pool
 859   // load.
 860   if (TID->mayLoad() && !TII->isInvariantLoad(this))
 861     // Otherwise, this is a real load.  If there is a store between the load and
 862     // end of block, or if the laod is volatile, we can't move it.
 863     return !SawStore && !hasVolatileMemoryRef();
 864
 865   return true;
 866 }
 867
 868 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
 869 /// instruction which defined the specified register instead of copying it.
 870 bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
 871                                  unsigned DstReg) const {
 872   bool SawStore = false;
 873   if (!getDesc().isRematerializable() ||
 874       !TII->isTriviallyReMaterializable(this) ||
 875       !isSafeToMove(TII, SawStore))
 876     return false;
 877   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
 878     const MachineOperand &MO = getOperand(i);
 879     if (!MO.isReg())
 880       continue;
 881     // FIXME: For now, do not remat any instruction with register operands.
 882     // Later on, we can loosen the restriction is the register operands have
 883     // not been modified between the def and use. Note, this is different from
 884     // MachineSink because the code is no longer in two-address form (at least
 885     // partially).
 886     if (MO.isUse())
 887       return false;
 888     else if (!MO.isDead() && MO.getReg() != DstReg)
 889       return false;
 890   }
 891   return true;
 892 }
 893
 894 /// hasVolatileMemoryRef - Return true if this instruction may have a
 895 /// volatile memory reference, or if the information describing the
 896 /// memory reference is not available. Return false if it is known to
 897 /// have no volatile memory references.
 898 bool MachineInstr::hasVolatileMemoryRef() const {
 899   // An instruction known never to access memory won't have a volatile access.
 900   if (!TID->mayStore() &&
 901       !TID->mayLoad() &&
 902       !TID->isCall() &&
 903       !TID->hasUnmodeledSideEffects())
 904     return false;
 905
 906   // Otherwise, if the instruction has no memory reference information,
 907   // conservatively assume it wasn't preserved.
 908   if (memoperands_empty())
 909     return true;
 910
 911   // Check the memory reference information for volatile references.
 912   for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
 913        E = memoperands_end(); I != E; ++I)
 914     if (I->isVolatile())
 915       return true;
 916
 917   return false;
 918 }
 919
 920 void MachineInstr::dump() const {
 921   cerr << "  " << *this;
 922 }
 923
 924 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
 925   raw_os_ostream RawOS(OS);
 926   print(RawOS, TM);
 927 }
 928
 929 void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
 930   // Specialize printing if op#0 is definition
 931   unsigned StartOp = 0;
 932   if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
 933     getOperand(0).print(OS, TM);
 934     OS << " = ";
 935     ++StartOp;   // Don't print this operand again!
 936   }
 937
 938   OS << getDesc().getName();
 939
 940   for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
 941     if (i != StartOp)
 942       OS << ",";
 943     OS << " ";
 944     getOperand(i).print(OS, TM);
 945   }
 946
 947   if (!memoperands_empty()) {
 948     OS << ", Mem:";
 949     for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
 950          e = memoperands_end(); i != e; ++i) {
 951       const MachineMemOperand &MRO = *i;
 952       const Value *V = MRO.getValue();
 953
 954       assert((MRO.isLoad() || MRO.isStore()) &&
 955              "SV has to be a load, store or both.");
 956
 957       if (MRO.isVolatile())
 958         OS << "Volatile ";
 959
 960       if (MRO.isLoad())
 961         OS << "LD";
 962       if (MRO.isStore())
 963         OS << "ST";
 964
 965       OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
 966
 967       if (!V)
 968         OS << "<unknown>";
 969       else if (!V->getName().empty())
 970         OS << V->getName();
 971       else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
 972         PSV->print(OS);
 973       } else
 974         OS << V;
 975
 976       OS << " + " << MRO.getOffset() << "]";
 977     }
 978   }
 979
 980   if (!debugLoc.isUnknown()) {
 981     const MachineFunction *MF = getParent()->getParent();
 982     DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
 983     DICompileUnit CU(DLT.CompileUnit);
 984     std::string Dir, Fn;
 985     OS << " [dbg: "
 986        << CU.getDirectory(Dir) << '/' << CU.getFilename(Fn) << ","
 987        << DLT.Line << ","
 988        << DLT.Col  << "]";
 989   }
 990
 991   OS << "\n";
 992 }
 993
 994 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
 995                                      const TargetRegisterInfo *RegInfo,
 996                                      bool AddIfNotFound) {
 997   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
 998   bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
 999   bool Found = false;
1000   SmallVector<unsigned,4> DeadOps;
1001   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1002     MachineOperand &MO = getOperand(i);
1003     if (!MO.isReg() || !MO.isUse())
1004       continue;
1005     unsigned Reg = MO.getReg();
1006     if (!Reg)
1007       continue;
1008
1009     if (Reg == IncomingReg) {
1010       if (!Found) {
1011         if (MO.isKill())
1012           // The register is already marked kill.
1013           return true;
1014         MO.setIsKill();
1015         Found = true;
1016       }
1017     } else if (hasAliases && MO.isKill() &&
1018                TargetRegisterInfo::isPhysicalRegister(Reg)) {
1019       // A super-register kill already exists.
1020       if (RegInfo->isSuperRegister(IncomingReg, Reg))
1021         return true;
1022       if (RegInfo->isSubRegister(IncomingReg, Reg))
1023         DeadOps.push_back(i);
1024     }
1025   }
1026
1027   // Trim unneeded kill operands.
1028   while (!DeadOps.empty()) {
1029     unsigned OpIdx = DeadOps.back();
1030     if (getOperand(OpIdx).isImplicit())
1031       RemoveOperand(OpIdx);
1032     else
1033       getOperand(OpIdx).setIsKill(false);
1034     DeadOps.pop_back();
1035   }
1036
1037   // If not found, this means an alias of one of the operands is killed. Add a
1038   // new implicit operand if required.
1039   if (!Found && AddIfNotFound) {
1040     addOperand(MachineOperand::CreateReg(IncomingReg,
1041                                          false /*IsDef*/,
1042                                          true  /*IsImp*/,
1043                                          true  /*IsKill*/));
1044     return true;
1045   }
1046   return Found;
1047 }
1048
1049 bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1050                                    const TargetRegisterInfo *RegInfo,
1051                                    bool AddIfNotFound) {
1052   bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1053   bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1054   bool Found = false;
1055   SmallVector<unsigned,4> DeadOps;
1056   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1057     MachineOperand &MO = getOperand(i);
1058     if (!MO.isReg() || !MO.isDef())
1059       continue;
1060     unsigned Reg = MO.getReg();
1061     if (!Reg)
1062       continue;
1063
1064     if (Reg == IncomingReg) {
1065       if (!Found) {
1066         if (MO.isDead())
1067           // The register is already marked dead.
1068           return true;
1069         MO.setIsDead();
1070         Found = true;
1071       }
1072     } else if (hasAliases && MO.isDead() &&
1073                TargetRegisterInfo::isPhysicalRegister(Reg)) {
1074       // There exists a super-register that's marked dead.
1075       if (RegInfo->isSuperRegister(IncomingReg, Reg))
1076         return true;
1077       if (RegInfo->getSubRegisters(IncomingReg) &&
1078           RegInfo->getSuperRegisters(Reg) &&
1079           RegInfo->isSubRegister(IncomingReg, Reg))
1080         DeadOps.push_back(i);
1081     }
1082   }
1083
1084   // Trim unneeded dead operands.
1085   while (!DeadOps.empty()) {
1086     unsigned OpIdx = DeadOps.back();
1087     if (getOperand(OpIdx).isImplicit())
1088       RemoveOperand(OpIdx);
1089     else
1090       getOperand(OpIdx).setIsDead(false);
1091     DeadOps.pop_back();
1092   }
1093
1094   // If not found, this means an alias of one of the operands is dead. Add a
1095   // new implicit operand if required.
1096   if (!Found && AddIfNotFound) {
1097     addOperand(MachineOperand::CreateReg(IncomingReg,
1098                                          true  /*IsDef*/,
1099                                          true  /*IsImp*/,
1100                                          false /*IsKill*/,
1101                                          true  /*IsDead*/));
1102     return true;
1103   }
1104   return Found;
1105 }